TOOL FLOW
&
Real-world Applications
CONTENTS
1. Simulation Tools
1.1 VCS
1.2 Xcelium
1.3 Questa-sim
2. Synthesis Tools
2.1 Design Compiler (DC)
2.2 Genus
3. STA Tools (Static Timing Analysis)
3.1 Prime Time
4. Lint & CDC Tools
4.1 SpyGlass
4.2 JasperGold
5. RTL IP Examples
5.1 FIFO
5.2 RAM
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1. Simulation Tools
Simulation tools are used to compile, elaborate, simulate, debug RTL code (verilog/system verilog) +
test-bench.
1.1 VCS (Synopsys)
Purpose: RTL simulation, coverage analysis, debug.
Basic flow:
View
Compile Elaborate Simulate
Waves
Common Commands
Compile
vcs -full64 -sverilog tb.v dut.v +lint=all
Compile + Elaborate + Simulate
vcs -full64 -debug_access +all [Link] [Link] -o simv
./simv
Enable Waveform Dump
initial begin
$dumpfile(“[Link]”);
$dumvars(0, tb);
end
Coverage
vcs -cm line+cond_fsm+branch_tgl [Link] [Link]
./simv -cm dir=./cov
urg -dir cov # Generate HTML report
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Real-world Applications
AREA REAL-WORLD USE
Pre-silicon Verification Verify RTL correctness using test-benches, UVM
environments.
Regression testing Companies tun 10,000+ tests nightly using VCS.
Coverage-driven verification Functional +code coverage for SoCs, CPUs,
DSPs.
Debugging complex designs Used by verification teams for pipeline, cache,
AXI/AHB/PCIe, DMA designs.
Power-aware simulation UPF/CPF based low-power SoC verification.
Gate-level simulation (GLS) Post-synthesus verification for timing/functional
correctness.
Used by: Intel, Qualcomm, NVIDIA, AMD, Broadcom, Synopsys.
1.2 Xcelium (Cadence)
Purpose: Fast SV/UVM simulation, coverage, assertions.
Compile+Elaborate+Simulate
xrun -sv [Link] [Link]
Enable Coverage
xrun -coverage all -covoverwrite [Link] [Link]
View Waves
Xcelium uses SHM waves:
xrun [Link] +define+DUMP
simvision [Link]
Real-World Applications
AREA REAL-WORLD USE
High-speed simulation Fastest simulator used for large SoCs (5+ million
gates).
UVM verification Used for functional verification of moderm
blocks, GPU pipelines, automotive ECUs.
Mixed-signal verification Works with spectre for AMS simulation.
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Low-power verification UPF-based SoC power sequencing validation.
RTL+Testbench co-simulation Large verification environments (DSP, memory
controllers).
Used by: Samsung, STMicroelectronics, Texas Instruments, Cadence clients.
1.3 Questa-Sim (Siemens/Mentor)
Purpose: RTL simulation, debugging (GUI), coverage.
Compile
vlog [Link] [Link]
Simulate
vsim [Link]
run -all
Enable GUI
vsim -gui [Link]
Add wave
Inside GUI console:
add wave sim:/tb/*
Code coverage
vsim -coverage tb -c -do “run -all: coverage save [Link]; exit”
Real-World Applications
AREA REAL-WORLD USE
Debug-heavy verification Best GUI for waveform, objects, signals, variable
tracking.
FPGA+ASIC simulation Widely used for xilinx/intel FPGA verification
Assertion-based verification SVA/PSL for bus protocols (AXI,AHB, PCIe)
Hardware-assisted verification Connects with emulators like Veloce
RTL coverage analysis Line, toggle, FSM, branch coverage reports.
Used by: Siemens EDA customers, aerospace, automotive companies.
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2. Synthesis Tools (RTL – Netlist)
2.1 Design Compiler (synopsys DC)
Purpose: covert RTL – gate-level netlist
Typical Flow
read file – set constarints – compile – generate report – write netlist
DC Commands
Start DC shell
dc_shell -gui
Read RTL
read_verilog dut.v
Set Constraints
create_clock -period 10 [get_ports clk]
set_input_delay 2 [get_ports in*]
set_output_delay 2 [get_ports out*]
Compile
compile_ultra
Reports
report_timing
report_area
report_power
Write output
write -format verilog -output
dut_netlist.v
write_sdc [Link]
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Real-World Applications
AREA REAL-WORLD USE
Gate-level netlist generation Converts RTL into optimized standard cell gates.
Timing closure Meeting setup/hold timing for ASIC SoCs.
Power optimization Multi-Vt, clock gating, logic restructuring.
Area optimization Important for mobile/IoT chips where area=cost.
Constraint-based optimization SDC-based real-time optimization for PPA.
Multi-core SOC synthesizing Millions of gates synthesized daily in industry.
Used by: Apple, Qualcomm, MediaTek, Nvidia, AMD.
2.2 Genus (Cadence)
purpose: Ultra-fast RTL systhesis.
Basic flow
read_hdl dut.v
read_sdc [Link]
elaborate
synthesize -to_mapped
write_hdl > dut_netlist.v
Real-World Applications
AREA REAL-WORLD USE
High-speed synthesis Very fast compile times for large, complex
designs.
Physical-aware sysnthesis Works with Innovus for PnR flow
Power-aware synthesis Reduces dynamic + static power in
IOT/automotive chips.
RTL-to-GDS flow Part of cadence full silicon development pipeline.
Advanced nodes synthesis (7nm, 5nm, 3nm) Used in cutting-edge chips
Used by: TSMC ecosystem, NXP, cadence customers.
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3. STA Tools (Static Timing Analysis)
3.1 Prime Time (Synopsys)
Used after synthesis to check setup/hold timing, paths, slack.
Basic commands
startPT
pt_shell
Read design
read_verilog dut_netlist.v
read_sdc [Link]
read_liberty [Link]
Write reports
report_power > [Link]
report_timing > [Link]
Real-World Applications
AREA REAL-WORLD USE
Timing signoff Finl timing check before sending chip to
fabrication.
Setup/hold analysis Validates clock speed requirements.
PVT corner analysis Checks timing at slow/fast process corners.
Clock tree verification Ensures skew/jitter within limits.
Path analysis Critical path detection in CPUs/SoCs.
Multi-mode multi-corner Automotive and aerospace safety chips.
Used by: all tier-1 semiconductor companies worldwide.
4. Lint & CDC Tools
Lint ensures RTL quality.
CDC checks asynchronous clock domain crossing.
4.1 SpyGlass (Synopsys)
Used for Lint + CDC + Reset checks + RTL quality.
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Basic flow
spyglass -project [Link]
Project file example
read_file { dut.v }
set_option top_module dut
run_goal lint/lint_rtl
Open GUI
spyglass_gui
Real-World Applications
AREA REAL-WORLD USE
Lint (RTL quality checks) Detects unreachable code, width mismatch,
unused signals.
CDC (clock domain crossing) Ensures metastability-safe synchronization.
Reset domain checks Clean reset release logic for safety-critical chips
DFT linting Ensures design is scan-chain friendly
RTL dtyle guide enforcements Coding rules for large teams
Used by: Automotive SoCs, 5G modems, microcontrollers, GPU blocks, networking ASICs.
4.2 JasperGold (Cadence)
Formal verification, CDC analysis.
CDC Mode
jaspergold -batch cdc_run.tcl
Basic Tcl file
read_design dut.v
set_top dut
run_cdc
report_cdc > cdc_report.txt
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Real-World Applications
AREA REAL-WORLD USE
Formal verification Mathematically proves design correctness.
Property checking (SVA) Ensures protocol compliance (AXI/PCIE/AHB)
CDC formal checks Detects CDC, RDC, glitch paths.
X-propagation checks Avoids ‘X’ explosion in simulation.
Sequential equivalence checking RTL vs netlist comparison after synthesis.
Bug hunting Finds bugs unreachable by simulation.
Used by: Intel, AMD, Apple, Cadence customers.
RTL IP Examples
Synchronous FIFO RTL code:
module sync_fifo #(parameter width=4,
parameter depth=7,
parameter addr=4) (input [width-1:0] din,
input clk,rst,we,re,
output reg [width-1:0] dout,
output full,empty);
reg [addr-1:0]wptr,rptr;
reg [width-1:0] mem [depth-1:0];
integer i;
//write oper
always@(posedge clk)
begin
if(rst)
begin
wptr<=4'b0;
for(i=0;i<depth;i=i+1)
mem[i]<=4'b0;
end
else if(we && !full)
begin
mem[wptr[2:0]]<=din;
wptr<=wptr+4'b1;
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end
end
//read oper
always@(posedge clk)
begin
if(rst)
begin
rptr<=4'b0;
dout<=4'b0;
end
else if(re && !empty)
begin
dout<=mem[rptr[2:0]];
rptr<=rptr+4'b1;
end
end
//output
assign empty = {wptr == rptr} ? 1'b1 : 1'b0;
assign full = {wptr == {!rptr[3],rptr[2:0]}} ? 1'b1 : 1'b0;
endmodule
RAM RTL code:
module sync_ram_16to8#(parameter depth=16, // Location size
parameter width=8, // Data Size
parameter addr_bus=4 // Address Size
) (input [width-1:0] din,
input clk,
input rst,
input [addr_bus-1:0] waddr,
input [addr_bus-1:0] raddr,
input we,
input re,
output reg [width-1:0]dout);
reg [width-1:0] mem [depth-1:0]; // 2D Memeory
integer i;
always@(posedge clk)
begin
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if(rst)
begin
dout<=8'b0;
for(i=0;i<16;i=i+1)
mem[i]<=8'b0;
end
else
begin
if(we)
mem[waddr]<=din;
else
mem[waddr]<=mem[waddr];
if(re)
dout<=mem[raddr];
else
dout<=dout;
end
end
endmodule
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