Basics of Verilog
CONTENTS
History of Verilog
Introduction to
Verilog
Abstraction
Hierarchical Design
Verilog Syntax
Verilog Module
Interview Question
1
aman nehra
Basics of Verilog
1. History of Verilog :
➢ 1984–85: Phil Moorby created Verilog at Gateway Design Automation.
➢ 1989: Cadence bought Gateway and took control of Verilog.
➢ 1995: Verilog became an official IEEE standard (IEEE 1364).
➢ 2001 & 2005: Updated versions Verilog-2001 & 2005 were released.
➢ 2005 onward: Accellera and IEEE together maintain Verilog and develop SystemVerilog (IEEE 1800),
which is the advanced version of Verilog.
2. Introduction of Verilog : Verilog is a hardware description language used to describe digital systems at
various levels of abstraction. It supports reg and wire data types. Verilog is case-sensitive and its syntax is
similar to the C language. Verilog designs are written inside modules, and its testbenchs are generally linear in
nature. The file extension for Verilog code is .v, and it is less complex compared to many other HDLs.
2.1 Real-life example : Verilog is widely used in CPU/SoC design, memory design (RAM, ROM, cache),
communication protocol implementation (UART, SPI, I2C, AXI, AHB, APB), and ASIC design for complex digital
chips.
2.2 Application areas of Verilog : Verilog is used in ASIC design, FPGA design, PLDs (Programmable Logic
Devices), and in designing standard digital components and IP blocks.
2
aman nehra
Basics of Verilog
2.3 Application Areas of Synthesis : Synthesis is used in converting RTL to gate-level netlists, optimizing
area, timing, and power, implementing designs on ASIC/FPGA, performing design rule checks, and generating
netlists for physical design.
2.4 Application Areas of Verification : Verification is used to check functional correctness of RTL, validate
communication protocols, ensure design reliability, perform coverage analysis, detect bugs before tape-out, and
build reusable testbench environments using SystemVerilog/UVM.
2.5 Comparison Table :
[Link] Features Verilog VHDL System Verilog UVM
0 Definition Verilog is a VHDL is a language SystemVerilog is a UVM is a standardized
hardware used to write and hardware verification framework
description design digital description and used to build reusable and
language circuits, similar to verification structured testbench
used to programming but for language used for environments.
describe hardware. both RTL design
digital and functional
systems at verification.
various levels
of
abstraction.
1 Purpose Hardware Hardware design Design + Verification methodology
design (RTL) (RTL) Verification
3
aman nehra
Basics of Verilog
2 Style C-like syntax Ada-like syntax C + OOP mix Full object-oriented
3 Testbench Simple, Simple, process- Class-based TB Component-based TB
module- based
based
4 File .v .vhd /.vhdl .sv .sv
Extension
5 Best For RTL coding Safety-critical design RTL + Testbench + Functional verification
SVA
6 Example AND gate, ALU, state machines AXI/APB interface, Verification of USB, PCIe,
counter, mux, for industrial & FIFO with AXI, DDR, SPI/I2C
flip-flop safety-critical control assertions, Class- controllers
systems based TB
3. Abstraction:
(a) Circuit Level :
• Lowest level abstraction using CMOS transistors (PMOS + NMOS).
• Describes pull-up and pull-down networks.
• Example: CMOS implementation of basic gates.
(b) Gate Level :
• Uses logic gates like AND, OR, NOT, NAND, NOR.
• Represents circuits using predefined primitives.
4
aman nehra
Basics of Verilog
• Example: Y = A & B.
(c) Data Flow Level (RTL) :
• Register Transfer Level representation.
• Uses continuous assignments (assign).
• Example: Y = (A & B) | C.
(d) Behavioral Level :
• Highest level of abstraction in Verilog.
• Uses always blocks to describe behavior.
• Focuses on functionality, not structure.
• Example: if-else, case statements.
4. Hierarchical Design : Complex designs are divided into multiple levels of hierarchy. Helps in design reuse,
readability, and easier debugging.
4.1 Bottom-Up Approach :
• Design starts from lowest level components such as transistors and basic gates.
• Small modules are created first and later combined to form bigger modules.
• Used when basic reusable building blocks are already available.
• Example: Transistor → AND Gate → Half Adder → Full Adder
4.2 Top-Down Approach :
• Design begins from the top-most system level.
• The system is divided into sub-modules and refined step-by-step.
• Most commonly used method in ASIC and SoC design.
• Example: Full Adder → 2 Half Adders + OR Gate
5
aman nehra
Basics of Verilog
5. Verilog Syntax :
(a) Keywords: Verilog keywords are written in lowercase (module, input, output, assign).
(b) Identifiers: Case-sensitive.
(c) Allowed characters: A–Z, a–z, 0–9, underscore (_), dollar sign ($).
(d) Comments: - Single-line: // comment
- Multi-line: /* comment */
6. Verilog Module :
module module_name(a,b,y,z);
input a,b ;
output y,z;
statement 1;
statement 2;
endmodule
6
aman nehra
Basics of Verilog
7. Interview Questions :
1. What is Verilog and why is it used?
2. Why is Verilog case-sensitive?
3. Why is Verilog syntax similar to the C language?
4. Where is Verilog used in the semiconductor industry?
5. How is Verilog used in SoC/CPU design?
6. Name three on-chip protocols designed using Verilog ?
7. How is Verilog used in FPGA design?
8. What is the role of Verilog in ASIC front-end design?
9. What is synthesis in digital design?
10. What is a gate-level netlist?
11. Why do we perform area, timing, and power optimization
12. What is gate-level modeling?
13. What is RTL (dataflow) modeling?
14. What is behavioral modeling?
15. Which modeling level is most used in industry and why?
16. What is hierarchical design?
17. Difference between top-down and bottom-up design.
18. Why is hierarchy important in SoC design?
19. Give an example of bottom-up design.
20. What is design reuse?
21. Why must Verilog keywords be lowercase?
22. Which characters are allowed in Verilog identifiers?
23. Difference between single-line and multi-line comments.
24. Why is case sensitivity important in Verilog?
25. What is the purpose of a port list in a Verilog module?
7
aman nehra