Chapter Three

Assembly level machine organization

1. Basic Organization of the von Neumann Machine

Von Neumann Architecture also known as the Von Neumann model, the computer consisted of a
CPU, memory and I/O devices. The program is stored in the memory. The CPU fetches an
instruction from the memory at a time and executes it. Thus, the instructions are executed
sequentially which is a slow process. Neumann models are called control flow computer because
instruction are executed sequentially as controlled by a program counter. To increase the speed,
parallel processing of computer have been developed in which serial CPU’s are connected in
parallel to solve a problem. Even in parallel computers, the basic building blocks are Neumann
processors. The von Neumann architecture is a design model for a stored-program digital
computer that uses a processing unit and a single separate storage structure to hold both
instructions and data. It is named after mathematician and early computer scientist John von
Neumann. Such a computer implements a universal Turing machine, and the common
“referential model” of specifying sequential architectures, in contrast with parallel architectures.

One shared memory for instructions (program) and data with one data bus and one address bus
between processor and memory. Instructions and data have to be fetched in sequential order
(known as the Von Neuman Bottleneck), limiting the operation bandwidth. Its design is simpler
than that of the Harvard architecture. It is mostly used to interface to external memory.

2. Control Unit

We have seen that the operation of a computer, in executing a program, consists of a sequence of
instruction cycles, with one machine instruction per cycle. Of course, we must remember that
this sequence of instruction cycles is not necessarily the same as the written sequence of
instructions that make up the program, because of the existence of branching instructions. What
we are referring to here is the execution time sequence of instructions.
We have further seen that each instruction cycle is made up of a number of smaller units. One
subdivision that we found convenient is fetch, indirect, execute, and interrupt, with only fetch
and execute cycles always occurring. To design a control unit, however, we need to break down
the description further. In fact, we will see that each of the smaller cycles involves a series of
steps, each of which involves the processor registers. We will refer to these steps as micro-
operations. The prefix micro refers to the fact that each step is very simple and accomplishes
very little. To summarize, the execution of a program consists of the sequential execution of
instructions. Each instruction is executed during an instruction cycle made up of shorter sub
cycles (e.g., fetch, indirect, execute, interrupt).The execution of each sub cycle involves one or
more shorter operations, that is, micro-operations. Micro-operations are the functional, or atomic,
operations of a processor.

3. Instruction Fetch

We begin by looking at the fetch cycle, which occurs at the beginning of each instruction cycle
and causes an instruction to be fetched from memory.

 Memory address register (MAR): Is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.
 Memory buffer register (MBR): Is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value read from memory.
 Program counter (PC): Holds the address of the next instruction to be fetched.
 Instruction register (IR): Holds the last instruction fetched.

Let us look at the sequence of events for the fetch cycle from the point of view of its effect on
the processor registers. At the beginning of the fetch cycle, the address of the next instruction to
be executed is in the program counter (PC); in this case, the address is [Link] first step is
to move that address to the memory address register (MAR) because this is the only register
connected to the address lines of the system bus. The second step is to bring in the instruction.
The desired address (in the MAR) is placed on the address bus, the control unit issues a READ
command on the control bus, and the result appears on the data bus and is copied into the
memory buffer register (MBR).We also need to increment the PC by the instruction length to get
ready for the next instruction. Because these two actions (read word from memory, increment
PC) do not interfere with each other, we can do them simultaneously to save time. The third step
is to move the contents of the MBR to the instruction register (IR).This frees up the MBR for use
during a possible indirect cycle.

Thus, the simple fetch cycle actually consists of three steps and four micro operations. Each
micro-operation involves the movement of data into or out of a register. So long as these
movements do not interfere with one another, several of them can take place during one step,
saving time. Symbolically, we can write this sequence of events as follows:
Where I is the instruction length. We need to make several comments about this sequence. We
assume that a clock is available for timing purposes and that it emits regularly spaced clock
pulses. Each clock pulse defines a time unit. Thus, all time units are of equal duration. Each
micro-operation can be performed within the time of a single time unit. The notation (t1,t2,t3)
represents successive time units.

In words, we have

 First time unit: Move contents of PC to MAR.

 Second time unit: Move contents of memory location specified by MAR to MBR.
Increment by I the contents of the PC.
 Third time unit: Move contents of MBR to IR.

Note that the second and third micro-operations both take place during the second time unit. The
third micro-operation could have been grouped with the fourth without affecting the fetch
operation:

The groupings of micro-operations must follow two simple rules:

 The proper sequence of events must be followed. Thus (MAR -> (PC)) must precede
(MBR -> Memory) because the memory read operation makes use of the address in the
MAR.
 Conflicts must be avoided. One should not attempt to read to and write from the same
register in one time unit, because the results would be unpredictable. For example, the
micro-operations (MBR -> Memory) and (IR ->MBR) should not occur during the same
time unit.

A final point worth noting is that one of the micro-operations involves an addition. To avoid
duplication of circuitry, this addition could be performed by the ALU. The use of the ALU may
involve additional micro-operations, depending on the functionality of the ALU and the
organization of the processor. We defer a discussion of this point until later in this chapter.
Whereas micro-operations are ignored in that figure, this discussion shows the micro-operations
needed to perform the sub-cycles of the instruction cycle.

4. Elements of Machine Instruction

The operation of the processor is determined by the instructions it executes, referred to as

machine instructions or computer instructions. The collection of different instructions that the
processor can execute is referred to as the processor’s instruction set.

Instruction Cycle State Diagram

Each instruction must contain the information required by the processor for execution. This
Figure shows the steps involved in instruction execution and, by implication, defines the
elements of a machine instruction. These elements are as follows:

 Operation code: Specifies the operation to be performed (e.g., ADD, I/O). The operation
is specified by a binary code, known as the operation code, or opcode.
 Source operand reference: The operation may involve one or more source operands,
that is, operands that are inputs for the operation.
 Result operand reference: The operation may produce a result.
 Next instruction reference: This tells the processor where to fetch the next instruction
after the execution of this instruction is complete.

The address of the next instruction to be fetched could be either a real address or a virtual
address, depending on the architecture. Generally, the distinction is transparent to the instruction
set architecture. In most cases, the next instruction to be fetched immediately follows the current
instruction. In those cases, there is no explicit reference to the next instruction. When an explicit
reference is needed, then the main memory or virtual memory address must be supplied. Source
and result operands can be in one of four areas:

 Main or virtual memory: As with next instruction references, the main or virtual
memory address must be supplied.
 Processor register: With rare exceptions, a processor contains one or more registers that
may be referenced by machine instructions. If only one register exists, reference to it may
be implicit. If more than one register exists, then each register is assigned a unique name
or number, and the instruction must contain the number of the desired register.
 Immediate: The value of the operand is contained in a field in the instruction being
executed.
 I/O device: The instruction must specify the I/O module and device for the operation. If
memory-mapped I/O is used, this is just another main or virtual memory address.

5. Instruction sets and types

Within the computer, each instruction is represented by a sequence of bits. The instruction is
divided into fields, corresponding to the constituent elements of the instruction. With most
instruction sets, more than one format is used. During instruction execution, an instruction is
read into an instruction register (IR) in the processor. The processor must be able to extract the
data from the various instruction fields to perform the required operation. It is difficult for both
the programmer and the reader of textbooks to deal with binary representations of machine
instructions. Thus, it has become common practice to use a symbolic representation of machine
instructions. An example of this was used for the IAS instruction set, in Table 3.1. Opcodes are
represented by abbreviations, called mnemonics, which indicate the operation. Common
examples include

IAS instruction set

Operands are also represented symbolically. For example, the instruction ADD R, Y may mean
add the value contained in data location Y to the contents of register R. In this example, Y refers
to the address of a location in memory, and R refers to a particular register. Note that the
operation is performed on the contents of a location, not on its address. Thus, it is possible to
write a machine-language program in symbolic form. Each symbolic opcode has a fixed binary
representation, and the programmer specifies the location of each symbolic operand. For
example, the programmer might begin with a list of definitions:

X = 513

Y = 514

and so on. A simple program would accept this symbolic input, convert opcodes and operand
references to binary form, and construct binary machine instructions. Machine-language
programmers are rare to the point of nonexistence. Most programs today are written in a high-
level language or, failing that, assembly language. However, symbolic machine language
remains a useful tool for describing machine instructions, and we will use it for that purpose.

Instruction Types

Consider a high-level language instruction that could be expressed in a language such as BASIC
or FORTRAN. For example,

X=X+Y

This statement instructs the computer to add the value stored in Y to the value stored in X and
put the result in X. How might this be accomplished with machine instructions? Let us assume
that the variables X and Y correspond to locations 513 and 514. If we assume a simple set of
machine instructions, this operation could be accomplished with three instructions:

 Load a register with the contents of memory location 513.

 Add the contents of memory location 514 to the register.
 Store the contents of the register in memory location 513.

As can be seen, a single BASIC instruction may require three machine instructions. This is
typical of the relationship between a high-level language and a machine language. A high-level
language expresses operations in a concise algebraic form, using variables. A machine language
expresses operations in a basic form involving the movement of data to or from registers. With
this simple example to guide us, let us consider the types of instructions that must be included in
a practical computer. A computer should have a set of instructions that allows the user to
formulate any data processing task. Another way to view it is to consider the capabilities of a
high-level programming language. Any program written in a high-level language must be
translated into machine language to be executed. Thus, the set of machine instructions must be
sufficient to express any of the instructions from a high-level language. With this in mind we can
categorize instruction types as follows:

 Data processing: Arithmetic and logic instructions

  Data storage: Movement of data into or out of register and or memory locations
 Data movement: I/O instructions
 Control: Test and branch instructions

Arithmetic instructions provide computational capabilities for processing numeric data. Logic
(Boolean) instructions operate on the bits of a word as bits rather than as numbers; thus, they
provide capabilities for processing any other type of data the user may wish to employ. These
operations are performed primarily on data in processor registers. Therefore, there must be
memory instructions for moving data between memory and the registers. I/O instructions are
needed to transfer programs and data into memory and the results of computations back out to
the user. Test instructions are used to test the value of a data word or the status of a computation.
Branch instructions are then used to branch to a different set of instructions depending on the
decision made.

Types of Operations

The number of different opcodes varies widely from machine to machine. However, the same
general types of operations are found on all machines. A useful and typical categorization is the
following:

 Data transfer Arithmetic Logical Conversion

 I/O System control Transfer of control

This section provides a brief survey of these various types of operations, together with a brief
discussion of the actions taken by the processor to execute a particular type of operation.

6. Assembly/machine language programming

Machine Language (low level language)

Low-Level language is the only language which can be understood by the computer. Low-level
language is also known as Machine Language. The machine language contains only two symbols
1 & 0. All the instructions of machine language are written in the form of binary numbers 1's &
0's. A computer can directly understand the machine language.

Assembly Language (middle level language)

Middle-level language is a computer language in which the instructions are created using
symbols such as letters, digits and special characters. Assembly language is an example of
middle-level language. In assembly language, we use predefined words called mnemonics.
Binary code instructions in low-level language are replaced with mnemonics and operands in
middle-level language. But the computer cannot understand mnemonics, so we use a translator
called Assembler to translate mnemonics into machine language. Assembler is a translator which
takes assembly code as input and produces machine code as output. That means, the computer
cannot understand middle-level language, so it needs to be translated into a low-level language to
make it understandable by the computer. Assembler is used to translate middle-level language
into low-level language.

High Level Language

High-level language is a computer language which can be understood by the users. The high-
level language is very similar to human languages and has a set of grammar rules that are used to
make instructions more easily. Every high-level language has a set of predefined words known
as Keywords and a set of rules known as Syntax to create instructions. The high-level language
is easier to understand for the users but the computer can not understand it. High-level language
needs to be converted into the low-level language to make it understandable by the computer.
We use Compiler or interpreter to convert high-level language to low-level language. Languages
like FORTRAN, C, C++, JAVA, Python, etc., are examples of high-level languages. All these
programming languages use human-understandable language like English to write program
instructions. These instructions are converted to low-level language by the compiler or
interpreter so that it can be understood by the computer.g++ [Link]
7. Instruction formats

The instruction format is a pattern of bits that control unit of the CPU can decode. After the
decode operation is complete the CPU executes the instruction as per the instruction set
architecture (ISA). The instruction format describes the layout of the instruction in terms of
group of bits called fields of the instruction format. Each field (group of bits) in the instruction
format provide a specific information to the processor. The processor needs to know the
information regarding the operation to be performed and the location of the data (address).

Program Instruction Execution

For example, the OPERAND part of the instruction format indicates either data or the address of
the data. The operation code OPCODE part indicates the type of operation to be performed on
the data. And the addressing mode part of the instruction format indicates the manner in which
the data is represented into the instruction format. The types of instruction formats supported by
the CPU depends upon the instruction set architecture (ISA) implemented by the CPU.
In machine instruction format, the bits are grouped together depending upon the type of the
instruction format. Each part (group of bits ) gives specific information to the CPU required to
decode and execute the operation.
In computer architecture, the instruction format is defined as standard machine instruction format
that can be directly decoded and executed by the central processing unit (CPU). The instruction
format is simply a sequence of bits (binary 0 Or 1) contained in a machine instruction that
defines the layout of the instruction. The machine instruction contains number of bits (pattern of
0 and 1). These bits are grouped together called fields. Each field of the machine instruction
provides specific information to the CPU regarding the operation to be performed and the
location of the data.

8. Addressing modes

The first part of the instruction format is called addressing mode. The data can either be stored in
the main memory RAM or it can be located in the CPU register. The addressing mode is defined
as the manner in which data is represented into the instruction format. The addressing mode is
the third field in the instruction format represented by a single bit. For example, in 16 bit
instruction format the addressing mode is represented by the 15th bit. The addressing mode
directs the CPU to locate the data (OPERAND) as specified in the machine instruction format.

Addressing Modes Types

The addressing mode bit in the instruction format defines the rules for the operand. The
addressing mode supported by the processor depends upon the microprocessor architecture and
the ISA – Instruction Set Architecture. For example, the RISC architecture supports only five
basic addressing modes. Whereas, the CISC architecture supports over ten plus addressing
modes.

 Direct Addressing Mode.

 Indirect Addressing Mode.
 Implied Addressing Mode.
  Immediate Addressing Mode.
 Register Addressing Mode.
 Register Indirect Mode.
 Auto Increment Mode.
 Relative Addressing Mode.
 Indexed Addressing Mode.
 Base Register Mode.

The operation field of an instruction specifies the operation to be performed. This operation will
be executed on some data which is stored in computer registers or the main memory. The way
any operand is selected during the program execution is dependent on the addressing mode of the
instruction. The purpose of using addressing modes is as follows:

 To give the programming versatility to the user.

 To reduce the number of bits in addressing field of instruction.

Immediate Mode

In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.

For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.

Register Mode

In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.
Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of operand
which is in memory. Thus, the register contains the address of operand rather than the operand
itself.

Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.

Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.

 Single memory reference to access data.

 No additional calculations to find the effective address of the operand.
For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.

NOTE: Effective Address is the location where operand is present.

Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in
memory. This slows down the execution, as this includes multiple memory lookups to find the
operand.

Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to
obtain the effective address of operand. EA = A + (R), In this the address field holds two values,
A(which is the base value) and R(that holds the displacement), or vice versa.
Relative Addressing Mode

It is a version of Displacement addressing mode. In this the contents of PC(Program Counter) is

added to address part of instruction to obtain the effective address. EA = A + (PC), where EA is
effective address and PC is program counter. The operand is A cells away from the current
cell(the one pointed to by PC)

Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),

where A is displacement and R holds pointer to base address.

Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top
two items from the stack, add them, and will then PUSH the result to the top of the stack.

9. Subroutine call and return mechanisms

Subroutine nesting is a common Programming practice In which one Subroutine calls another
Subroutine.

Subroutine calling another subroutine

From the above figure, assume that when Subroutine 1 calls Subroutine 2 the return address of
Subroutine 2 should be saved somewhere. So if the link register stores the return address of
Subroutine 1 this will be (destroyed/overwritten) by the return address of Subroutine 2. As the
last Subroutine called is the first one to be returned ( Last in first out format). So stack data
structure is the most efficient way to store the return addresses of the Subroutines.
 Return address of subroutine is stored in stack memory

10. I/O and interrupts

The method that is used to transfer information between internal storage and external I/O devices
is known as I/O interface. The CPU is interfaced using special communication links by the
peripherals connected to any computer system. These communication links are used to resolve
the differences between CPU and peripheral. There exists special hardware components between
CPU and peripherals to supervise and synchronize all the input and output transfers that are
called interface units. Mode of Transfer: The binary information that is received from an external
device is usually stored in the memory unit. The information that is transferred from the CPU to
the external device is originated from the memory unit. CPU merely processes the information
but the source and target is always the memory unit. Data transfer between CPU and the I/O
devices may be done in different modes. Data transfer to and from the peripherals may be done
in any of the three possible ways.

 Programmed I/O.
 Interrupt- initiated I/O.
 Direct memory access (DMA).

An interrupt is a signal from a device attached to a computer or from a program within the
computer that requires the operating system to stop and figure out what to do next. Interrupt
systems are nothing but while the CPU can process the programs if the CPU needs any IO
operation. Then, it is sent to the queue and it does the CPU process. Later on Input/output (I/O)
operation is ready. The I/O devices interrupt the data which is available and does the remaining
process; like that interrupts are useful. If interrupts are not present, the CPU needs to be in idle
state for some time, until the IO operation needs to complete. So, to avoid the CPU waiting time
interrupts are coming into picture.

Processor handle interrupts

Whenever an interrupt occurs, it causes the CPU to stop executing the current program. Then,
comes the control to interrupt handler or interrupt service routine. These are the steps in which
ISR handles interrupts. These are as follows
  Step 1 − When an interrupt occurs let assume processor is executing i'th instruction and
program counter will point to the next instruction (i+1)th.
 Step 2 − When an interrupt occurs the program value is stored on the process stack and
the program counter is loaded with the address of interrupt service routine.
 Step 3 − Once the interrupt service routine is completed the address on the process stack
is popped and placed back in the program counter.
 Step 4 − Now it executes the resume for (i+1)th line.

Types of interrupts

There are two types of interrupts which are as follows −

Hardware interrupts

The interrupt signal generated from external devices and i/o devices are made interrupt to CPU
when the instructions are ready.

For example: In a keyboard if we press a key to do some action this pressing of the keyboard
generates a signal that is given to the processor to do action, such interrupts are called hardware
interrupts.

Hardware interrupts are classified into two types which are as follows −

 Maskable Interrupt − The hardware interrupts that can be delayed when a highest priority
interrupt has occurred to the processor.
 Non Maskable Interrupt − The hardware that cannot be delayed and immediately be
serviced by the processor.

Software interrupts

The interrupt signal generated from internal devices and software programs need to access any
system call then software interrupts are present.

Software interrupt is divided into two types. They are as follows −

 Normal Interrupts − The interrupts that are caused by the software instructions are called
software instructions.
 Exception − Exception is nothing but an unplanned interruption while executing a
program. For example − while executing a program if we got a value that is divided by
zero is called an exception.