Question
1. Brief Introductions/Introduce yourself?
2. Have you worked on Cadence only?
3. Your past experience in the VLSI field & which different projects you did in DFT?
4. What is your contribution to the DFT field?
5. Did you perform RTL coding? Testbench generation? For which project?
6. What major challenges you Faced in entire DFT flow?
7. You had Analog/Mixed signal IPs in your project?
8. Brief Introduction of Present Profile and Past Academic Profile.
9. What is your role and Responsibility in Project?
10. Explain previous projects/currently working projects and tasks.
Why we do DFT?
What is different logic we are adding in DFT?
What are the inputs required for DFT?
What is OCC and PLL?
Why JTAG is used?
Any experience on JTAG and 1149.6 AC JTAG protocols?
Did you get a chance to work on JTAG? How the TAP works?
TAP functioning – FSM?
BSD – Insertion or verification? What all need to take care for insertion?
What is INTEST and EXTEST?
What you know about the JTAG?
Have you worked on Scan/ATPG?
What are the DRC’s you faced in scan? DRCs faced during SCAN Insertion?
What are the pre DRC’s and post DRC’s?
Is it mandatory to fix all the DRC’s?
What are the DRC’s we can ignore?
If we have DRC’s means can we go to ATPG or not?
What will happen if we go to ATPG with scan DRC’s?
DRC violations ( A sync & Clock ) faced in Spyglass & your approach to resolve the same
What is EDT
What is the difference between Synopsys compression vs EDT? Which is better?
How do you start scan insertion? How you approach for scan insertion?
Explain about wrapper cells? How you are avoiding the X propagation?
Explain about OCC?
What is test point insertion? Why? Advantages and disadvantages
Different type of fault models. Why different kind of fault models?
Type of fault model implemented
Test coverage vs fault coverage
How you improve coverage
How much coverage was improved changing abort limit?
Why is AU fault targeted first
What is the coverage for SAF and how did you improve the coverage?
Have you faced any critical DRC issue
How much coverage improvement,
What are the coverage improvements us have done
Have you worked on transition and path delay
Have you worked on cadence tool, any DRC’s have you faced
What is hierarchal ATPG? How you do hierarchical ATPG?
How to target cross clock Domain paths in Transition?
Why we need to path delay testing? Even if transition is 100% coverage?
Compression ratio analysis?
SMS overview?
Tool, you have used for MBIST, How many memories are there in your design/ have you worked on
repairable memory?
Have you faced any timing issue during MBIST simulation?
Explain about MBIST?
Redundancy calculation for Memory and how to decide Efuse ?
How do we group memories in MBIST? Any issues did you face during MBIST insertion?
MBIST Flow?
MBIST – how to group memories?
Do we use same 1149.1 TAP or Integrator (SMS) generated TAP for chip?
How do you configure User instruction in SMS TAP
What is UDS and CPF file? What are the contents are present? How to generate
How does Fault injection is performed? Different ways of injecting it
How do you generate repair vector and delivery to tester?
What do you do in trace resets and pre-scan steps and why do you do them before MBIST?