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Instruction Set

The document outlines an instruction set for a data transfer and arithmetic group, detailing various instructions such as MOV, MVI, LDA, STA, and arithmetic operations like ADD, SUB, and INR. Each instruction includes addressing modes, byte sizes, and examples of execution. The instructions facilitate data manipulation between registers and memory locations in a computing environment.

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0% found this document useful (0 votes)
5 views9 pages

Instruction Set

The document outlines an instruction set for a data transfer and arithmetic group, detailing various instructions such as MOV, MVI, LDA, STA, and arithmetic operations like ADD, SUB, and INR. Each instruction includes addressing modes, byte sizes, and examples of execution. The instructions facilitate data manipulation between registers and memory locations in a computing environment.

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siu2uuuu
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© All Rights Reserved
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INSTRUCTION SET

DATA TRANSFER GROUP INSTRUCTION:


1. MOV rd,rs: [MOVE REGISTER]
Addressing Mode: Register addressing
Bytes: 1 byte
Group: Data transfer
Comment: This instruction will transfer the content of source register to destination
register.
Example: [A]=05H and [B ]=55H
Instruction: MOV A,B
After Execution: [A]= 55H and [B]=55H
2. MOV r,M : [MOVE FROM MEMORY]
Addressing Mode: Register Iindirect addressing
Bytes: 1 byte
Group: Data transfer
Comment: This instruction will load destination register with the content of memory
location , whose address is stored in H-L register pair. The register can be
A,B,C,D,E,H,L.
Example: [H-L]=CFFFH , [CFFF]=35H and [B ]=85H
Instruction: MOV B,M
After Execution: [B]= 35H
[CFFF]=35H
3. . MOV M,r : [MOVE TO MEMORY]
Addressing Mode: Register Iindirect addressing
Bytes: 1 byte
Group: Data transfer
Comment: This instruction will copy the content of register r to the memory
location , whose address is stored in H-L register pair. The register can be
A,B,C,D,E,H,L.
Example: [H-L]=F000H , [F000]=40H and [C ]=FAH
Instruction: MOV M,C
After Execution: [C]= FAH
[F000]=FAH
4. MVI r, DATA : [MOVE IMMEDIATE 8 BIT]
Addressing Mode: Immediate addressing
Bytes: 2 byte
Group: Data transfer
Comment: This instruction will load register r with 8-bit immediate data specified in
second byte of instruction.
Example: MVI A , 35H
This instruction will load accumulator with immediate data 35H.
5. MVI M, DATA : [MOVE IMMEDIATE 8 BIT]
Addressing Mode: Immediate addressing/ register indirect
Bytes: 2 byte
Group: Data transfer
Comment: This instruction will load the memory location , whose address is stored in
H-L pair with 8-bit immediate data specified in the second byte of instruction.
Example: Let [H][L]=D000H
Instruction : MVI M,35H
This instruction will load memory location D000H with immediate with immediate
data 35H.
[Link] addr: [LOAD ACCUMULATOR DIRECT]
Addressing Mode: Direct addressing
Bytes: 3 byte
Group: Data transfer
Comment: This instruction will load accumulator with content of memory location , whose
address is given in instruction itself.
Example: [C500]=26H
INSTRUCTION : LDA C500
After execution: [A]=26H
[C500]=26H
7. STA addr: [STORE ACCUMULATOR DIRECT]
Addressing Mode: Direct addressing
Bytes: 3 byte
Group: Data transfer
Comment: This instruction will load the content of accumulator into with the memory
location , whose address is given in instruction itself.
Example: [A]=35H
INSTRUCTION : STA C500
After execution: [C500]=35H
[A]=35H
[Link] rp,16-bit data: [Load register pair immediate]
Addressing Mode: Immediate
Bytes: 3 byte
Group: Data transfer
Comment: The Byte three of instruction is moved into higher order register of register pair
and Byte 2 is moved into lower order register of register pair. The register pair can be BC ,
DE, HL or SP.
Example:
INSTRUCTION : LXI H,3500H
This instructions will load H-L pair with 3500H . 35H will be loaded in high order register(H)
and 00H will be loaded in lower order register(L).
9. LHLD address:[Load H and L register direct]
Format: [L] [[Byte 3][Byte 2]]
[H] [[Byte 3][Byte 2]+1]
Addressing Mode: direct Addressing
Bytes: 3 byte
Group: Data transfer
Comment: In this instruction the first byte gives the opcode and second and third
byte gives 16-bit address of memory location . The contents of memory location
whose address is specified in instruction are loaded into L register and the content of
next memory location loaded in H register.
Example:
[2100H]=31 H , [2101 H]=52 H
After executing instruction LHLD 2100 H
Register H contains data 31H and register L contains data 52H

10. SHLD address:[ Store H and L register direct]


Format: [[Byte 3][Byte 2]] [L]
[[Byte 3][Byte 2]+1] [H]
Addressing Mode: direct Addressing
Bytes: 3 byte
Group: Data transfer
Comment: In this instruction the first byte gives the opcode and second and third
byte gives 16-bit address of memory location . The contents of register L are
transferred to the memory location whose address is specified by byte 3 and byte 2
of the instruction . The contents of register H are moved to succeeding memory
location.

11. LDAX rp: [Load accumulator indirect]


Format: [A] [rp]
Addressing Mode: Register indirect Addressing
Bytes: 1 byte
Group: Data transfer
Comment: The contents of memory location whose address is stored in register pair
rp are loaded into accumulator. Rp can BC or DE
Example: [B]= 25H , [C]= 25H and[2525 H]=33H
After execution : LDAX B
[A]= 33H

[Link] rp: [Store accumulator indirect]


Format: [rp] [A]
Addressing Mode: Register indirect Addressing
Bytes: 1 byte
Group: Data transfer
Comment: The contents of Accumulator are transferred to the memory location
whose address is stored in register pair rp .Rp can BC or DE
Example: [D]= 25H , [E]= 25H and[A]=53H
After execution : STAX D
[2525]= 53H

13. XCHG: [Exchange H and L with D and E]


Format: [H]<-> [D]
[L]<-> [E]
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Data transfer
Comment: The contents of register H are exchange with register D and the
contents of L are exchange with register E.
Example: [H]= 23H , [L]= 32H [D]=53H ,[E]= 55H
After execution: XCHG
[H]=53H , [L]=55H
[D]=23H , [E]=32H

II] ARITHMETIC GROUP:


1. Add r:[ Add Register]
Format: [A]  [A] + [r]
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register r are added to the contents Accumulator, The
result is stored in accumulator.
Example: [D]=35 H AND [A]= 05H
Instruction: ADD D
35H= 0011 0101
+05H=0000 0101
3AH=0011 1010
1.
2. Add M:[ Add Memory]
Format: [A]  [A] + [[H] [L]]
Addressing Mode: Register Indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of accumulator are added to the contents of memory
location whose address is stored in HL pair, The result is stored in accumulator.
Example: [HL]=D000H , [D000]=35 H AND [A]= 55H
Instruction: ADD M

[Link] data:[ Add Immediate data to accumulator ]


Format: [A]  [A] + [2-byte data]
Addressing Mode: Immediate Addressing
Bytes: 2 byte
Group: Arithmetic group
Comment: This instruction add the 8-bit immediate data contents to the
contents Accumulator, The result is stored in accumulator.
Example: [A]=05 H
Instruction: ADI 15H

[Link] r:[ Add Registerto accumulator with carry]


Format: [A]  [A] + [r] +[cy]
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register r and carry are added to the contents
Accumulator, The result is stored in accumulator.
Example: ADC D

[Link] M:[ Add Memory to accumulator with carry]


Format: [A]  [A] + [[H] [L]] +[cy]
Addressing Mode: Register Indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of accumulator are added to the contents of memory
location whose address is stored in HL pair and carry , The result is stored in
accumulator.
Example: [HL]=D000H , [D000]=35 H AND [A]= 55H
Instruction: ADC M
[Link] data:[ Add Immediate data to accumulator with carry]
Format: [A]  [A] + [2-byte data] + [cy]
Addressing Mode: Immediate Addressing
Bytes: 2 byte
Group: Arithmetic group
Comment: This instruction add the 8-bit immediate data contents along with the
carry to the contents of Accumulator, The result is stored in accumulator.
Example: [A]=05 H
Instruction: ACI 15H

[Link] r: [Subtract register from accumulator]


Format: [A]  [A] – [r]
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comments: The contents of register are subtracted from the contents of
accumulator. The result is placed in accumulator.
Example: SUB C

[Link] M: [Subtract memory from accumulator]


Format: [A]  [A] - [[H] [L]]
Addressing Mode: Register Indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of memory location whose address stored in HL
register pair are subtracted from accumulator.
Example: SUB M

[Link] data:[ Subtract immediate from accumulator]


Format: [A]  [A] - [data]
Addressing Mode: Immediate Addressing
Bytes: 2 byte
Group: Arithmetic group
Comment: The 8-bit immediate data subtracted from accumulator.
Example: SUI 15H
[Link] r: [Increment register content by 1]
Format: [r] [r]+1
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register r are incremented by 1 and the result is
stored in the same. The register r can be A,B,C,D,E,H,L.
Example: INR B
[Link] r: [Increment mempry content by 1]
Format: [[H][L]] [[H][L]]+1
Addressing Mode: Register indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of memory location whose address is stored in HL pair
are incremented by 1 and the result is stored in the same.
Example: INR M

[Link] rp: [Increment register pair by 1]


Format: [rp] [rp]+1
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of registerpair rp are incremented by 1. The
instruction views the contents of the two registers as 16-bit number.
Example: INX B

[Link] r: [Decrement register content by 1]


Format: [r] [r] - 1
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register r are decremented by 1 and the result is
stored in the same. The register r can be A,B,C,D,E,H,L.
Example: DCR B

[Link] M: [Decrement memory content by 1]


INR r: [Increment register content by 1]
Format: [[H][L]] [[H][L]] -1
Addressing Mode: Register indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: This instruction decrements the contents of memory location whose
address is stored in HL pair by 1 and result is placed in same place.
Example: DCR M

[Link] rp: [Decrement register pair content by 1]


Format: [rp] [rp] - 1
Addressing Mode: Register indirect Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register pair rp are decremented by 1 .
Example: DCX B

[Link] rp:[Add register pair to H and L register]


Format: [H][L] [H][L] + [rp]
Addressing Mode: Register Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The contents of register pair rp are added to the contents of HL pair.
Result is placed in HL pair.
Example: [H]=03H , [L]=05H , [D]=15H , [E]=12H
Instruction: DAD D
After Execution: [L]=05+ 12= 17H
[H]=03=15=18H
[HL]=1817H

[Link]: [Decimal Adjust Accumulator]


Addressing Mode: Implied Addressing
Bytes: 1 byte
Group: Arithmetic group
Comment: The 8-bit number in the accumulator is adjusted to form two four -bit
binary coded decimal digit by this instruction. By following condition:
i)If the value of the least significant 4 bits of accumulator is greater than 9, then 06
added to the low order 4-bit of accumulator.
ii) If the value of the most significant 4 bits of accumulator is greater than 9, then 60
added to the high order 4-bit of accumulator.
iii)If LSB and MSB of accumulator are greater than 9 , then add 66 to accumulator.
Example: 39 = 0011 1001
+ 12 = 0001 0010
51 = 0100 1011 =4BH
The binary sum is 4BH. But BCD sum is 51
To adjust the result add 6 to low order bit
4B = 0100 1011
+06 = 0000 0110
51 = 0101 0001

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