Class 3 Notes1 : Hard – LEVEL
MAH MCA CET Computer Organization
Last 10 Years Previous Year Questions (PYQ)
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1. In which case does pipeline hazard occur?
A) When instruction fetch is slow
B) When two instructions need same resource
C) When CPU clock is high
D) When cache size is large
Answer: B
Explanation: Resource conflict causes hazard.
2. Which register is incremented automatically after instruction fetch?(2017)
A) IR
B) MAR
C) PC
D) MDR
Answer: C
Explanation: PC moves to next instruction.
3. Which cache mapping uses modulo function?
A) Fully associative
B) Direct mapping
C) Set associative
D) Virtual mapping
Answer: B
Explanation: Direct mapping uses block mod cache lines.
4. Which addressing mode uses contents of a register as address?(2016)
A) Immediate
B) Direct
C) Register indirect
D) Indexed
Answer: C
Explanation: Address is taken from register.
5. What is the main drawback of Von Neumann architecture?(2019)
A) Large memory
B) Single bus for data & instruction
C) Expensive hardware
D) Low speed ALU
Answer: B
Explanation: Causes Von Neumann bottleneck.
6. Which memory has lowest access time?(2015)
A) Hard Disk
B) RAM
C) Cache
D) ROM
Answer: C
Explanation: Cache is fastest.
7. Which type of ROM can be erased electrically?
A) PROM
B) EPROM
C) EEPROM
D) Mask ROM
Answer: C
Explanation: EEPROM is electrically erasable.
8. Which instruction format has no operand field?(2016)
A) One address
B) Two address
C) Three address
D) Zero address
Answer: D
Explanation: Zero address uses stack.
9. Which factor does NOT affect cache performance?
A) Hit ratio
B) Block size
C) Mapping technique
D) Hard disk speed
Answer: D
Explanation: Cache does not depend on hard disk.
10. Which type of hazard is caused by branch instruction?(2017)
A) Structural
B) Data
C) Control
D) Resource
Answer: C
Explanation: Branch causes control hazard.
11. Which register stores the operand fetched from memory?(2018)
A) MAR
B) MDR
C) PC
D) IR
Answer: B
Explanation: MDR stores data from memory.
12. Which technique improves instruction level parallelism?(2019)
A) Paging
B) Segmentation
C) Pipelining
D) Virtual memory
Answer: C
Explanation: Pipelining executes instructions in parallel.
13. In set associative mapping, cache block can go to(2020)
A) Only one line
B) Any line
C) A specific set
D) Only first line
Answer: C
Explanation: Block maps to one set.
14. Which addressing mode is fastest?(2019)
A) Immediate
B) Direct
C) Register
D) Indirect
Answer: C
Explanation: Register access is fastest.
15. What is the purpose of TLB?(2018)
A) Increase RAM size
B) Store instructions
C) Speed up address translation
D) Store cache blocks
Answer: C
Explanation: TLB speeds virtual-to-physical address translation.
16. Which memory management technique causes internal fragmentation?
A) Paging
B) Segmentation
C) Virtual memory
D) Cache mapping
Answer: A
Explanation: Paging causes internal fragmentation.
17. Which instruction cycle phase identifies operation?
A) Fetch
B) Decode
C) Execute
D) Interrupt
Answer: B
Explanation: Decode phase identifies operation.
18. Which type of interrupt is non-maskable?(2021)
A) Software
B) Hardware
C) Timer
D) Power failure
Answer: D
Explanation: Power failure interrupt cannot be masked.
19. Which memory is organized in rows and columns?(2021)
A) SRAM
B) DRAM
C) ROM
D) Cache
Answer: B
Explanation: DRAM uses matrix structure.
20. Which addressing mode adds offset to base register?(2023)
A) Immediate
B) Relative
C) Indexed
D) Direct
Answer: C
Explanation: Indexed addressing adds offset.
21. What happens on cache miss?
A) CPU stops
B) Data fetched from cache
C) Data fetched from main memory
D) Data lost
Answer: C
Explanation: Data comes from main memory.
22. Which component handles I/O interrupts?
A) ALU
B) Cache
C) Control Unit
D) Hard Disk
Answer: C
Explanation: CU handles interrupts.
23. Which CPU design uses complex instructions?(2022)
A) RISC
B) CISC
C) Harvard
D) Von Neumann
Answer: B
Explanation: CISC has complex instructions.
24. Which technique reduces branch penalty?
A) Loop unrolling
B) Branch prediction
C) Paging
D) DMA
Answer: B
Explanation: Branch prediction reduces delay.
25. Which cache policy writes data immediately to main memory?(2020)
A) Write back
B) Write through
C) Write allocate
D) No write allocate
Answer: B
Explanation: Write-through updates main memory instantly.