|| Jai Sri Gurudev ||
Sri Adichunchanagiri Shikshana Trust (R)
SJB Institute of Technology
Department of Electronics & Communication
Engineering
Advanced VLSI – 21EC71
Module-5
Randomization & Functional Verification
By
Mrs. S Nithya
Assistant Professor
Dept of ECE, SJBIT
Introduction
• As designs grow larger, it becomes more difficult to create a complete set of
stimuli needed to check their functionality. we can write a directed test case
to check a certain set of features, but you cannot write enough directed test
cases when the number of features keeps doubling on each project.
• The solution is to create test cases automatically using constrained-random
tests (CRT). A directed test finds the bugs you think are there, but a CRT
finds bugs you never thought about, by using random stimulus.
• A CRT is made of two parts: the test code that uses a stream of random values
to create input to the DUT, and a seed to the pseudo-random number
generator (PRNG),
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What to Randomize
• When you think of randomizing the stimulus to a design, the first thing
you may think of are the data fields. These are the easiest to create – just
call $random.
• The problem is that this approach has a very low payback in terms of
bugs found: you only find data-path bugs, perhaps with bit-level
mistakes.
• The test is still inherently directed. The challenging bugs are in the
control logic.
• As a result, you need to randomize all decision points in your DUT.
Wherever control paths diverge, randomization increases the probability
that you’ll take a different path in each test case.
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You need to think broadly about all design input such as the following:
• Device configuration
• Environment configuration
• Primary input data
• Encapsulated input data
• Protocol exceptions
• Delays
• Transaction status
• Errors and violations
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Randomization in SystemVerilog
• The random stimulus generation in SystemVerilog is most useful when used
with OOP.
• You first create a class to hold a group of related random variables, and then
have the random-solver fill them with random values. You can create
constraints to limit the random values to legal values, or test-specific features.
• Note that you can randomize individual variables, but this case is the least
interesting. True constrained-random stimuli is created at the transaction level,
not one value at a time.
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1. Simple Class with Random
Variables
• Sample 6.1 shows a packet class
with random variables and
constraints, plus testbench code
that constructs and randomizes a
packet.
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This class has four random variables.
• The first three use the rand modifier, so that every time you randomize the
class, the variables are assigned a value.
• The kind variable is randc, which means random cyclic, so that the
random solver does not repeat a random value until every possible value has
been assigned.
• The randomize() function returns 0 if a problem is found with the
constraints.
• uses a $fatal to stop simulation,
• uses assert to test the result from randomize()
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2. Checking the Result from Randomization
• The randomize() function assigns random values to any variable in the
class that has been labeled as rand or randc, and also makes sure that all
active constraints are obeyed.
• Randomization can fail if your code has conflicting constraints (see next
section), and so you should always check the status. If you don’t check, the
variables may get unexpected values, causing your simulation to fail.
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3. The Constraint Solver
• The process of solving constraint expressions is handled by the SystemVerilog
constraint solver. The solver chooses values that satisfy the constraints.
• The values come from SystemVerilog’s PRNG, which is started with an initial
seed. If you give a SystemVerilog simulator the same seed and the same
testbench, it always produces the same results.
• The solver is specific to the simulation vendor, and a constrained-random test
may not give the same results when run on different simulators, or even on
different versions of the same tool.
• The SystemVerilog standard specifies the meaning of the expressions, and the
legal values that are created, but does not detail the precise order in which the
solver should operate. Dept. of ECE, SJBIT 9
4. What can be Randomized?
• SystemVerilog allows you to randomize integral variables, that is,
variables that contain a simple set of bits.
• This includes 2-state and 4-state types, though randomization only works
with 2-state values.
• we can have integers, bit vectors, etc. You cannot have a random string,
or refer to a handle in a constraint.
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Random Number Functions
we can use all the Verilog-1995 distribution functions, plus several that are new
for SystemVerilog. Some of the useful functions include the following.
• $random() – Flat distribution, returning signed 32-bit random
• $urandom() – Flat distribution, returning unsigned 32-bit random
• $urandom_range() – Flat distribution over a range
• $dist_exponential() – Exponential decay, as shown in Figure 6-1
• $dist_normal() – Bell-shaped distribution
• $dist_poisson() – Bell-shaped distribution
• $dist_uniform() – Flat distribution
• The $urandom_range() function takes two arguments, an optional low value,
and a high value.
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Dept. of ECE, SJBIT 12
Random Number Generators
• How random is SystemVerilog?
• On the one hand, your testbench depends on an uncorrelated stream of
random values to create stimulus patterns that go beyond any directed test.
• On the other hand, you need to repeat the patterns over and over during
debug of a particular test, even if the design and testbench make minor
changes.
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• Verilog uses a simple PRNG
that you could access with the
$random function. The
generator has an internal state
that you can set by providing a
seed to $random.
• Sample 6.68 shows a simple
PRNG, not the one used by
SystemVerilog. The PRNG
has a 32-bit state. To calculate
the next random value, square
the state to produce a 64-bit
value, take the middle 32 bits,
then add the original value.
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[Link] Stability – Multiple Generators
• Verilog has a single PRNG that is used for the entire simulation. What would
happen if SystemVerilog kept this approach?
• Testbenches often have several stimulus generators running in parallel,
creating data for the design under test. If two streams share the same PRNG,
they each get a subset of the random values.
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Dept. of ECE, SJBIT 16
• In Figure 6-3, there are two
stimulus generators and a single
PRNG producing values a, b, c,
etc. Gen2 has two random
objects, and so during every
cycle, it uses twice as many
random values as Gen1. A
problem can occur when one of
the classes changes. Gen1 gets an
additional random variable, and
so consumes two random values
every time it is called.
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This approach changes
the values used not
only by Gen1 but also
by Gen2 (Figure 6-4).
In SystemVerilog,
there is a separate
PRNG for every object
and thread. Changes to
one object don’t affect
the random values seen
by others (Figure 6-5).
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