Module 3

Instruction Format
What is an Instruction Format?
• An instruction is a binary command given to the CPU.
An instruction format defines how the bits of an instruction are
arranged.
• Every instruction generally contains:
– Opcode → What opera on to perform (ADD, SUB, LOAD, etc.)
– Operand(s) → Data or address of data
– Addressing info → How to find the operand

• Instruction format = layout of these fields inside an instruction

 Instruction Example
General Form Explanation
Format Instruction(s)

Adds b and c, stores result in a, and

4-Address OP dest, src1, src2, next ADD a, b, c, NEXT explicitly gives address of next
instruction

Adds b and c, stores result in a;

3-Address OP dest, src1, src2 ADD a, b, c
next instruction decided by PC

Adds b to a and stores result back

2-Address OP dest/src, src ADD a, b
in a
LOAD b
OP address (Accumulator Uses accumulator (AC) implicitly;
1-Address ADD c
implicit) only one explicit address
STORE a
PUSH b
Uses stack; operands taken from
PUSH c
0-Address OP (Stack based) stack, no explicit address in ALU
ADD
instruction
POP a
 Example
• Memory is divided into fixed-size blocks called words. Word length is the
number of bytes (or bits) that a computer can read, write, or process in
one memory access.
• The CPU accesses memory one word at a time.
• Let’s assume the following in order to justify which type of the
instruction format is best :
– Word length = 3 bytes
– Opcode – 1 byte
– Addresses/data – 3 bytes
 Memory
24 Bits / 3 Bytes
4- Address
8
Instruction
24 24 24 24

CPU Op Code ResAddr Op1Addr Op2Addr NextiAddr

Op Code ResAddr Op1Addr Op2Addr NextiAddr
Op1 Example: add M1,M2,M3, nexti
Op2 + M(1)M(2)+M(3)
Memory Required to store an Instruction:
Resop
5 x 3 bytes = 15 Bytes
Memory Required to Encode an Instruction:
1Byte+ 4 x 3 bytes = 13 Bytes

Calculation of Memory Accesses

To fetch Instruction itself To Execute an Instruction
Opcode=1
Op1Addr=1 Op1=1
Op2Addr=1 Op2=1
ResAddr=1 Res=1
NextiAddr=1 Total=3
Total=5

Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute

Total Memory Traffic= 5 + 3 =8
 Memory
24 Bits / 3 Bytes
3- Address
8
Instruction
24 24 24

CPU Op Code ResAddr Op1Addr Op2Addr

Op Code ResAddr Op1Addr Op2Addr
Op1
+
Example: add M1,M2,M3 M(1)M(2)+M(3)
Op2
Memory Required to store an Instruction:
Resop 4 x 3 bytes = 12 Bytes
Memory Required to Encode an Instruction:
1Byte+ 3 x 3 bytes = 10 Bytes
PC 24
Calculation of Memory Accesses
To fetch Instruction itself To Execute an Instruction
Opcode=1
Op1Addr=1 Op1=1
Op2Addr=1 Op2=1
ResAddr=1 Res=1
Total=4 Total=3

Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute

Total Memory Traffic= 4+ 3 =7
 Memory
24 Bits / 3 Bytes
2- Address Instruction
8 24 24

CPU Op Code Op1Addr Op2Addr

Op Code Op1Addr Op2Addr
Op1
+
Example: add M2,M3 M(2)M(2)+M(3)
Op2
Memory Required to store an Instruction:
Resop 3 x 3 bytes = 09 Bytes
Memory Required to Encode an Instruction:
PC 1Byte+ 2 x 3 bytes = 7 Bytes
24
Calculation of Memory Accesses
To fetch Instruction itself To Execute an Instruction
Opcode=1
Op1Addr=1 Op1=1
Op2Addr=1 Op2=1
Res=1
Total=3
Total=3

Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute

Total Memory Traffic= 3+ 3 =6
 Memory
24 Bits / 3 Bytes
1- Address Instruction
8 24

CPU Op Code Op1Addr

Op Code Op1Addr
Op1 Example: add M2
Op2 + Memory Required to store an Instruction:
Resop 2 x 3 bytes = 06 Bytes
Acc
Memory Required to Encode an Instruction:
PC 1Byte+ 1 x 3 bytes = 4Bytes
24
Calculation of Memory Accesses
To fetch Instruction itself To Execute an Instruction
Opcode=1
Op1Addr=1 Op1=1
Total=2 Total=1

Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute

Total Memory Traffic= 2+ 1 =3
0-Address Instruction
 Comparisons
Instruction Memory Memory No. of [Link] M/As Total
Type Required Required M/As to to Execute Memory
To Store To Encode fetch an an Traffic
in Bytes in Bytes Instruction Instruction
4-address 5 x 3 = 15 1+(4 x 3) = 13 5 3 5+3=8

3-Address 4 x 3 = 12 1+(3 x 3) = 10 4 3 4+3=7

2-Address 3 x 3 = 09 1+(2 x 3) = 07 3 3 3+3=6

1-Address 2 x 3 = 06 1+(1 x 3) = 04 2 1 2+1=3

0-Address 1 x 3 = 03 1+(0 x 3) = 01 1 0 1+0=1

 Summary

Format Addresses Fetch MAs Execute MAs Total

4-address 4 High 3 High
3-address 3 Medium 3 Medium
2-address 2 Lower 3 Lower
1-address 1 Lowest 1 Very low
0-address 0 Lowest 0* Lowest

* -stack assumed internal

 Example for Memory Traffic
Calculation
• Compute Memory traffic, total memory for
encoding and storing code that implements
the expression evaluation a=(b+c)*d-e.
Assume that the opcode occupy one byte,
addresses occupy three bytes, data values also
occupy three bytes and 3 byte world length.
3-Address
Evaluate a = (b+c)*d - e
add a, b, c ab+c 0-Address

mpy a, a, d aa*d push b

sub a, a, e aa-e push c
2-Address
add
mov a, b ab
push d
add a, c aa+c
mpy
mpy a, d aa*d
push e
sub a, e aa-e
1-Address sub
load b Accb pop a
add c AccAcc+c
mpy d AccAcc*d
sub e AccAcc-e
store a aAcc
 Memory Memory M/As to M/As to Memory
to Store to Fetch Execute Traffic
encode
add a, b, c ab+c
4*3=12 1+(3*3)=1 4 3 4+3=7
mpy a, a, d aa*d 0
sub a, a, e aa-e 4*3=12 1+(3*3)=1 4 3 4+3=7
0
4*3=12 1+(3*3)=1 4 3 4+3=7
0
36 30 12 9 21
Memory Memory M/As to M/As to Memory
to Store to encode Fetch Execute Traffic

Mov a,b ab 3*3=9 1+(2*3)= 3 2 5

Add a,c aa+c 7
mpy a, d aa*d 3*3=9 1+(2*3)= 3 3 6
7
Sub a,e a a- e
3*3=9 1+(2*3)= 3 3 6
7
3*3=9 1+(2*3)= 3 3 6
7
36 28 12 11 23
 Memory Memory M/As to M/As to Memory
to Store to Fetch Execute Traffic
load b Accb encode
2*3=6 1+(1*3)=4 2 1 2+1=3
add c AccAcc+c
2*3=6 1+(1*3)=4 2 1 2+1=3
mpy d AccAcc*d
2*3=6 1+(1*3)=4 2 1 2+1=3
sub e AccAcc-e
2*3=6 1+(1*3)=4 2 1 2+1=3
store a aAcc
2*3=6 1+(1*3)=4 2 1 2+1=3
30 20 10 5 15
push b
2*3=6 1+(1*3)=4 2 1 3
push c
2*3=6 1+(1*3)=4 2 1 3
add
3 1 1 0 1
push d
2*3=6 1+(1*3)=4 2 1 3
mpy
3 1 1 0 1
push e 2*3=6 1+(1*3)=4 2 1 3
sub
3 1 1 0 1
pop a
2*3=6 1+(1*3)=4 2 1 3
39 23 13 5 15
 Summary of 3-,2-,1-, and 0-Addresss instruction programming

Instructio Memory to Memory M/As to M/As to Memory

n Format Store to Encode Fetch Execute Traffic

4-Address 45 39 24 9 33

3-Address 36 30 12 9 21

2-Address 36 28 12 11 23

1-Address 30 20 10 5 15

0-Address 39 23 13 5 15
 Exercise
• Compute Memory traffic, total memory for
encoding and storing code that implements
the expression evaluation A= (B-C)*D.
Assume that the opcode occupy one byte,
addresses occupy two bytes, data values also
occupy two bytes and 1 byte world length
 Addressing Modes

• An addressing mode defines how an instruction

specifies the location of its operand (data).
• In simple words:
– It tells the CPU where the data is
– And how to calculate the effective address (EA)
• Effective Address (EA)
– The actual memory address from which data is
fetched.
– Most addressing modes are about how EA is
calculated.
 Let’s consider

Symbol Meaning
A Address field in instruction
R Register specified in instruction
(A) Contents of memory at address A
(R) Contents of register R
EA Effective Address
 Algorithm (EA
No. Addressing Mode Advantage Disadvantage
calculation)
No memory
reference for Operand size limited
1 Immediate Operand = A
operand (fast by instruction format
execution)
Simple and easy to
2 Direct (Absolute) EA = A Limited address space
use
Large address Multiple memory
3 Indirect EA = (A)
space references (slow)

No memory access, Limited number of

4 Register EA = R
very fast registers
Large address
space, fewer
5 Register Indirect EA = (R) Extra register needed
memory accesses
than indirect
Flexible, supports More complex
6 Displacement EA = A + (R)
arrays & structures hardware
No explicit operand
EA = Top of
7 Stack address, compact Limited applicability
Stack
code
 Problems
1. Find the effective address and the content of AC for the given data.
Addressing Mode Effective Content of AC
Address
Direct Address 500 AC ← (500) 800
Immediate operand 201 AC ← 500 500
Indirect address 800 AC ← ((500)) 300
Relative address 702 AC ← (PC + 500) 325
Indexed address 600 AC ← (XR + 500) 900
Register - AC ← R1 400

Register Indirect 400 AC ← (R1) 700

Autoincrement 400 AC ← (R1)+ 700
Autodecrement 399 AC ← -(R1) 450
 Exercise

• An instruction is stored at location 300 with its

address field at location 301. The address field
has the value 400. A processor register R1
contains the number 200. Evaluate the
effective address if the addressing mode of
the instruction is (a) direct; (b) immediate (c)
relative (d) register indirect; (e) index with R1
as the index register.