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Instruction Format Problem

The document discusses the impact of the number of addresses in instruction sets on instruction size and program structure, using an arithmetic function as an example. It explains zero, one, two, and three-address instruction types, detailing how each type operates with respect to memory and registers. The document includes tables illustrating the specific instructions and their functions for each address type.

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0% found this document useful (0 votes)
5 views5 pages

Instruction Format Problem

The document discusses the impact of the number of addresses in instruction sets on instruction size and program structure, using an arithmetic function as an example. It explains zero, one, two, and three-address instruction types, detailing how each type operates with respect to memory and registers. The document includes tables illustrating the specific instructions and their functions for each address type.

Uploaded by

k.mala31169
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

NUMBER OF ADDRESSES AND INSTRUCTION SIZE

There are instructions set with zero address, one address, two address, three address, and RISC (Reduced Instruction
Set Computers). What is the impact of number of
addresses in an instruction on instruction size and program? It will be discussed with the help of program that evaluates the
arithmetic function:
A =(W+X) × (Y+Z)
Zero address instruction: The instructions used for stack organized computers do not have the address field in the
instruction. As you can see in the following instructions that no address is assigned in the instruction except for the PUSH
and POP commands. The operands are implicit and are taken from the top of the stack. Hence, these are called Zero address
instructions. The program to evaluate the value of A is given in Table 9.4.
Table 9.4: Zero Address instructions
PUSH W The stack top position W
PUSH X The stack top position X
ADD The stack top position W+X
PUSH Y The stack top position Y
PUSH Z The stack top position Z
ADD The stack top position Y+Z
MUL The stack top position (W+X)×(Y+Z)
POP A A  The stack top position
One address instruction: in these instructions, only one address field is present while the second operand is an implicit
register operand - the AC accumulator register. The set of instructions that can solve the stated mathematical operation are
discussed in
Table 9.5: One address instructions

Instruction Function Discussion


LOAD W AC M[W] Data of Memory Address W is loaded in
accumulator register
ADD X ACAC +M[X] Data of Memory Address X is added with
accumulator data
STORE A M[A] AC Accumulator data containing (W+X) is stored in
Memory Address A
LOAD Y AC M[Y] Data from Memory Address Y is loaded in
accumulator
ADD Z ACAC +M[Z] Data Memory Address Z is added with accumulator data
Memory address A is loaded in accumulator
MUL A ACAC *M[A] Accumulator data is stored in Memory address A
STORE A M[A] AC

Table 9.5. You can observer that all the instructions in the Table 9.5 have just one perand address specified in the
instruction. We can see, instructions are only with one address.
Two addresses instruction: Here, one instruction holds two addresses which may be memory address or processor register.
As listed in the following table, all the instructions hold two addresses one of these is a processor register and the other is the
memory location.
Table 9.6: Two-addresses instructions

Instruction Function Discussion


MOV R1, W R1 M[W] Data of Memory Address W is moved to
register R1
ADD R1, X R1R1 +M[X] Data of Memory Address X is added with
data of register R1 and result is saved in R1
MOV R2, Y R2 M[Y] Data of Memory Address Y is moved to
register R2
ADD R2, Z R2R2 +M[Z] Data of Memory Address z is added with data
of register R2 and result is saved in R2
MUL R1, R2 R1R1 *R2 Data of registers R1 and R2 is multiplied and
saved in R1
MOV A, R1 M[A]R1 Results of R1 is moved to Memory address A

Three addresses Instructions: These instructions hold three addresses which may be
processor register and/or memory. As shown in the following table, all the instructions
hold three addresses.

Table 9.7: 3-address instructions

Instruction Function Discussion


ADD R1, W, X R1 M[W]+M[X] Data of memory location W and X are added
and result is stored in processor register R1

ADD R2, Y, Z R2M[Y] +M[Z] Data of memory location Y and Z are added, and
result is stored in processor register R2

MUL A, R1, R2 M[A]R1*R2 Data of processor registers R1 and R2 is


multiplied and saved in memory location A .

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