MODULE 1
1. Obtain a minimum product of sums with a Karnaugh map
F( w, x, y, z ) = x’ z’ + w yz + w’ y’ z’ + x’ y [DEC 23/ JAN 24]
2. Find the minimum sum of products for each function using
Karnaugh map.
i. F1 (a, b, c) = M0 + M2 + M5 + M6
ii. F2 (d, e, f) =summation m (0, 1, 2, 4)
iii. F3 (r, s, t) = rt’ + r’ s’ + r’ s [DEC 23/ JAN 24]
3. Identify the prime implicants and essential prime implicants of
the following functions:
i. f ( A, B, C, D) = summation (1, 3, 4, 5, 10, 11, 12, 13, 14, 15)
ii. f (W, X, Y, Z) = summation (0, 1, 2, 5, 7, 8, 10, 15) [DEC 23/
JAN 24]
4. write a Verilog code for the given expression using dataflow and
behavioural model where
Y = (A B’ + A’ B) (CB + AD) (A B’ C – A C) [DEC 23/ JAN 24]
5. write a Verilog code and timing diagram for the given circuit with
propagation delay where the AND, OR gate has a delay of 30ns
and 10ns.
[DEC 23/ JAN 24]
6. demonstrate the positive and negative logic using AND gate.
[JUNE/ JULY 25, MQP 3]
7. Show that NAND and NOR function are commutative and but not
associative. [JUNE/ JULY 25]
8. Simplify the Boolean function F ( w, x, y, z) = summation m (0, 1,
2, 4, 6, 7, 9, 12, 14) using K -map and implement using NAND
gates. [JUNE/ JULY 25]
9. What is binary logic? List out any 4 laws of logic. [JUNE/ JULY 25,
MQP 3]
10. Find the POS expression for F ( A, B, C, D) = pi M (2, 3, 5, 8,
10, 13, 14) + d ( 1, 6, 7, 11) and realize it using NOR gates. [JUNE/
JULY 25]
i.
11. Determine the complement of the following function:
i. F = x y’ + x’ y
ii. F = x’ y z’ + x’ y’ z [DEC 24/ JAN 25]
12. Describe map method for three variables. [DEC 24/ JAN 25]
13. Apply K map technique to simplify the following function:
i. F (x, y, z) = summation (0, 2, 4, 5, 6)
ii. F (x, y, z) = x’ y + y z’ + y’z’ [ DEC 24/ JAN 25]
14. Apply K map technique to simplify the function:
F ( w, x, y, z) = summation (1, 3, 7, 11, 15) and d ( w, x, y, z) =
summation (0, 2, 5) [DEC 24/ JAN 25, JUNE/ JULY 24]
15. Determine all the prime implicants for the Boolean function
F and also determine which are essential F (w, x, y, z) =
summation (0, 2, 4, 5, 6, 7, 8, 10, 13, 15) [DEC 24/ JAN 25]
16. Develop a Verilog gate – level description of the circuit
shown
[DEC 24/ JAN 25]
17. Reduce the following Boolean expressions to the minimum
number of literals.
i. x(x’ +y)
ii. x + x’ y
iii. (x + y) (x+ y’)
iv. x y + x’ z + y z
v. (x + y) (x’ + z) (y + z) [JUNE/ JULY 24]
18. Determine the minimum SOP form using Karnaugh Map
F= A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’ [JUNE/ JULY 24]
19. Simplify and implement the following Boolean function
using NAND gates F( x, y, z) = (1, 2, 3, 4, 5, 7) [JUNE/ JULY 24]
20. Demonstrate the non associativity of the NOR gate [MQP 1]
21. Design a car safety alarm circuit diagram. The system
considers four inputs: door (D), key (K), seat pressure (P) and
seat belt (B). The input is considered HIGH (1) if the door is
closed, the key is in, the driver is on the seat, or the seat belt is
fastened. The alarm (A) should sound with two conditions as
stated below: The door is not closed, and the key is in. The door is
closed, the key is in the driver's seat, and the seat belt is not
closed.
(a) Construct a truth table for the system based on input
arrangement D, K, P, B with A as an output
(b)Design a Karnaugh map to verify the simplified expression
(c) Draw the simplified circuit using NOR gates only [MQP 1]
22. With an example explain the working of Test Bench in
Verilog. [MQP 1, MQP 2]
23. Demonstrate the positive and negative logic signal [MQP 1]
24. A digital system is to be designed in which the month of the
year is given as I/P in four-bit form. The month of January is
represented as '0000', February as "0001" and so on. The output
of the system should correspond to the input of the month
containing 31 days, or otherwise, it is '0'. Consider the excess
number in the I/P beyond 1011' as don't care condition:
(i) Write truth table, SOP Em and POSIIM form
(ii) Simplify for SOP using K-m
(iii)Realize using basic gates [MQP 1]
25. What is User-Defined Primitives in Verilog? What are the
general rules for UDP? Explain with an example HDL for user
defined primitive. Draw the Schematic for the Circuit with
UDP_02467 [ MQP 1]
26. Demonstrate the working of Test Bench in Verilog. [MQP 2]
27. Simplify the following Boolean functions into
i. Sum of products
ii. Product of sums
F (A, B, C, D)= summation (0, 6, 8, 13, 14)
d (A, B, C, D) = summation (2, 4, 10) [MQP 2]
28. Write a program, in Verilog to demonstrate the working of
user- defined primitive table. [MQP 2]
29. Realize F = AB+ CD using NAND gate only. [MQP 2]
30. Simplify the following Boolean expression using kmap:
F ( A, B, C, D) = summation ( 0, 1, 3, 7, 8, 9, 10, 13, 15)
F (w, x, y, z) = summation ( 0, 1, 2, 4, 5, 6, 7, 10, 15) [MQP 2]
31. Find the POS expression for F (a, b, c, d) = pi (2, 3, 5, 8, 10,
13, 14) + d (1, 6, 7, 11) and realize it using NOR gates. [ MQP 3]
32. Simplify the Boolean function F (w, x, y, z) = summation (0,
1, 2, 4, 6, 7, 9, 12, 14) using k map and write the Verilog program
for realizing the minimized expression. [MQP 3]
33. Simplify the following Boolean function and find its SOP:
i. F (x, y, z) = summation (0, 1, 4, 5, 6) + d(2, 3, 7)
ii. F( w, x, y, z) = summation ( 5, 6, 7, 12, 14, 15) + d(13, 9, 11)
[MQP 3]
34. Write a short note on hardware description language.
[MQP 3]