Student Name (As per last

qualification mark sheet) ABISHEK S

Enrollment Number IIMTS/IND/MPETE/SA2744/7B15
Course title MPETE
Semester No. 3rd
Subject title Advanced Microprocessor Based System
Examination paper receiving
date 11/04/2017

Q1. (a) List the three buses found in all computer systems.
(b) What is the purpose of a segments register in the real mode operation of the
microprocessors?

Q2. (a) Which register or register is used as an offset address for string instruction
destinations in the microprocessors?
(b) For a Pentium 4 descriptor that contains a base address of 00280000H, a
limit of 00010H, and G=1, what starting and ending location are addressed by
the descriptor?

Q3. (a) Describe what happens when a new number is loaded into a segments
register when the microprocessor is operated in the protected mode.
(b) What is a displacement? How does it determine the memory address in a
MOV [2000H], AL instruction?

Q4. (a) Develop a data structure that has five field of one word each named F1, F2,
F3, F4 and F5 with a structure name FIELDS.
(b) What is the difference between an inter segment and intra segments jump?

Q5. (a) From a short sequence of instruction that load the data segment register with
a 10000H.
(b) Which instruction set and clears the direction flag?

Q6. (a) What is an assembly language directive?

(b) What directives indicate the start and end of a procedure?

Q7 (a) Describe the difference between the AND and TEST instructions.
(b) What is the difference between the NOT and the NEG instruction?

Q8. (a) What is a short JMP?

(b) Which JMP instruction allows the program to continue execution at any
memory locations in the systems?

Q9. (a) What is a Procedure?

(b) What is a Interrupt?
(c) What does the IRETD instruction?
(d) What is a null string?
Q1. (a.) List the three buses found in all computer systems?

Types of Buses in Computer Architecture

Inside computers, there are many internal components. In order for these components
to communicate with each other they make use of wires that are known as a ‘bus’ .
A bus is a common pathway through which information flows from one computer
component to another. This pathway is used for communication purpose and it is
established between two or more computer components. We are going to check
different computer bus architectures that are found in computers.

Different Types of Computer Buses

The Computer Buses | Source

Functions of Buses in Computers

1. Data sharing - All types of buses found in a computer transfer data between the
computer peripherals connected to it.
The buses transfer or send data in either serial or parallel method of data transfer. This
allows for the exchange of 1, 2, 4 or even 8 bytes of data at a time. (A byte is a group of
8 bits). Buses are classified depending on how many bits they can move at the same
time, which means that we have 8-bit, 16-bit, 32-bit or even 64-bit buses.
2. Addressing - A bus has address lines, which match those of the processor. This
allows data to be sent to or from specific memory locations.
3. Power - A bus supplies power to various peripherals connected to it.
4. Timing - The bus provides a system clock signal to synchronize the peripherals
attached to it with the rest of the system.
The expansion bus facilitates easy connection of more or additional components and
devices on a computer such as a TV card or sound card.
 Bus Terminologies
Computers have two major types of buses:
1. System bus:- This is the bus that connects the CPU to main memory on the
motherboard. The system bus is also called the front-side bus, memory bus, local bus,
or host bus.
2. A number of I/O Buses, (I/O is an acronym for input / output), connecting various
peripheral devices to the CPU. These devices connect to the system bus via a ‘bridge’
implemented in the processors chipset. Other names for the I/O bus include “expansion
bus", "external bus” or “host bus”.

Expansion Bus Types

These are some of the common expansion bus types that have ever been used in
computers:
 ISA - Industry Standard Architecture
 EISA - Extended Industry Standard Architecture
 MCA - Micro Channel Architecture
 VESA - Video Electronics Standards Association
 PCI - Peripheral Component Interconnect
 PCMCIA - Personal Computer Memory Card Industry Association
 AGP - Accelerated Graphics Port
 SCSI - Small Computer Systems Interface.

(b.) What is the purpose of a segments register in the real mode operation of the
microprocessors?

Real mode, also called real address mode, is an operating mode of all x86-
compatible CPUs. Real mode is characterized by a 20-bit segmented memory
address space (giving exactly 1 MiB of addressable memory) and unlimited direct
software access to all addressable memory, I/O addresses and peripheral hardware.
Real mode provides no support for memory protection, multitasking, or code privilege
levels. Before the release of the 80286, which introduced protected mode, real mode
was the only available mode for x86 CPUs.[1] In the interest of backward compatibility, all
x86 CPUs start in real mode when reset, though it is possible to emulate real mode on
other systems when starting on other modes.

The 8086, 8088, and 80186 have a 20-bit address bus, but the unusual
segmented addressing scheme Intel chose for these processors actually produces
effective addresses which can have 21 significant bits. This scheme shifts a 16-bit
segment number left four bits (making a 20-bit number with four least-significant zeros)
before adding to it a 16-bit address offset; the maximum sum occurs when both the
segment and offset are 0xFFFF, yielding 0xFFFF0 + 0xFFFF = 0x10FFEF. On the 8086,
8088, and 80186, the result of an effective address that overflows 20 bits is that the
address "wraps around" to the zero end of the address range, i.e. it is taken modulo
2^20 (2^20 = 1048576 = 0x100000). However, the 80286 has 24 address bits and
computes effective addresses to 24 bits even in real mode. Therefore, for the segment
0xFFFF and offset greater than 0x000F, the 80286 would actually make an access into
the beginning of the second mebibyte of memory, whereas the 80186 and earlier would
access an address equal to [offset]-0x10, which is at the beginning of the first mebibyte.
(Note that on the 80186 and earlier, the first kibibyte of the address space, starting at
address 0, is the permanent, immovable location of the interrupt vector table.) So, the
actual amount of memory addressable by the 80286 and later x86 CPUs in real mode is
1 MiB + 64 KiB – 16 B = 1114096 B.

Following reset, Intel processors start executing code in the real-mode operating
environment. Since real-mode is fully compatible with the 8086 architecture, it enables
execution of MS-DOS applications on newer processors such as the Pentium and
Pentium Pro. Unfortunately, along with the numerous benefits of real-mode, there is also
one major drawback to this mechanism. That is, a processor running in real-mode can
exploit only the lowest 20 bits of its address bus and is therefore limited to the meagre
1MB memory space of the 8086. IBM's decision to reserve the upper 384KB of the PC
for ISA add-on cards (and the BIOS), made things even worst since it left real-mode
applications (including MS-DOS itself) with barely 640KB of RAM to work with.

As you already know, a processor requires a minimum of 20 address lines to have the
ability to access 1MB of memory. When Intel engineers designed the 8086, it was
impracticle to implement a 20 bit address register to hold the generated addresses. So
instead, Intel decided to divide address space into 64KB segments and coordinate
memory access through the use of two 16 bit values - a Segment and an Offset.

The value set into a segment register identifies a specific 64KB region of
memory, whereas the offset part points to an exact location within that
region. To calculate a physical address, the processor shifts the content of
the segment register four bits to the left (thus multiplying its value by 16)
and adds the offset.
Q2. (a.) Which register or register is used as an offset address for string instruction
destinations in the microprocessors?

In 16-bit mode, such as provided by the Pentium processor when operating

as a Virtual 8086 (this is the mode used when Windows 95 displays a DOS
prompt), the processor provides the programmer with 14 internal registers, each 16
bits wide. They are grouped into several categories as follows:

 Four general-purpose registers, AX, BX, CX, and DX. Each of these is a
combination of two 8-bit registers which are separately accessible as AL,
BL, CL, DL (the "low'' bytes) and AH, BH, CH, and DH (the "high'' bytes).
For example, if AX contains the 16-bit number 1234h, then AL
contains 34h and AH contains 12h.
 Four special-purpose registers, SP, BP, SI, and DI.
 Four segment registers, CS, DS, ES, and SS.
 The instruction pointer, IP (sometimes referred to as the program counter).
 The status flag register, FLAGS.

Although I refer to the first four registers as "general-purpose'', each of them is

designed to play a particular role in common use:

 AX is the "accumulator''; some of the operations, such as MUL and DIV,

require that one of the operands be in the accumulator. Some other
operations, such as ADD and SUB, may be applied to any of the registers (that
is, any of the eight general- and special-purpose registers) but are more
efficient when working with the accumulator.
 BX is the "base'' register; it is the only general-purpose register which may
be used for indirect addressing. For example, the instruction MOV [BX],
AX causes the contents of AX to be stored in the memory location whose
address is given in BX.
 CX is the "count'' register. The looping instructions (LOOP, LOOPE,
and LOOPNE), the shift and rotate instructions (RCL, RCR, ROL, ROR, SHL, SHR,
and SAR), and the string instructions (with the prefixes REP, REPE, and REPNE)
all use the count register to determine how many times they will repeat.
 DX is the "data'' register; it is used together with AX for the word-
size MUL and DIV operations, and it can also hold the port number for
the IN and OUT instructions, but it is mostly available as a convenient place
to store data, as are all of the other general-purpose registers.

Here are brief descriptions of the four special-purpose registers:

 SP is the stack pointer, indicating the current position of the top of the stack.
You should generally never modify this directly, since the subroutine and
interrupt call-and-return mechanisms depend on the contents of the stack.
  BP is the base pointer, which can be used for indirect addressing similar to
BX.
 SI is the source index, used as a pointer to the current character being read
in a string instruction (LODS, MOVS, or CMPS). It is also available as an offset to
add to BX or BP when doing indirect addressing; for example, the
instruction MOV [BX+SI], AX copies the contents of AX into the memory
location whose address is the sum of the contents of BX and SI.
 DI is the destination index, used as a pointer to the current character being
written or compared in a string instruction (MOVS, STOS, CMPS, or SCAS). It is
also available as an offset, just like SI.

Since all of these registers are 16 bits wide, they can only contain addresses
for memory within a range of 64K (=2^16) bytes. To support machines with more
than 64K of physical memory, Intel implemented the concept
of segmented memory. At any given time, a 16-bit address will be interpreted as an
offset within a 64K segment determined by one of the four segment registers (CS,
DS, ES, and SS).

As an example, in the instruction MOV [BX], AX mentioned above, the BX

register really provides the offset of a location in the current data segment; to find
the true physical address into which the contents of the accumulator will be stored,
you have to add the value in BX to the address of the start of the data segment.
This segment start address is determined by taking the 16-bit number in DS and
multiplying by 16. Therefore, if DS contains 1234h and BX contains 0017h, then
the physical address will be 1234h TIMES 16+0017h=12340h+0017h=12357h. (This
computation illustrates one reason why hexadecimal is so useful; multiplication by
16 corresponds to shifting the hex digits left one place and appending a zero.) We
refer to this combined address as 1234:0017 or, more generally, as DS:BX.

Since segment starts are computed by multiplying a 16-bit number by

16=2^4, the effect is that physical addresses have a 20-bit range, so that a total of
1M (=2^20) of memory may be used. Intel considered that this would be enough
for applications of the 8086 over its projected lifetime of about five years from its
introduction in 1978; by the time microcomputers were needing more than a meg
of main memory, the next Intel processor (the iAPX432) was due to be available,
with a 32-bit address space (able to address 4G---over 4 billion memory locations).
However, the IBM PC's debut in 1981 and subsequent popularity has forced Intel
to continue the 80x86 family of backward-compatible processors to the present,
including support for a mode in which only 1M of memory is accessible.
Processors since the 80286 have also provided the "protected'' mode of operation,
which in the Pentium gives each process a flat 32-bit address space of up to 4G.

You might think that a segment register would only need to provide the
uppermost 4 bits to extend an address out to 20 bits, but consider one of the
 implications of only having 16 different, non-overlapping segments: every
segment would have to occupy a full 64K of memory, even if only a small fraction
of this space were needed. By allowing a segment to start at any address divisible
by 16, the memory may be allocated much more efficiently---if one program only
needs 4K for its code segment, then theoretically the operating system could load
another program into a segment starting just 4K above the start of the first. Of
course, MS-DOS is not really this sophisticated, but the Intel designers wanted it
to be possible.

Q3. (a.) Describe what happens when a new number is loaded into a segments register
when the microprocessor is operated in the protected mode?

The microprocessor as a programmable device by first looking at its internal

programming model and then at how it addresses its memory space. The
addressing modes for Intel family of microprocessors are described for both the real
and protected modes of operation. Real mode memory exists at locations 00000H-
FFFFFH the first 1M byte of the memory system—and is present on all versions of
the microprocessor. Protected mode memory exists at any location in the entire
memory system, but is available only to the 80286—Pentium II, not to the earlier

8086 or 8088 microprocessors. Protected mode memory for the 80286

contains 16M bytes; for the 80386-Pentium, 4G bytes; and for the Pentium Pro and
Pentium II, either 4G or 64G [Link] a program is written or any instruction
investigated, the internal configuration of the microprocessor must be known. This
section of the chapter details the program-visible internal architecture of the 8086—
80486 and the Pentium—Pentium II microprocessors. Also detailed are the function
and purpose of each of these internal registers.

The programming model of the 8086 through the Pentium II’s considered to
be program visible because its registers are used during application programming
and are specified by the instructions. Other registers, detailed later in this chapter,
are considered to be program invisible because they are not addressable directly
during applications programming, but may be used indirectly during system
programming. Only the 80286 and above contain the program-invisible registers
used to control and operate the protected memory system.

The programming model of the 8086 through the Pentium II microprocessor.

The earlier 8086, 8088, and 80286 contain 16-bit internal architectures, a subset of
the registers. The 80386, 80486, Pentium, Pentium Pro, and Pentium II mi-
croprocessors contain full 32-bit internal architectures. The architectures of the
earlier 8086 through the 80286 are fully upward-compatible to the 80386 through the
Pentium II. The shaded areas in this illustration represent registers that are not
found in the 8086, 8088, or 80286 microprocessors.
EAX (accumulator)

EAX is referenced as a 32-bit register (EAX), as a 16-bit register (AX), or as

either of two 8-bit registers (AH and AL). Note that if an 8- or 16-bit register is
addressed, only that portion of the 32-bit register changes without affecting the
remaining bits. The accumulator is used for instructions such as multiplication,
division, and some of the adjustment instructions. For these instructions, the
accumulator has a special purpose, but is generally considered to be a multipurpose
register. In the 80386 and above, the EAX register may also hold the offset address
of a location in the memory system.

EBX (base index)

EBX is addressable as EBX, BX, BH, or BL. The BX register sometimes holds
the offset address of a location in the memory system in all versions of the
microprocessor. In the 80386 and above, EBX also can address memory data.

ECX (count)

ECX is a general-purpose register that also holds the count for various
instructions. In the 80386 and above, the ECX register also can hold the offset
address of memory data. Instructions that use a count are the repeated string
instructions (REP/REPE/REPNE); and shift, rotate, and LOOP/LOOPD instructions.
The shift and rotate instructions use CL as the count, the repeated string instructions
use CX, and the LOOP/LOOPD instructions use either CX or ECX.

EDX (data)

EDX is a general-purpose register that holds a part of the result from a

multiplication or part of the dividend before a division. In the 80386 and above, this
register can also address memory data.

EBP (base pointer)

EBP points to a memory location in all versions of the microprocessor for

memory data transfers. This register is addressed as either BP or EBP.
(b.) What is a displacement? How does it determine the memory address in a
MOV [2000H], AL instruction?

Register indirect addressing allows data to be addressed at any memory

location through an offset address held in any of the following registers: BP, BX, DI,
and SI. For example, if register BX contains a l000H and the MOV AX,[BX]
instruction executes, the word contents of data segment offset address I 000H are
copied into register AX. If the microprocessor is operated in the real mode and
DS = OIOOH, this instruction addresses a word stored at memory bytes 2000H and
2001H, and transfers it into register AX (see Figure 3—6). Note that the contents of
2000H are moved into AL and the contents of 2001H are moved into AH. The [
] symbols denote indirect addressing in assembly language. In addition to using the
BP, BX, DI, and SI registers to indirectly address memory, the 80386 and above
allow register indirect addressing with any extended register except ESP. Some
typical instructions using indirect addressing appear in Table 3—5.

The data segment is used by default with register indirect addressing or any
other addressing mode that uses BX, DI, or SI to address memory. If the BP register
addresses memory, the stack segment is used by default. These settings are
considered the default for these four index and base registers. For the 80386 and
above, EBP addresses memory in the stack segment by default; FAX, EBX, ECX,
EDX, EDT, and ESI address memory in the data segment by default. When using a
32-bit register to address memory in the real mode, the contents of the 32-bit
register must never exceed 0000FFFFH. In the protected mode, any value can be
used in a 32-bit register that is used to indirectly address memory, as long as it does
not access a location outside of the segment, as dictated by the access rights byte.
An example 80386/80486/Pentium II instruction is MOV EAX,[EBX]. This instruction
loads FAX with the doubleword-sized number stored at the data segment offset
address indexed by EBX.

In some cases, indirect addressing requires specifying the size of the data are
specified with the special assembler directive BYTE PTR, WORD PTR, or DWORD
PTR. These directives indicate the size of the memory data addressed by the
memory pointer (PTR). For example, the MOV AL,[DIJ instruction is clearly a byte-
sized move instruction, but the MOV [DI], 1OH instruction is ambiguous. Does the
MOV [DIJ,10H instruction address a byte-, word-, or double-word-sized memory
location? The assembler can’t determine the size of the IOH. The instruction MOV
BYTE PTR [DI],IOH clearly designates the location addressed by Dl as a byte-sized
memory location. Likewise, the MOV DWORD PTR [DI],IOH clearly identifies t~ie
memory location as doubleword-sized. The BYTE PTR, WORD PTR, and DWORD
PTR directives are used only with instructions that address a memory location
through a pointer or index register with immediate data, and for a few other
instructions that are described in subsequent chapters.

Indirect addressing often allows a pi cam to refer to tabular data located in the
memory system. For example, suppose that you must create a table of information
that contains 50 samples taken from memory location 0000:046C. Location
0000:046C contains a counter that is maintained by the personal computer’s real-
time clock. Figure 3—7 shows the table and the BX register used to sequentially
address each location in the table. To accomplish this task, load the starting location
of the table into the BX register with a MOV immediate instruction. After initializing
the starting address of the table, use register indirect addressing to store the 50
samples sequentially.

The sequence shown in Example 3—6 loads register BX with the starting
address of the table and initializes the count, located in register CX, to 50. The
OFFSET directive tells the assembler to load BX with the offset address of memory
location TABLE, not the contents of

TABLE. For example. the MOV BX,DATAS instruction copies the contents of
memory location DATAS into BX, while the MOV BX,OFFSET DATAS instruction
copies the offset address of DATAS into BX. When the OFFSET directive is used
with the MOV instruction, the assembler calculates the offset address and then uses
a MOV immediate instruction to load the address into the specified 16-bit register.

Once the counter and pointer are initialized, a repeat-until CX = 0 loop

executes. Here, data are read from extra segment memory location 46CH with the
 MOV AX,ES:[046CH] instruction and stored in memory that is indirectly addressed
by the offset address located in register BX. Next, BX is incremented (one is added
to BX) to the next table location, and finally the LOOP instruction repeats the LOOP
50 times. The LOOP instruction decrements (subtracts one from) the counter (CX); if
CX is not zero, LOOP causes a jump to memory location AGAIN. If CX becomes
zero, no jump occurs and this sequence of instructions ends. This example copies
the most recent 50 values from the clock into the memory array DATAS. This
program will often show the same data in each location because the contents of the
clock are changed only4 18.2 times per second. To view the program and its
execution, use the CodeView program. To use CodeView, type CV [Link] or
access it as DEBUG from the Programmer’s WorkBench program under the RUN
menu. Note that CodeView functions only with .EXE or .COM files. Some useful
CodeView switches are /50 for a 50-line display and IS for use of high-resolution
video displays in an application. To debug the file [Link] with 50 lines, type
CV /50 [Link] at the DOS prompt.

Q4 (a.) Develop a data structure that has five field of one word each named F1, F2, F3, F4 and F5
with a structure name FIELDS.?

Every one of us has seen these 12 function keys on the Keyboard. But how
many of us used these keys to have our jobs performed easier? These function keys
perform different functions in different applications and programs. In combination
with other keys these function keys perform different functions differently. For the
benefit of all of us I have codified the ‘Function Keys’ performances.

As this information is collected from various web sites, magazines, some of them
may prove wrong. I have tested most of them, and they are Ok. While collecting the
information I have taken every care to collect correct information without ambiguity
and I may have missed some, SO this is not the end.

F1:
If you are in an application and you press this key, you will get its help file. Suppose
you are not in Windows Explorer or Desktop, you press this key you will get
Windows Help file. Suppose you are in an application, and you want windows help
file, press windows key + F1, you will get windows help file. F1 + in combination with
other keys:
SHIFT + F1 = Start context-sensitive help or reveal formatting (What is this? help)
ALT + F1 = Go to the next field
ALT + SHIFT + F1 = Go to the previous field
CTRL + ALT + F1 = Display Microsoft system information
For formatting characters and paragraphs:
CTRL + SHIFT + F1 = Change the font

F2:
You select a program on your Desktop (icon) and press this key. You will be allowed
to rename that program. The same function you can also perform by Right
Clicking the mouse and in the resultant memo you will have the option to rename the
program.

SHIFT + F2 = Copy Text

CTRL + F2 = Choose the print preview command (file menu)
ALT + SHIFT + F2 = Choose the save command (file menu)
CTRL + ALT + F2 = Choose the open command (file menu)

F3:
While you are working in Windows Explorer or on Desktop, you press this key you
will get the ‘Find Files’ window. You need not go to Start > find.
While you are working in MS Word (make your selection) and press
ALT + F3 = Create an auto text entry box appears.
SHIFT + F3 = Change the case of the letters.

F4:
While you are in Internet Explorer and you will press this key the address bar will
open.
If you want to close the selected window, press ALT + F4.
When no windows are open if you press ALT + F4, you will see the shut down
screen. When no windows are open if you press ALT + F4, you will see the shut
down screen.
When you are in MS Word, press
F4 = Repeat the last action
SHIFT + F4 = Repeat a Find or Go To action
CTRL + F4 = Close the Window
ALT + F4 = Quit the word program

F5:
To refresh the active window in IE or WE, press F5.
When you are in MS Word and you press this key, you will have the Find and
replace window > Go To (Edit menu)
SHIFT + F5 = Move to previous revision
CTRL + F5 = Restore the document window size
CTRL + SHIFT + F5 = Edit a bookmark
ALT + F5 = Quit the word program
(b.) What is the difference between an inter segment and intra segments jump?

The jmp (jump) instruction unconditionally transfers control to another point in the
program. There are six forms of this instruction: an intersegment/direct jump two
intrasegment/direct jumps an intersegment/indirect jump and two
intrasegment/indirect jumps. Intrasegment jumps are always between statements in
the same code segment. Intersegment jumps can transfer control to a statement in a
different code segment.

These instructions generally use the same syntax it is

Jmp target

The assembler differentiates them by their operands:

jmp disp8 ;direct intrasegment

8 bit displacement.
jmp disp16 ;direct intrasegment
16 bit displacement.
jmp adrs32 ;direct intersegment
32 bit segmented address.
jmp mem16 ;indirect intrasegment
16 bit memory operand.
jmp reg16 ;register indirect intrasegment.
jmp mem32 ;indirect intersegment
32 bit memory operand.

Intersegment is a synonym for far intrasegment is a synonym for near.

The two direct intrasegment jumps differ only in their length. The first form consists
of an opcode and a single byte displacement. The CPU sign extends this
displacement to 16 bits and adds it to the ip register. This instruction can branch to a
location -128..+127 from the beginning of the next instruction following it (i.e. -
126..+129 bytes around the current instruction).

The second form of the intrasegment jump is three bytes long with a two byte
displacement. This instruction allows an effective range of -32 768..+32 767 bytes
and can transfer control to anywhere in the current code segment. The CPU simply
adds the two byte displacement to the ip register.

These first two jumps use a relative addressing scheme. The offset encoded as part
of the opcode byte is not the target address in the current code segment but the
distance to the target address. Fortunately MASM will compute the distance for you
automatically so you do not have to compute this displacement value yourself. In
many respects these instructions are really nothing more than add ip
disp instructions.
 The direct intersegment jump is five bytes long the last four bytes containing a
segmented address (the offset in the second and third bytes the segment in the
fourth and fifth bytes). This instruction copies the offset into the ipregister and the
segment into the cs register. Execution of the next instruction continues at the new
address in cs:ip. Unlike the previous two jumps the address following the opcode is
the absolute memory address of the target instruction; this version does not use
relative addressing. This instruction loads cs:ip with a 32 bit immediate value.

For the three direct jumps described above you normally specify the target address
using a statement label. A statement label is usually an identifier followed by a colon
usually on the same line as an executable machine instruction. The assembler
determines the offset of the statement after the label and automatically computes the
distance from the jump instruction to the statement label. Therefore you do not have
to worry about computing displacements manually. For example the following short
little loop continuously reads the parallel printer data port and inverts the L.O. bit.
This produces a square wave electrical signal on one of the printer port output lines.

Q 5. (a.) From a short sequence of instruction that load the data segment register with a
10000H.?

Register indirect addressing allows data to be addressed at any memory location

through an offset address held in any of the following registers: BP, BX, DI, and SI. For
example, if register BX contains a l000H and the MOV AX,[BX] instruction executes, the
word contents of data segment offset address I 000H are copied into register AX. If the
microprocessor is operated in the real mode and DS = OIOOH, this instruction addresses
a word stored at memory bytes 2000H and 2001H, and transfers it into register AX (see
Figure 3—6). Note that the contents of 2000H are moved into AL and the contents of
2001H are moved into AH. The [ ] symbols denote indirect addressing in assembly
language. In addition to using the BP, BX, DI, and SI registers to indirectly address
memory, the 80386 and above allow register indirect addressing with any extended
register except ESP. Some typical instructions using indirect addressing appear in Table
3—5.

The data segment is used by default with register indirect addressing or any
other addressing mode that uses BX, DI, or SI to address memory. If the BP register
addresses memory, the stack segment is used by default. These settings are
considered the default for these four index and base registers. For the 80386 and
above, EBP addresses memory in the stack segment by default; FAX, EBX, ECX,
EDX, EDT, and ESI address memory in the data segment by default. When using a
32-bit register to address memory in the real mode, the contents of the 32-bit
register must never exceed 0000FFFFH. In the protected mode, any value can be
used in a 32-bit register that is used to indirectly address memory, as long as it does
not access a location outside of the segment, as dictated by the access rights byte.
An example 80386/80486/Pentium II instruction is MOV EAX,[EBX]. This instruction
loads FAX with the doubleword-sized number stored at the data segment offset
address indexed by EBX.

In some cases, indirect addressing requires specifying the size of the data are
specified with the special assembler directive BYTE PTR, WORD PTR, or DWORD
PTR. These directives indicate the size of the memory data addressed by the
memory pointer (PTR). For example, the MOV AL,[DIJ instruction is clearly a byte-
sized move instruction, but the MOV [DI], 1OH instruction is ambiguous. Does the
MOV [DIJ,10H instruction address a byte-, word-, or double-word-sized memory
location? The assembler can’t determine the size of the IOH. The instruction MOV
BYTE PTR [DI],IOH clearly designates the location addressed by Dl as a byte-sized
memory location. Likewise, the MOV DWORD PTR [DI],IOH clearly identifies t~ie
memory location as doubleword-sized. The BYTE PTR, WORD PTR, and DWORD
PTR directives are used only with instructions that address a memory location
through a pointer or index register with immediate data, and for a few other
instructions that are described in subsequent chapters.

Indirect addressing often allows a pi cam to refer to tabular data located in the
memory system. For example, suppose that you must create a table of information
that contains 50 samples taken from memory location 0000:046C. Location
0000:046C contains a counter that is maintained by the personal computer’s real-
time clock. Figure 3—7 shows the table and the BX register used to sequentially
address each location in the table. To accomplish this task, load the starting location
of the table into the BX register with a MOV immediate instruction. After initializing
the starting address of the table, use register indirect addressing to store the 50
samples sequentially.

The sequence shown in Example 3—6 loads register BX with the starting
address of the table and initializes the count, located in register CX, to 50. The
OFFSET directive tells the assembler to load BX with the offset address of memory
location TABLE, not the contents of TABLE. For example. the MOV BX,DATAS
instruction copies the contents of memory location DATAS into BX, while the MOV
 BX,OFFSET DATAS instruction copies the offset address of DATAS into BX.
When the OFFSET directive is used with the MOV instruction, the assembler
calculates the offset address and then uses a MOV immediate instruction to load the
address into the specified 16-bit register.

Once the counter and pointer are initialized, a repeat-until CX = 0 loop

executes. Here, data are read from extra segment memory location 46CH with the
MOV AX,ES:[046CH] instruction and stored in memory that is indirectly addressed
by the offset address located in register BX. Next, BX is incremented (one is added
to BX) to the next table location, and finally the LOOP instruction repeats the LOOP
50 times. The LOOP instruction decrements (subtracts one from) the counter (CX); if
CX is not zero, LOOP causes a jump to memory location AGAIN. If CX becomes
zero, no jump occurs and this sequence of instructions ends. This example copies
the most recent 50 values from the clock into the memory array DATAS. This
program will often show the same data in each location because the contents of the
clock are changed only4 18.2 times per second. To view the program and its
execution, use the CodeView program. To use CodeView, type CV [Link] or
access it as DEBUG from the Programmer’s WorkBench program under the RUN
menu. Note that CodeView functions only with .EXE or .COM files. Some useful
CodeView switches are /50 for a 50-line display and IS for use of high-resolution
video displays in an application. To debug the file [Link] with 50 lines, type
CV /50 [Link] at the DOS prompt.

Q.6 (a.) What is an assembly language directive.?

It is sometimes referred to as assembly or ASL, assembly language is a low-

level programming language used to interface with computer hardware. Assembly
language uses structured commands as substitutions for numbers allowing humans
to read the code easier than looking at binary. Although easier to read than binary,
assembly language is a difficult language and is usually substituted for a higher
language such as C. Below, is an example of assembly language in a debug routine.
An assembly language is a low-level way to instruct a computer to carry out a
[Link] do not inherently understand instructions from people. At the most
basic level, computers understand instructions in binary language, that is,
sequences of zeroes and ones. Binary language or machine language is extremely
cumbersome to program in, however. Assembly language was invented as a
symbolic representation of the underlying sequences of zeroes and ones. A program
called an assembler converts assembly language code into the underlying machine
language.

Assembly language is mostly a thin layer above the machine structure. An

assembly language is a low-level programming language for a computer,
microcontroller, or other programmable device, in which each statement
corresponds to a single machine code instruction. Each assembly language is
specific to a particular computer architecture, in contrast to most high-level
programming languages, which are generally portable across multiple systems.
Assembly language is converted into executable machine code by a utility program
referred to as an assembler; the conversion process is referred to as assembly, or
assembling the code.

Assembler Directive :An assembler directive is a message to the assembler that tells
the assembler something it needs to know in order to carry out the assembly
process; for example, an assemble directive tells the assembler where a program is
to be located in memory.

Examples of common assembler directives are ORG (origin), EQU (equate), and
DS.B (define space for a byte).

Equate:The EQU assembler directive simply equates a symbolic name to a numeric

value. Consider:

Sunday EQU 1

Monday EQU 2

The assembler substitutes the equated value for the symbolic name; for example, if
you write the instruction ADD.B #Sunday,D2, the assembler treats it as if it were
ADD.B #1,D2.
Sunday EQU 1

Monday EQU Sunday + 1

In this case, the assembler evaluates "Sunday + 1" as 1 + 1 and assigns the value 2
to the symbolic name "Monday".

Assigns a value to a symbol (same as EQU)

ORG

sets the current origin to a new value. This is used to set the program or register
address during assembly. For example, ORG 0100h tells the assembler to assemble
all subsequent code starting at address 0100h.

DS

Defines an amount of free space. No code is generated. This is sometimes used for
allocating variable space.

ID

Sets the PIC’s identification bytes. PIC16C5x chips have two ID bytes, which can be
set to a 2-byte value. Newer PICs have four 7-bit ID locations, which can be filled
with a 4-character text string.

INCLUDE

Loads another source file during assembly. This allows us to insert an additional
source file into your code during assembly. IF

Assembles code if expression evaluates to TRUE.

IFNOT

Assembles code if expression evaluates to FALSE.

ELSE

Assembles code if preceding evaluation is rejected.

ENDIF

Ends conditional evaluation.

 RESET

sets the reset start address. This address is where program execution will start
following a reset. A jump to the given address is inserted at the last location in
memory.

(b.) What directives indicate the start and end of a procedure.?

Assembly languages are low-level languages for programming computers,

microprocessors, microcontrollers, and other IC. They implement a symbolic
representation of the numeric machine Codes and other constants needed to program a
particular CPU architecture. This representation is usually defined by the hardware
manufacturer, and is based on abbreviations that help the programmer to remember
individual instructions, registers. An assembler directive is a statement to give
direction to the assembler to perform task of the assembly process.
It control the organization if the program and provide necessary information to the
assembler to understand the assembly language programs to generate necessary
machine codes. They indicate how an operand or a section of the program is to be
processed by the assembler.
An assembler supports directives to define data, to organise segments to control
procedure, to define macros. It consists of two types of statements: instructions and
directives. The instructions are translated to the machine code by the assembler
whereas directives are not translated to the machine codes.

Assembler Directives of the 8086 Microprocessor

(a) The DB directive
(b) The DW directive
(c) The DD directive
(d) The STRUCT (or STRUC) and ENDS directives (counted as one)
(e)The EQU Directive
(f)The COMMENT directive
(g)ASSUME
(h) EXTERN
(i) GLOBAL
(j) SEGMENT
(k)OFFSET
 (l) PROC
(m)GROUP
(n) INCLUDE

Q.7 (a.) Describe the difference between the AND and TEST instructions.?

AND:
outlines the testing approach and everything else that surrounds it. It is different
from the test plan, in the sense that a Test strategy is only a sub set of the test
plan. It is a hard core test document that is to an extent generic and static. There
is also an argument about at what levels test strategy or plan is used- but I really
do not see any discerning difference.

Example: Test plan gives the information of who is going to test at what time. For
example: Module 1 is going to be tested by “X tester”. If tester Y replaces X for
some reason, the test plan has to be updated.

On the contrary, test strategy is going to have details like – “Individual modules
are to be tested by test team members. “ In this case, it does not matter who is
testing it- so it’s generic and the change in the team member does not have to be
updated, keeping it static.

This is a one line pointer that testers create as an initial, transitional step into the test
design phase. This is mostly a one line definition of “What” we are going to test with
respect to a certain feature. Usually, test scenarios are an input for the creation of test
cases. In agile projects, Test scenarios are the only test design outputs and no test
cases are written following these. A test scenario might result in multiple tests.

TEST:
Test Case is a commonly used term for a specific test. This is usually the smallest unit
of testing. A Test Case will consist of information such as requirements testing, test
steps, verification steps, prerequisites, outputs, test environment, etc. A set of inputs,
execution preconditions, and expected outcomes developed for a particular objective,
such as to exercise a particular program path or to verify compliance with a specific
requirement.
Test Scenario: Test scenario consists of a detailed test procedure. We can
also say that a test scenario has many test cases associated with it. Before
executing the test scenario we need to think of test cases for each scenario.

Test Script: A Test Script is a set of instructions (written using a programming

language) that is performed on a system under test to verify that the system
performs as expected.

Test scripts is the term used when referring to automated testing. When you're
creating a test script, you are using an automation tool to create your script.
 outlines the testing approach and everything else that surrounds it. It is different
from the test plan, in the sense that a Test strategy is only a sub set of the test
plan. It is a hard core test document that is to an extent generic and static. There
is also an argument about at what levels test strategy or plan is used- but I really
do not see any discerning difference.

Example: Test plan gives the information of who is going to test at what time. For
example: Module 1 is going to be tested by “X tester”. If tester Y replaces X for
some reason, the test plan has to be updated.

On the contrary, test strategy is going to have details like – “Individual modules
are to be tested by test team members. “ In this case, it does not matter who is
testing it- so it’s generic and the change in the team member does not have to be
updated, keeping it static.

(b.) What is the difference between the NOT and the NEG instruction.?

NEG:

 The NEG instruction negates a value by finding 2's complement of its single
operand.
 This simply means multiply operand by -1.
 When a positive value is negated the result is negative.
 A negative value will become positive.
 Zero remains zero.
 For example,
 mov al, -1 ; Load register
 neg al ; AL now has 1

NOT:

NOT - One's Complement Negation (Logical NOT)

Usage: NOT dest

Modifies Flags: None

Inverts the bits of the "dest" operand forming the 1s complement.

Clocks

operands 286 386 486 Size Bytes

reg 2 2 1 2

mem 7 6 3 2-4
Q.8 (a.) What is a short JMP.?

Here we discuss the use of two-byte JMP instructions in x86 Assembly code.
Though we mention only JMP code, what you'll learn here about Relative offsets will
also apply to all Conditional Jumps (such as JE, JG, JC, JZ, JNE, JNG, JNC, JNZ,
etc.) as well!

These are also known as SHORT Relative Jumps. Programs using only
Relative Jump instructions can be relocated anywhere in memory without having to
change the machine code for the Jumps. The first byte of a SHORT Jump is
always EB and the second is a relative offset from 00h to 7Fh for Forward jumps,
and from 80h to FFh for Reverse (or Backward) jumps. [Note: The
offset count always begins at the byte immediately after the JMP instruction
for any type of Relative Jump!]

Whether you use a label to point to the next instruction or a

specific address (as required by MS-Debug's Assemble command),
all Assemblers still figure out the value of the offset byte for you. If you point to
an address that's too far away for a SHORT Jump to reach, the Assembler should
code the instruction as a three-byte NEAR Jump instead* (an Absolute FAR Jump is
one that will jump outside of the present 64 KiB Code Segment). Therefore,
programmers who are trying to keep a routine down to the least number of bytes,
must know the limits of both Forward and Reverse SHORT (and NEAR) Jumps!

(b.) Which JMP instruction allows the program to continue execution at any
memory locations in the systems .?

Forward Jumps are the easiest of the two to work with. They use relative
offset values from 00h to 7Fh which enable program execution to jump to another
instruction with a maximum of 127 bytes in-between them. A jump of any kind to an
instruction immediately following the code, would be just plain illogical; unless you
wanted to reserve two or more bytes there in a tricky manner (without using NOPs;
90h bytes). There may, however, be some cases where one wishes to jump over a
single-byte instruction.

The relative offset byte is essentially an 8-bit signed number where the most
significant bit is 0 for positive numbers. Therefore, all the bytes
from zero through 7Fh (0111 1111 binary) are positive and give us a Forward Jump.

For JMP instructions beginning at Offset 100h, the following is true:

 Second Bytes NextInstruction
Byte Value in-between Location (Hex)
00 0 102
01 1 103
02 2 104
03 3 105
04 4 106
... ... ...
7c 124 17e
7d 125 17f
7e 126 180
7f 127 181

Formula:

JMP_Address + 2 + Second_Byte_value = Next_Instruction_Address

Examples:

Address Code Instruction Formula Examples

0100 EB 03 JMP 0105 100h + 2 + 03h = 105h

0152 EB 23 JMP 0177 152h + 2 + 23h = 177h

0173 EB 47 JMP 01BC 173h + 2 + 47h = 1BCh
0200 EB 7F JMP 0281 200h + 2 + 7Fh = 281h

Reverse (or Backward) SHORT Jumps

Reverse (or Backward) Jumps have relative offset bytes from 80h to FFh. Unlike
Forward Jumps, the seemingly largest offset byte here actually indicates

the shortestbackward jump, because we must use the 2's Complement* of

each negatively signed offset byte! Let's compute the 2's Complement for both the
upper and lower limits of a SHORT Backward Jump:
First, you invert each bit of the offset byte (giving its 1's Complement):
FFh (1111 1111) —> 00h (0000 0000) and
80h (1000 0000) —> 7Fh (0111 1111).
Following this, you simply add 1 to each intermediate value, then make it a negative
number. So, the 2's Complement of each byte is in reality:
FFh —> -01h (a -1) and
80h —> -80h (a -128); these are not only conceptually negative numbers, but
also electronically, or there couldn't be backward jumps (the CPU knows they are
negative offsets because the first byte EB, tells it this is a SHORT Jump instruction
where any value from 80h to FFh is treated as such).
________________
*I'll try not to get too technical here about the mathematics, but I must say this:
If only simple 8-bit signed numbers were used, then 00h would give us
a +0 (positive zero; though strictly speaking, zero is neither positive nor
negative), but an 80h (being 1000 0000 binary) would give us a -
0 (negative zero)! So, one very good reason for using 2's Complement arithmetic is
to avoid havingtwo different zeros!

Let's work through one more example in detail: If we have an offset byte
of AAh, that would be 10101010 in Binary. So, it's 1's complement would be:
01010101 or 55h. Therefore, we'd have a 2's complement of: -56h (-86). But how do
we translate that into a real backwards jump? Well, assuming that the address of our
SHORT JMP code is 0696h, we must first add 2 to get to the address of the
instruction immediately following our JMP; 0698h being that location. And finally add
our negative 2's complement value of -56h to arrive at the next instruction address
of: 0642h. (In MS-DEBUG, if you Enter the bytes EB AA at 696 [-e 696 eb aa],
a disassembly of that address [-u 696 698] will show up as: JMP 0642 on the
screen.)

Since all Jump counts must begin with the byte after the JMP code, Reverse
Jumps must count backwards through their own code! This means that a Reverse
Jump must waste 2 offset value counts in order to jump over itself before getting
back to just the last byte of any instruction preceding it. Practically speaking, this
means you should never see JMP code with an offset byte of FFh, unless the
programmer had something rather "clever" in mind. Most businesses wouldn't
consider such code as being professional though. One possible use of the code EB
FE would be to 'lockup' program execution by putting it into an endless loop; it would
keep repeating the same Jump to itself over and over again! There are few, if
any, practical jumps to the preceding two bytes, because we'd need at least one 2-
byte instruction (such as "JZ elsewhere") to break out of the loop such code would
form!

The furthest back that a SHORT Relative JMP can reach is to the first byte of
any instruction with 127 bytes in-between it and whatever instruction is
immediately after the JMP code. You can see by this,
that both Reverse and Forward Jumps have the same numerical reach, but a
Reverse Jump must count back through its own code first! So in reality, Reverse
Jumps have only a maximum of125 bytes between them and the first byte of
the Next Instruction.

For JMP instructions beginning at Offset 200h, the following is true:

 Second Logical Two's (2's) Next Instruction Bytes
Byte Value NOT (hex) Complement* Location (Hex) in-between
Possibly a
clever trick,
FF 00 -1 201
but very Un-
Professional
FE 01 -2 200 Endless Loop
FD 02 -3 1FF 0
FC 03 -4 1FE 1
FB 04 -5 1FD 2
... ... ... ... ...
83 7C -125 185 122
82 7D -126 184 123
81 7E -127 183 124
80 7F -128 182 125
*Showing the fact that the 8-bit signed bytes here are all negative.

Formula:

JMP_Address + 2 + (2's Complement of Second Byte value)

= Next_Instruction_Address

Two's (2's)
Address Code Instruction Formula Examples
Complement
0147 EB FC JMP 0145 -4 147h + 2 + (- 4) = 145h
0152 EB D7 JMP 012B -29h (-41) 152h + 2 + (- 29h) = 12Bh
0173 EB AF JMP 0124 -51h (-81) 173h + 2 + (- 51h) = 124h
0200 EB 80 JMP 0182 -80h (-128) 200h + 2 + (- 80h) = 182h

Q.9 (a.) What is a Procedure.?

In computer programming, a procedure is a set of coded instructions that tell

a computer how to run a program or calculation. Many different types of
programming languages can be used to build a procedure. Depending on the
programming language, a procedure may also be called a subroutine, subprogram
or function. In database programming, a stored procedure is a set of programming
code (like PL/SQL) that executes a specific query or function. This stored procedure
is often used to execute one or more series of commands, search for, insert, update
or delete data in a database.
 (b.) What is a Interrupt.?

An interrupt is a condition that causes the microprocessor to temporarily

work on a different task, and then later return to its previous task. Interrupts can be
internal or external. Internal interrupts, or "software interrupts," are triggered by a
software instruction and operate similarly to a jump or branch instruction. An external
interrupt, or a "hardware interrupt," is caused by an external hardware module. As
an example, many computer systems use interrupt driven I/O, a process where
pressing a key on the keyboard or clicking a button on the mouse triggers an
interrupt. The processor stops what it is doing, it reads the input from the keyboard
or mouse, and then it returns to the current program.

The image below shows conceptually how an interrupt happens:

The grey bars represent the control flow. The top line is the program that is currently
running, and the bottom bar is the interrupt service routine (ISR). Notice that when the
interrupt (Int) occurs, the program stops executing and the microcontroller begins to
execute the ISR. Once the ISR is complete, the microcontroller returns to processing the
program where it left off.

(c.) What does the IRETD instruction.?

Returns program control from an exception or interrupt handler to a

program or procedure that was interrupted by an exception, an external
interrupt, or a software-generated interrupt. These instructions are also
used to perform a return from a nested task. (A nested task is created
when a CALL instruction is used to initiate a task switch or when an
interrupt or exception causes a task switch to an interrupt or exception
handler.) See the section titled "Task Linking" in Chapter 6 of the IA-32
Intel Architecture Software Developer's Manual, Volume 3.
IRET and IRETD are mnemonics for the same opcode. The IRETD
mnemonic (interrupt return double) is intended for use when returning from
an interrupt when using the 32-bit operand size; however, most assemblers
use the IRET mnemonic interchangeably for both operand sizes.
In Real-Address Mode, the IRET instruction preforms a far return to the
interrupted program or procedure. During this operation, the processor
pops the return instruction pointer, return code segment selector, and
 EFLAGS image from the stack to the EIP, CS, and EFLAGS registers,
respectively, and then resumes execution of the interrupted program or
procedure.
In Protected Mode, the action of the IRET instruction depends on the
settings of the NT (nested task) and VM flags in the EFLAGS register and
the VM flag in the EFLAGS image stored on the current stack. Depending
on the setting of these flags, the processor performs the following types of
interrupt returns:
 Return from virtual-8086 mode.
 Return to virtual-8086 mode.
 Intra-privilege level return.
 Inter-privilege level return.
 Return from nested task (task switch).
If the NT flag (EFLAGS register) is cleared, the IRET instruction performs a
far return from the interrupt procedure, without a task switch. The code
segment being returned to must be equally or less privileged than the
interrupt handler routine (as indicated by the RPL field of the code segment
selector popped from the stack). As with a real-address mode interrupt
return, the IRET instruction pops the return instruction pointer, return code
segment selector, and EFLAGS image from the stack to the EIP, CS, and
EFLAGS registers, respectively, and then resumes execution of the
interrupted program or procedure. If the return is to another privilege level,
the IRET instruction also pops the stack pointer and SS from the stack,
before resuming program execution. If the return is to virtual-8086 mode,
the processor also pops the data segment registers from the stack.
If the NT flag is set, the IRET instruction performs a task switch (return)
from a nested task (a task called with a CALL instruction, an interrupt, or
an exception) back to the calling or inter- rupted task. The updated state of
the task executing the IRET instruction is saved in its TSS. If the task is re-
entered later, the code that follows the IRET instruction is executed.

(d.) What is a null string.?

A null string does not refer to an instance of a [Link] object and any
attempt to call a method on a null string results in a NullReferenceException. e.g.
given below
string str = null;
int len = [Link];

When run the above code it will throw NullReferenceException.

THE END