Register Transfers and

Microoperations
Designing the core of a digital computer
 ▪ A digital system is made by connecting different digit
hardware parts.
▪ These parts work together to process information and
do a specific task.
▪ Digital systems can be small or large. A small system
may use only a few ICs, while a big system may have
many connected computers.
Digital Systems ▪ Digital system design usually follows
modular
a
Basics approach. This means the
system is divided into small,
simple modules. These modules are made using digital
components like: REGISTERS, DECODERS, ARITHMETI
CONTROL LOGIC etc.
▪ All modules are connected using common data paths
and control paths.
▪ Together, they form a complete digital computer
system
 ▪ Digital modules are mainly described by:
1. The registers they have
2. The operations performed on the data in those
registers
▪ The operations done on data stored in registers are
called micro-operations.
Micro- ▪ A micro-operation is an elementary operation
performed on the information stored in one or more
operations registers.
▪ Examples of micro-operations are shift, count, clear,
and load.
REGISTER TRANSFER LANGUAGE

▪ Register Transfer : Specifies how data moves between

registers and what operations are performed.
▪ Language : Like a programming language, it uses
symbols to explain processes clearly and concisely.

▪ RTL is a symbolic way of describing how data is

transferred between registers and what micro - operations
are performed on that data inside a digital system.
 Registers are small storage units
in a computer used to store and
process data.
What are They are named with capital
computer letters, sometimes followed by
numbers, to show their function:
registers? • Examples: MAR, PC, IR, R1
How Registers Store Data
❑ Registers store data as bits (0s and
1s) .
❑ Bits are numbered from right to left,
starting at 0 (rightmost bit is 0)
Example : A 16-bit register can be split :
Bits 0– 7: Low byte (L).
Bits 8– 15: High byte (H).
The register can be referred to as PC(L)
or PC(H) for low and high bytes .
 •Data can be transferred between
registers.
•Example:
•R2 ← R1
Register Transfer: •The ← symbol implies that the
Simple contents of register R1 are
transferred to register R2.
•R1 here is a source register while R2
is a destination register .
•The data in R1 remains unchanged
after the transfer.
 ▪ A path is needed to move data from one
register to another.
▪ Data moves from the source register (R1)
to the destination register (R2).
▪ The destination register must have
parallel load capability.
▪ This means it should load all bits at the same
Register Transfer: time, not one by one.
Important Points ▪ Data transfer happens only when the
control unit gives permission.
▪ Inside a processor, many registers use a
common data bus to transfer data.
▪ The bus size must be equal to the
register size.
▪ Example: If a register is 8 - bit, the data bus
must also be 8 - bit wide.
 ▪ In a digital system, data transfer does
not happen all the time. It happens only
when a control condition is true.
▪ This condition is written using an IF –
THEN statement in RTL.
▪ IF the control signal is 1 (true),
Register Transfer:
Conditional THEN the data transfer or micro -
operation is performed.
▪ If the control signal is 0 (false),
the operation does not happen.
▪ The control signal is usually generated by
the control unit.
 ▪ Example:
IF P = 1, THEN R2 ← R1
▪ where P is a control signal generated in
the control section.
▪ This means: data from register R1 is
Register Transfer: transferred to R2 only when P = 1.
Conditional ▪ In RTL, it can be written as:
P: R2 ← R1.
The control function is included in the
transfer statement. It is terminated by a
colon (:) and placed in front of the actual
transfer statement
HARDWARE CONSTRUCTION FOR CONTROL FUNCTION
▪ A control function decides when a
register transfer should occur. This
control function is implemented using
hardware logic circuits.
▪ The control signal is connected to the
load (enable) input of the destination
register.
▪ When the control signal P = 1:
▪ The load input becomes active
▪ Data is transferred from the source
register to the destination register.
▪ When the control signal P = 0:
▪ The load input is inactive
▪ No data transfer takes place .
HARDWARE CONSTRUCTION FOR CONTROL
FUNCTION
▪ The control signal P is synchronized
with the system clock.
▪ The transfer happens only at the rising
edge of the clock pulse.
▪ At time t, control signal P becomes
active.
▪ The actual transfer to R2 occurs at
the next clock pulse transition (t + 1).
▪ If P remains active, the transfer will
repeat with every clock pulse.
 • All micro - operations written on the
same line are executed at the same
time if there is no conflict.
Register • A conflict happens if two different
Transfer: registers try to transfer data to the
same destination simultaneously.
Simultaneous
• Example: 𝑅 1← 𝑅 2, 𝑅 1← 𝑅 3 is invalid
because R1 cannot accept data from
both R2 and R3 at once.
 T: R2 ← R1, R1← R2
(Will occur
•Conditional Transfer
only when T is 1)
(Swaps
• Simultaneous Operations
Register Transfer: the contents of R1 and R2
EXAMPLE during one clock cycle)

•Note: Simultaneous operations

are possible with registers that
have edge triggered flip flops.
BUS SYSTEM
Designing the CPU
 Need for a Common Bus
• A digital computer has multiple registers
that need to transfer information.
• Using separate lines between every pair
of registers would require excessive
wiring .
Efficient Transfer with a Common Bus
Bus and • A common bus system provides a shared
path for transferring binary information.
Memory
• Each bit of a register is transferred
Transfers through a corresponding line in the bus.
• Control signals decide which register is
active during a transfer.
Construction of a Bus System
• Multiplexers are used to construct the
bus system.
• The multiplexers select the source
register and place its data on the bus.
Example: Four
-Register Bus System

• Each register has 4 bits, numbered 0 to [Link] bus includes four 4 ×1

multiplexers, one for each bit position (0, 1, 2, 3).Selection inputs S1
and S0 control which register's data is transferred.
Example: Four
-Register Bus System
• Each bit position of the
registers connects to the
corresponding multiplexer
input.
• For example:
• MUX 0 handles the 0 th
bit of all registers.
• MUX 1 handles the 1st
bit , and so on.

1. A specific register is selected by setting the appropriate values

S1and
of S0.
2. The binary information from the selected register is placed on the bus for
transfer.
This system simplifies interconnections and reduces the wiring needed for data
transfer between multiple registers.
 Symbolic Representation of Bus Transfers

Including the Bus: Implied Bus:

•Example: BUS ← C, R1 ← BUS •Example: R1 ← C
•Register C places its •Assumes the bus is used
content on the bus. for the transfer.
•The bus content is loaded •The designer activates
into R1. the necessary control
signals to enable the
transfer via the bus
Three-State Bus Buffers
▪ A bus system can be
constructed with
three - state gates
instead of
multiplexers.
▪ Three - state gate has
a third state called
“High Impedance”
state which behaves
like an open circuit.
Memory Transfer
Designing the CPU
Arithmetic Operations
Designing the CPU
 Types of Microoperations
A microoperation is an elementary operation performed with the data stored in registe

Register Transfer Microoperations : Transfer binary

information from one register to another

Arithmetic Microoperations : Perform arithmetic operations

(e.g., addition, subtraction) on numeric data stored in
registers
Logic Microoperations : Perform bit manipulation
operations on non -numeric data stored in registers.
Shift Microoperations : Perform shift operations (e.g.,
left or right shifts) on data stored in registers [Link]
Arithmetic Operations
 • A binary adder adds binary numbers of any length.
Binary Adder • It is constructed by cascading multiple full - adders.
• Each full - adder’s output carry is connected to the
input carry of the next full - adder
 • Inputs:
• Augend bits A 0 ,A 1,A 2 ,A 3 (from register R 1).
• Addend bits B 0 ,B 1,B 2 ,B 3 (from register R 2 ).

Binary Adder • Carry Chain:

• Input carry C 0 is provided externally.
• Output carry C 4 is generated after the addition.
• Outputs:
• Sum bits S 0 ,S 1,S 2 ,S 3
 Combines binary addition
and subtraction into a
single circuit.

Binary Adder A single circuit performs

Subtractor both addition and
subtraction efficiently.

Circuit
The mode control (M)
allows dynamic switching
between operations
Adder Subtractor Circuit
o M=0: Circuit acts as an Adder. o M=1: Circuit acts as a Subtractor.
▪ B is passed directly to the full
-adders. ▪ B is complemented (via XOR gates).
▪ C0=0 (no initial carry). ▪ C0= 1 (adds 1 for the 2’s complement).
▪ Performs A+B ▪ ′s complementof B)
Performs A+(2
Adder Subtractor Circuit
Binary Incrementor
Binary Incrementer
Arithmetic Circuits

• Goal: To create one composite circuit that can perform variety

of arithmetic microoperations.
• The basic component of an arithmetic circuit is the parallel
adder .
• By controlling the data inputs to the adder, it is possible to
obtain different types of arithmetic operations.
• It has four full - adder circuits that constitute the 4 - bit adder
and four multiplexers for choosing different operations.
 • These control the
Arithmetic inputs to the adder.
Circuits: • Each multiplexer
determines what
Multiplexer data is sent to the
Section binary adder based
on two selection
inputs ( 𝑆 1 a n d
𝑆0 ).
Arithmetic Circuits:
adder Section
• Together they form a 4 - bit
parallel adder.
• Each full adder handles one
bit
• A is given to FA directly.
• B is given via MUX
Arithmetic Circuit
• 4 Full Adders (FA) form the core
adder.
• 4 × 1 Multiplexers (MUX) at the Y
inputs of each FA.
• The MUXs control which data is
fed to the adder, based on the
select lines S1 and S0.
• Inputs to the MUXs for each bit I
are: Bi, Bi’, 0 and 1.
Arithmetic Circuit
• The output of the binary adder is
calculated from the following
arithmetic sum:

D=A+Y+Cin
• A: The first operand.
• Y: The second operand,
determined by the multiplexers.
• Cin : Optional carry input
Arithmetic Circuit
Back Back 1
Logic Operations
Designing the CPU
 Logic Microoperations
• Logic microoperations perform binary operations on each bit of a register.
• These operations treat each bit independently as a binary variable (0 or 1)
and apply logical operations like AND, OR, XOR, etc.
• Each bit of the registers is operated on separately .

Example:

• If P=1 (control condition is true), perform the XOR operation between R1 and
R2.
• Store the result back into R1.
• Let R1=1010 and 𝑅 2=1100.
• XOR Operation: 𝑅 1 ⊕ 𝑅 2
 • There are 16 different logic operations that
can be performed with two binary variables.
List of Logic
• They can be determined from all possible
Microoperations truth tables obtained with two binary
variables
 Boolean
operations
expressed in
algebraic form
 • The hardware implementation involves
Logic logic gates for performing the required
logic microoperations on individual bits
Microoperation of the registers.
s: Hardware • Only four basic logic operations —AND,
Implementation OR, XOR (Exclusive -OR), and Complement —
are implemented, as all other
operations can be derived from these.
• A multiplexer (MUX) is used to select
the desired microoperation based on
the control (selection) inputs.
Back Back 1
 Logic Operations: Applications
Logic microoperations allow manipulation of specific bits in
a register .
These operations are essential for tasks like;
1. changing bit values
2. deleting bits
3. inserting new ones .

[Link]
1. Selective set
• Set bits in register A to 1 wherever corresponding bits in
register B are 1.
• Use the OR microoperation.

A before : 1010
B : 1100
A after : 1110

[Link]
 Logic Operations: Applications
2. Selective Complement
• Flip (complement) bits in A wherever corresponding
bits in B are 1.
• Use the XOR microoperation.

A before : 1010
B : 1100
A after : 0110

[Link]
 Logic Operations: Applications
3. Selective Clear
• Clear (set to 0) bits in A wherever corresponding bits
in B are 1.
• Use the AND with NOT (B') microoperation.

A before : 1010
B : 1100
A after : 0010
[Link]
 Logic Operations: Applications
4. Mask Operation
• Clear bits in A wherever corresponding bits in B are
0.
• Use the AND microoperation.

A before : 1010
B : 1100
A after : 1000
[Link]
 Logic Operations: Applications
5. Insert Operation
• Replace a group of bits in A with new values.
• Steps:
1. Mask the unwanted bits using an AND operation.
2. Insert new bits using an OR operation

[Link]
 Logic Operations: Applications
5. Insert Operation
• Example: Register A contains eight bits, 0110 1010. We want to replace
leftmost bits by the value 1001.
1. Maskthe unwanted bits using an AND operation.

2. Insert new bits using an OR operation

[Link]
 Logic Operations: Applications
6. clear Operation
• Check if two registers (A and B) are equal.
• Use the XOR microoperation; result is all 0s if A
equals B .
A : 1010
B : 1010
A after: 0000

[Link]
Shift Micro
Operations
Designing the CPU Core
Shift Microoperations
• Shift microoperations are used to move the contents of a register
left or right.
• They are helpful in serial data transfer and are often combined
with arithmetic, logic, and other data -processing tasks .

How It Works??
• Bits are moved one position, and new data (from the serial input)
is added to the empty position.
• Left shift: New data comes into the rightmost position.
• Right shift: New data comes into the leftmost position.
3 Types of shifts

Logical Shift Circular Shift Arithmetic Shift

Shift Microoperations: Summary
Hardware Implementation of Shift
Operations

How it works??
• A multiplexercontrols the
direction of the shift:
• Shift Right: When selection
input S=0.
• Shift Left: When selection
input S=1.
 Hardware
Implementation
of Shift
Operations
Combining it all……
Designing the CPU
Logic Circuit

Arithmetic Circuit

ONE STAGE OF
ARITHMETIC LOGIC
SHIFT UNIT
Operations Supported

1. 8 Arithmetic
Operations
(Controlled by S1 ,S0
, Ci ).
• S3 S2 = 00
2. 4 Logic Operations
(Controlled by S1
,S0 ).
• S3 S2 = 01
3. 2 Shift Operations
(Controlled by S3
,S2 ).
Thanks
Reference
Computer System Architecture,
by
Morris Mano,
3rd Edition
Pg 93-119