MODULE-3

required to be generated in
Ihere are many applications in which digital outputs are
accordance with the sequence in which the input signals are received. This requirement
cannot be satisfied using a combinational logic system. These appications require
input conditions but
vputs to be generated that are not ony dependent on the present
history 1s provided by
sO depend upon the past history of these inputs. The past
feedback from the output back to the input.
Fig- 3.1.1 shows the
block diagram of sequential Combinational
circuit /Finite State Machine
Inputs circuit Outputs:
(FSM). As shown in the (Combinational
Fig. 3.1.1, memory elements component)
are Connected to the Memory
elements
combinational circuit as a (Sequential Next state
Present state
feedback path. componerit)
The information stored
in the memory elements at Sequential circuit
any given time defines the Fig. 3.1.1 Block diagram of sequential circuit / FSM
present state of the
sequential circuit. The present state and the external inputs determine the outputs and
the next state of the sequential circuit. Thus we can specify the sequential circuit by a
time sequence of external inputs, internal states (present states and next states), and
outputs. The counters and registers are the common examples of sequential circuits.
binay elernen
The memory element used in sequential circuits is a fAlip-flop which is capable of storing 1-bit
binary information.

3.1.1 Comparison between Combinational and Sequential Logic Circuits

Sr. Combinational circuits Sequential circuits
No.
In combinational circuits, the
output n sequential circuits, the output varlables
Variables are at all times dependent on the depend not only on the present inpu
Combination of input variables. variables but they also depend upon the the
past history of these input variables.
2. Memory unit is not required
in Memory unit is required to store the past
combinational circuits.
history of input variables in the Sequential
citcuit.
 3
Combinational circuits are faster in speed Sequential circuits are slower than the
because the delay between input and output combinational circuits.
is due to
propagation delay of gates.
4.
Combinational circuits are easy to design. Sequential circuits are comparatively harder
to design.
5. Parallel adder is a combinational circuit. Serial adder is a sequential circuit.
Table 3.1.1 Comparison between combinational and sequential circuts
3.1.2Clock
Clock
Aclock signal is a particular type of signal period
that oscillates between a high and a low state
and is utilized to co-ordinate actions of
Flg. 3.1.2 Clock signal
circuits. It is produced by a clock generator.
The most common clock signal is in the form
of a square wave with a 50 % duty cycle, usually with a fixed, constant frequency
as

shown in Fig. 3.1.2. Circuits using the clock signal for synchronization may becomne
in
active at either the rising edge, falling edge or in the case of double data rate, both
the rising and in the falling edges of the clock cycle.
cycle.
The time required to complete one cycle is called 'clock period' or 'clock
as shown
Ideally, the clock signal should have sharp transitions from one level to other
in Fig. 3.1.2.
Sequential
3.1.3 Comparison between Synchronous and Asynchronous
Circuits
These circuits are
We have already introduced to synchronous sequential circuits.
sequential
further classified depending on the timing of their signals: Synchronous
circuits, signals
circuits and asynchronous sequential circuits. In synchronous sequential
of time. In asynchronous
can affect the memory elements only at discrete instants of
memory element at any instant
sequential circuits change in input signals can affect
time.

Synchronous sequential circuits Asynchronous sequential circuits

Sr. No.
asynchronous circuits, memory
1. In synchronous circuits, memory elements In
elements are either uncocked flip-flops or
are clocked flip-flops.
time delay elements.
change in In asynchronous circuits change in input
2. In synchronous circuits, the
memory element signals can affect memory element at any
input signals can affect signal. instant of time.
upon activation of clock
 3.2 The Basic Bistable Element
used in latches and flip-flops. The
The Fig. 3.2.1 shows the basic bistable element
crosS-coupled inverters, ie.,
basic bistable element has two outputs Q and Q. It has two
the second inverter and the
the output of the first inverter is connected as an input to
first inverter.
output of second inverter is connected as an input to the

B
B
(a) Using basic inverter (b) Using NAND gates (c) Using NOR gates
Fig. 3.2.1 Basic bistable element (1-bit memory cel!)

Thebasic bistable element circuit has two stable states logic 0 and logic 1, hernce ne
name bistable'. To illustrate this, assume A =0. When A = 0. the output of inverter 15
2, A = B B=1.
1 (A), ie., Q= 1. Since the output of inverter 1 is the input to the inverter 2,
Consequently, the output of nverter 2, 1e., Bis 0. Since the output of the inverter 2
connected to the input of the inverter 1, Q = B = A = 0. We have assumned Same value
similar
for A. Thus, the circuit is stable with Q= A = B = 0 and O=A = B = 1. Using
explanation it is easy to show that if it is assumed that A = 1, the basic bistable element
= B= 1and Q=A = B = 0. This is a condition of
is stable with Q = A second stable C
element.
the basic bistable
 binary elements,
The two stable states of basic bistable elements are used to store two
and state Q= 01s
0 and 1. In positive logic system, state O = 1 is used to store logic 1,
used to store logic 0. It is important to note that the two outputs are complementary.
That is when Q = 0, Q = 1; and when Q = 1, Q= 0.
From the above discussion we can note following things about the
basic bistable
element.

1. The outputs Q and Q are always complementary.

as
2. The circuit has two stable states. The state corresponds to Q = 1is referred to
referred to as 0 state or
1state or set state and state corresponds to O = 0 is
Reset state.
remain in the set state and if the circuit is
3. It the circuit is in the set (1) state, it will
property of the circuit
in the reset (0) state, it will remain in the reset state. This
Therefore, the circuit is called a
shows that it can store 1-bit of digital information.
1-bit memory cell.
locked or latched in the circuit.
4. The 1-bit information stored in the circuit is
Therefore, this circuit is also referred to as a latch.
Dec.10,15
3.3 Latches Feb. 07 08, 09, June-10, Dec.-10,11, Jan. 14, July- 11,14,15,
basic building blocks
Latches and flip-flops both are bistable elements. These are the
between latches and flip-flops is in the
of most sequential circuits. The main difference
for a sequential device
method used for changing their state. We use the name flip-flop
only at times determined by
that normally samples its inputs and changes its outputs latch for asequential device that
clocking signal. On the other hand, we use the. name
accordingly at any time
checks all of its inputs continuously and changes its outputs provided with the latch.
independent of a clocking signal. Marny times enable sigrnal is
input changes. But when enable
When enable signal is active output changes occur as
affect output.
signal is not activated input changes do not
3.3.1 SR Latch
3.3.1. SRLatch using NAND Gate
which is 1-bit S (Set)
Fig. 3.3.1 shows SR latch
memory cell. As shown in the Fig.
3.3.1, two D
enter the
nverters 3 and 4 are connected to
and
digital information. Input for gate 3 is Scalled
is also
nput for gate 4 is R. This latch R(Reset)
RS latch.
Fig. 3.3.1 SR latch
 ror understanding the cireuit operation, we must first determine the output of
NAND gate whose one of the input is logic 0 and accordingly we have to determine the
output of other NAND gate in the cross coupled circuit. Because the output of NAND
gate is 1 if any one input is 0. The circuit operation is as follows. n Fig. 3.3.2, the
output of shaded NAND gate is determined first, and the 0 input that decides the
output of shaded NAND as 1 is shown in bold.
Case 1: S = R=0
In this case, S = R= 1. fO is 1, Q and B inputs for NAND gate 2 are both 1
and hence output Q= 0. Since Q = 0 and ` = 1, the output ofNAND gate 1 is
1, ie. Q= 1.
If Q is 0, Q and R inputs for NAND gate 2 are 0 and 1, and hence output
Q=1. Since Q = 1 and S = 1,the output of NAND gate 1 is 0, i.e., Q = 0.
Initial state :Q=0, =1 Initial state : Q=1, Q=0

-oQ=1

o
R R
1

Fig. 3.3.2
This shows that when S = R 0, the outputs do not change.
Case 2:S =1 and R= 0
o Q=1
In this case, S = 0and R = 1. Since 0
S = 0, the output of NAND gate 1,
Q = 1 (Recall that, for NAND any
one or more input is 0, the output is R
1) For NAND gate 2, both inputs Q 1
and Rare 1, thus output Q= 0. Fig. 3.3.3
The inpputs S = 1and R=0, makes = 1, ie., set state
Case 3 :S=0 and R=1 Q=0
In this case, S = 1 and R = 0. Since
R= 0, the output of NAND gate 2,
õ= 1. Por NAND gate 1, both
inputs Q and S are 1, thus output R
0
Q=0.
Fig. 3.3A
 The inputs S = 0 and R= 1, makes Q=0, i.e., reset state.
Case 4: S = 1and R =1
When S = R= 1, both the outputs O and try to become 1which is not allowed
and therefore, this input condition is prohibited.
[Link] SR Latch using NOR Gates
Fig. 3.3.5 shows the SR latch using two NOR
gates. As shown in the Fig. 3.3.5, the two NOR R(Reset) Q

gates are cross coupled so that the output of NOR

gate 1 is connected to one of the inputs of NOR
gate 2 and vice versa. The latch has two outputs
Q and Q, and two inputs, set and reset.
S (Set)
Before going to analyse the SR latch, we recall
that a logic 1 at any input of a NOR gate forces Fig. 3.3.5 SR latch using NOR gates
its output to a logic 0. Let us understand the
operation of this circuit for various input/output R(Reset)
possibilities.

CASE 1: S = 1and R=0

In this case, S input of the NOR gate 2 is at S (Set) 0

logic 1, hence its output, Q is at logic 0. Both
inputs to NOR gate 1 are now at logic 0. So that Fig. 3.3.5 (a)
its output, Q is at logic 1. R (Reset) Q
CASE 2:S = 0 and R=1
1 is at
In this case, R input of the NOR gate
logic 1, hence its output, Qis at logic 0. Both
So that
nputs to NOR gate 2 are now at logic 0. s (Set)
-
its output, Q is at logic 1. 0

Fig. 3.3.5 (b)

CASE 3:S =0 and R = 0
R(Reset)
Initially, Q=1and Q =0 Q
and Q = 0 .
Let us assume that initially Q= 1
0

With Q = 0, both inputs to NOR gate 1 are at

1,
logic 0. So its output, Q is at logic 1. With Q= its
1, hence
One input of NOR gate 2 is at logic
1

output, O is at logic 0. This shows that

when S s (Set) 0
2 0
and R both are low (at logic 0) the output state Flg. 3.3.5 (c)
does not change.
 Initially, Q = 0 and Q = 1 R(Reset)
Let us make opposite assumption that Q= 0
and Q =1. With Q = 1, one input of NOR gate 1
is at logic 1, hence its output Q is at logic 0.
With Q= 0, both inputs to NOR gate 2 are at 2
S (Set) 1
logic 0. So its output Q is at logic 1. In this case 0

also there is no change in the output state. Fig. 3.3.5 (d)

CASE 4: S= 1 and R=1

the outputs of both NOR gates to the
When R and S both are at logic 1, they force
state. (Q=0 and Ì = 0). So we call this an indeterminate or prohibited state, and
low
condition in the truth table as an asterisk (). This condition also violates
represent this
to be the complement of Q. Thus in
the basic definition of a latch that requires
operation this condition must. be avoided by making sure that 1's are not
normal
applied to both the inputs simultaneously.
symbol and truth table for SR latch. Looking at Fig. 3.3.6 we can
Fig. 3.3.6 shows the
:
summarize the operation of SR latch as follows
both inputs low, the output does not change and latch remains latched in its
With because nothing changes.
last state. This condition is called inactive state
input is low and S input is high, the Q output of latch is set (at logic 1).
When R
Q output of latch is reset (at
When R input is high and S input is low, the
logic 0).
unpredictable. This is called
When R and S inputs both are high, output is
indeterminate condition.

R State
0 0
No change(NC)
0 1

0 0
S Reset
1

1 0 0
R Set
0 1 1

1 0 X
Indeterminate
1 1 X

(a) Symbol (b) Truth table

Fig. 3.3.6
 3.3.2 An Application of the SR Latch : ASwitch Debouncer
For interfacing keys to the digital
systems, usually push bottom keys are V
used. These push button keys when
pressed bounces a few times, closing and B Ve
opening the contacts before providing V
V
steady reading, as shown in the
Fig. 3.3.7. Reading taken during
bouncing period may be faulty. This Fig. 3.3.7 Effect of key debounce
problem is known as key debounce. The
problem of key debounce is undesirable SA
and it must be avoided.
One way to avoid key debounce
problem is to use SR latch. The circuit
used to avoid keybounce with SR latch is
called a switch debouncer. The Fig. 3.3.7 Fig. 3.3.7 (a) Switch debouncer
shows the switch debouncer circuit and
VA
its waveforms. When key is at position
V
A, the output of SR latch is logic 1, and
when key is at position B, the output of
SR latch is logic 0. It is important to Vet
note that, when key is in between A and V
B, SR inputs are 00 and hence output
does not change, preventing debouncing
of key output. In other words, we can
say that the output does not change
during transition period, eliminating key
debounce.

Fig. 3.3.7 (b) Wavefons of switch debouncer

3.3.3 The S R Latch
From SR latch using two NOR gates we can construct the equivalent SR latch using
two NAND gates, as shown in the Fig. 3.3.8.
truth table for
Looking at Fig. 3.3.8, we can call this latch RSlatch or SR latch. The
this latch is different fromn that for the NOR gate latch. It is shown in Fig. 3.3.9. Here, R
complemented form.
d Sinputs are applied in the
R (Reset)
1 Q
R(Reset)
D
2 S (Set)
S (Set)

gate
(a) Basic circuit (b) Roplacing NOR gate by bubbled AND
Flg. 3.3.8

R(Reset) R

-Q
S (Set)
(c) Shifing bubble (d) Equivalent NAND gate SR latch
Fig. 3.3.8

State
X
Indeterminate
X
0 1
Set

R 0 0
Reset

0
1 1
No change(NC)

(a) Logic symbol (b)Truth table

Flg. 3.3.9
To understand how this circuit functions, recall that a low on any
input to a NAND
gate forces its output high. Thus a low on the S input will set the RS latch. i.e. O=1 and
Õ=0. A low on the R input will reset it, ie. Q=0 and Q =1, If both R and S are
the latch will remain in its previous state. When both R and S high,
inputs are low, the output
is invalid.
 3.3,4 The Gated SR Latch
that
In the SR latch we have seen EN S RQn Qn+1 State
after
output changes occur immediately 1 0 0 No Change (NC)
latch is
the input changes occur i.e. the 1 0 1 1
sensitive to its S and R inputs at all 0 1 Reset
1
times. However, it can easily be 1 0 1 1
to create a latch that is
modified 1 0 0 Set
1
sensitive to these inputs only when an 1 1 0 1
enable input is active. Such a latch with 1 1 1 0 X Indeterminate
SR
enable input is known as gated 1 1 1 X
latch. It is as shown in the Fig. 3.3.12. 0 X X No Change (NC)
The Table 3.3.1 shows the truth table X X 1 1
tor gated latch. As shown by truth
table, the circuit behaves like a SR latch Table 3.3.1 Truth table for SR latch with enable
Input
when EN = 1, and retains its previous
state when EN = 0.
 EN
EN
R

R
D (b) Logic symbol
gates
(a) SR latch with enable input using NAND
Fig. 3.3.12

3.3.5 Gated SR Latch using NOR Gates

We can construct SR latch using NOR gates R
as shoWn Fig. 3.3.13. Here, AND gates are
used to implement gating function. AND gates
high. EN
are active only when enable input is
When enable input is low, AND gate outputs
are low and latch is in no-change state. S

Fig. 3.3.13 SR latch using NOR gates

3.3.6 The Gated D Latch
can realize that when both inputs are
Looking at the truth table of the SR latch we and
same the output either does not change or it is invalid (Inputs ’ 00, no change
applications, these input conditions are not
inputs ’ 11, invalid). In many practical
making them complement of each
required. These input conditions can be avoided by
as D latch.
other. This modified SR latch is known
Fig. 3.3.14 shows the D D
Q
latch. The NAND gates 1,
2, 3 and 4 form the basic EN
with enable EN
SR latch
input. The fifth NAND
is used to
gate R
provide the complemented (a) D latch (b) Logic symbol
inputs. Fig. 3.3.14

As shown in the Fig. 3.3.14, D input goes directly to the S input, and its complement
is applied to the R input, through gate 5. Therefore, only two input conditions exists,
either S =0 and R=1or S = 1 and k = 0. The truth table for D latch is as shówn in the
Table 3.3.2.
 Flilp-Flops
Dgital System Design 3- 13

EN D State
1 X 0 Resel
1 X 1 Set
0 X X No Change (NC)
Table 3.3.2 Truth table for D latch
As shown in the truth table, the Q output folows the
EN 01 11 10
D input. For this reason D latch is sometimes called
transparent latch. 0

Looking at the truth table for D latch with enable input 1 0 1 1

and simplifying Qni function by k-map we get the

characteristicequation for D latch with enable input as Qn+ EN-D +EN-Q,
Qn+ = EN D+ EN-Qn This is illustrated in Fig. 3.3.15. Fig. 3.3.15 Characteristic
equation
 3.5 Master-Slave SR Flip-Flop Feb 0405 0TAug.«09 June 10,11

A master-slave flip-flop is
constructed from two flip-flops. One Q S
circuit serves as a master and the Master Slave
other as a slave, and the overall R R
circuit is referred to as a

master-slave flip-flop. Fig. 3.5.l CP

shows SR master-slave flip-flop. It Fig. 3.5.1 Master-slave SR flip-flop
consists of a master flip-flop, a slave
flip-flop, and an inverter. Both the flip-flops are positive level triggered, but inverter
connected at the clock input of the slave flip-flop forces it to trigger at the negative
level.
The output state of the master flip-flop is determined by the S and R inputs at the
positive clock pulse. The output state of the master is then transferred as an input to
the slave flip-flop. The slave flip-flop uses this input at the negative clock pulse to
determine its output state. The Fig. 3.5.2 illustrates the operation of the master-slave
flip-flop.
CP

Master output

Slave output:
Triggered Master Slave Master Slave Master Slave
sets resets resets NC NC
flip-flop sets
Fia. 3.5.2 Input and output wavefoms for master-slave flip-flop
3.6 Master-Slave JK Flip-Flop Dec.-11,15, Jam.-1
Feb.-2000, 07, Aug.-2000,06,09,11, June-10, July-11,2,15,
Q
Fig. 3.6.1 shows one way to build
a JK master-slave flip-flop. It consists CLK Master Slave
of cdocked JK flip-flop as a master
K
and cdocked JK flip-flop as a slave. K

The output of the master flip-flop is

fed as an input to the slave flip-flop. Fig. 3.6.1 Master-slave JK flip-fop
As shown in the Fig. 3.6.1, clock
signal is connected directly to the master flip-flop, but it is connected through inverter to
the slave flip-flop. Therefore, the information presernt at the Jand K inputs is transmitted
to the output of master flip-lop on the positive clock pulse and it is held there until the
negative cdock pulse occurs, after which it is allowed to pass through to the output of
släve flip-flop.
When J = 1 and K = 0, the master sets on the positive cdock. The high Y output of
the master drives the J input of the slave, so at negative clock, slave sets, copying the
action of the master.
When J = 0 and K=1, the master resets on the positive clock. The high Y output of
the master goes to the K input of the slave. Therefore, at the negative clock slave resets,
again copying the action of the master.
When J = 1and K=1, master toggles on the positive clock and slave then copies the
output of master on the negative clock.
When J =K = 0, the output of master remains same at the positive clock. Thus
output of slave also remains same at the negative clock The Fig. 3.6.2 shows the truth
table and symbol for master-slave JK flip-flop.
PR
CUK J K

0 a, (No change) J
0 (Reset)
CLK
1 1 (Set)
K
1 1 O, (Toggle)
(a) Truth table CLK
(b) Symbol
 Note : It is important to note that clock input of the master-slave flip-flop is not edge
triggered.
Fig. 3.6.3 shows the master slave JK flip-flop using only NAND gates. It consists of
clocked JK flip-flop as a master and clocked SR flip-flop as a slave. The output of the
master tlip-tlop is fed as an input to the slaye flip-flop. As shown in the Fig. 3.6.3, clock
signal is Connected directly to the master flip-flop, but it is connected through inverter to
the slave flip-flop. Therefore, the information present at the J and K inputs is transmitted
to the output of master flip-flop on the positive clock pulse and it is held there until the
negative cock pulse occurs, after which it is allowed to pass through to the output of
slave flip-flop. The output of the slave lip-flop is connected as a third input of the
master JK flip-flop.
Master
Slave

Ho Q

CP

K R

Fig. 3.6.3 Master-slave JK flip-lop

1 2 3 4 5
CP

K
Master
output
(Slave S)
Master ():
output
(Slave R)

Output
Slave Q
Triggered Sve Master Slave Master Slave Master Sláve
lip-flop Master Slave Master Slave Master
resets resets NC
sets sets NC NC NC toggles sets toggles resets
(sets) (resets)
Fla. 3.6A Input and output wavefoms of master-slave JK Nip-flop
HNICAL PUBLICATIONS- An up thrust for knowledge
 clock. "The high
the master sets on the positive output of
WhenJ=1 and K = 0,
slave, so at negative clock, slave sets, copying the
the master drives the Sinput of the
action of the master.
the positve CIÛCk. ie ngn Y output of
When J =0and K=1., the master resets on at the negative clock slave reset
input of the slave. Therefore,
ne master goes to the R
again copying the action of the master.
=1,master toggles on the positive clock and slave then copies t.
When J=1 and K the mastos
master on the negative clock. At this instant, feedback inputs to
Output of flip-flon t
complemented but as it is negative half of the clock pulse master
flip-flop are race-around condition. Fig. 3.6.4 shows input and outout
inactive. This prevents
page.)
waveforms of master-slave JK flip-flop. (See Fig. 3.6.4 on previous
Catching problem
flip-flop is a latch and it is enabled
Refer Fig. 3.6.3. The master of master-slave JK
the slave latch is in 1-state, then a
during the entire high level of the clock input. Thus if
1 causes the master latch to
logic-1 on the K input line while the clock input signal is
when the control signal
reset. This subsequently results in the slave becoming reset
returns to 0. This behaviour is known as 0's catching.
J input the while
In similar manner, if the slave is storing a 0, then a logic 1 on the
results in the
the clock signal is 1 causes the master latch to be set, which subsequently
clock signal. This
setting of the slave upon the occurrence of the falling edge of the
behaviour is known as 1's catching.
Hence it is
In many applications, the 0's and l's catching behaviour is undésirable.
normally recommended that the Jand K input values should be held fixed during the
entire interval that the master is enabled. To satisfy this constraint, any changes in the J
and Kinputs must occur while the clock signal is 0.
MODULE-4
MODULE-5