LAB ASSESSMENT TASK 1

Name : Omkar Umesh Jawalikar

Registration no. : 22BCE2223

SLOT : L33 + L34

Course Code : BECE102P

Faculty Name : Dr. Abhishek N. Tripathi

Course Name : Digital Systems Design

Lab
Q.1 Write a Verilog gate-level and data
flow description with the test bench of
the circuit shown below.

Gate level :

module ques1(a,b,c,d,f);
input a,b,c,d;
output f;
wire wnc,w1,w2,w3;
not n1(wnc,c);
and a1(w1,c,d);
and a2(w2,b,wnc);
or o1(w3,w1,b);
and a3(w4,w3,a);
or o2(f,w4,w2);
endmodule
Dataflow:

module ques1df(a,b,c,d,f);
input a, b, c, d;
output f;
wire wnc, w1, w2, w3, w4;

assign wnc = ~c;

assign w1 = c & d;
assign w2 = b & wnc;
assign w3 = w1 | b;
assign w4 = w3 & a;
assign f = w4 | w2;

endmodule
Testbench:

module testbench;

reg a, b, c, d;
wire f;

ques1df uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);

reg clk = 0;
always #5 clk = ~clk;

initial begin
a = 0; b = 0; c = 0; d = 0;
#5 a = 1; b = 0; c = 0; d = 1;
#5 a = 0; b = 1; c = 1; d = 0;
#5 a = 1; b = 1; c = 1; d = 1;
 $display("a=%b, b=%b, c=%b,
d=%b, f=%b", a, b, c, d, f);
$finish;
end

endmodule
 LAB ASSESSMENT TASK 2

Name : Omkar Umesh Jawalikar

Registration no. : 22BCE2223

SLOT : L33 + L34

Course Code : BECE102P

Faculty Name : Dr. Abhishek N. Tripathi

Course Name : Digital Systems Design

Lab
Q.1 Write Gate level, Data flow, and
Behavioral modeling with the Test bench
of the following Combinational
circuits:

a. Full adder

Gate level:

module fulladder_str(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire x1,x2,x3;
xor(x1,a,b);
xor(sum,x1,cin);
and(x2,x1,cin);
and(x3,a,b);
or(cout,x2,x3);
endmodule
Data flow :

module fulladder_df(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|cin&(a^b);
endmodule

Behavioral model :

module full_adder_beh(A, B, Cin, S,

Cout);
input wire A, B, Cin;
output reg S, Cout;
always @(A or B or Cin)
begin
case ({A,B,Cin})
3'b000: begin S = 0; Cout = 0; end
3'b001: begin S = 1; Cout = 0; end
3'b010: begin S = 1; Cout = 0; end
3'b011: begin S = 0; Cout = 1; end
3'b100: begin S = 1; Cout = 0; end
3'b101: begin S = 0; Cout = 1; end
3'b110: begin S = 0; Cout = 1; end
3'b111: begin S = 1; Cout = 1; end
endcase
end
endmodule

Test Bench :

module fulladder_test;
reg a,b,cin;
wire sum,cout;
fulladder_df fa1(a,b,cin,sum,cout);
initial
begin
a=0;
b=0;
cin=0;

#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=0;
 #10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule

Full Subtractor

Gate level :

module fullsubtractor_str(a, b, bin,

diff, bout);
input a, b, bin;
output diff, bout;
wire a_xor_b, a_and_b;

xor(a_xor_b, a, b);
xor(diff, a_xor_b, bin);
and(a_and_b, a, b);
or(bout, a_and_b, bin);
endmodule
Data flow :

module fullsubtractor_df(a, b, bin,

diff, bout);
input a, b, bin;
output diff, bout;

assign diff = a ^ b ^ bin;

assign bout = (~a&b)|(bin &(~a^b));
endmodule

Behavioral model :

module full_subtractor_beh(A, B, Bin, Diff,

Bout);
input wire A, B, Bin;
output reg Diff, Bout;

always @(A or B or Bin) begin

case ({A, B, Bin})
3'b000: begin Diff = 0; Bout = 1; end
 3'b001: begin Diff = 1; Bout = 1; end
3'b010: begin Diff = 0; Bout = 1; end
3'b011: begin Diff = 1; Bout = 0; end
3'b100: begin Diff = 1; Bout = 1; end
3'b101: begin Diff = 0; Bout = 0; end
3'b110: begin Diff = 1; Bout = 0; end
3'b111: begin Diff = 0; Bout = 0; end
endcase
end
endmodule

Test Bench :

module fullsubtractor_test;
reg a, b, bin;
wire diff, bout;
fullsubtractor_df fs1(a, b, bin,
diff, bout);

initial begin
a = 0;
b = 0;
bin = 0;
 #10 a = 0; b = 0; bin = 1;
#10 a = 0; b = 1; bin = 0;
#10 a = 0; b = 1; bin = 1;
#10 a = 1; b = 0; bin = 0;
#10 a = 1; b = 0; bin = 1;
#10 a = 1; b = 1; bin = 0;
#10 a = 1; b = 1; bin = 1;
#50 $stop;
end
endmodule
b. 2:1 MUX

Gate level :

module m21_str(D0, D1, S,Y);

output Y;
input D0, D1, S;
wire T1, T2, Sbar;
and A1(T1, D1, S);
and A2(T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);
endmodule

Data flow :

module m21_df(D0, D1, S, Y);

output Y; input D0, D1, S;
assign Y=(S)?D1:D0;
endmodule
Behavioral Modeling :

module m21_beh_case(D0,D1,S,Y);
input wire D0,D1,S;
output reg Y;
always @ (D0 or D1 or S)
begin
case (S) 1'b0 : y <= D0; 1'b1 : y <= D1;
endcase end endmodule

Test bench :
module mux21_test;
reg D0,D1, S; wire Y;
m21_df M1(D0,D1,S,Y);
initial
begin
D0=0; D1=0; S=0;
#10 D0=0;D1=0;S=1;
#10 D0=0; D1=1; S=0;
#10 D0=0; D1=1; S=1;
#10 D0=1; D1=0; S=0;
#10 D0=1; D1=0; S=1;
#10 D0=1; D1=1; S=0;
#10 D0=1; D1=1; S=1;
#50 $stop;
end
endmodule
 4:1 MUX

Gate level :

module m41_str(y, a, b, c, d, s0, s1);

output y; input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);
and A1(T1, a, s0bar, s1bar);
and A2(T2, b, s0bar, s1);
and A3(T3, c, s0, s1bar);
and A4(T4, d, s0, s1);
or(y, T1, T2, T3, T4);
endmodule

Data flow :

module m41_df(ab,c,d,s0,s1,y) ; input

a,b,c,d,s0,s1; output y; assign out =
s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule
Behavioral Modeling :

module m41_beh_case(a, b, c, d, s0, s1, y);

input wire a, b, c, d;
input wire s0, s1;
output reg y;
always @ (a or b or c or d or s0, s1)
begin
case (s0 | s1)
2'b00 : y <= a;
2'b01 : y <= b;
2'b10 : y <= c;
2'b11 : y <= d;
endcase
end
endmodule

TEST BENCH :

module m41_beh_case_tb;
reg a, b, c, d;
reg s0, s1;
wire y;

m41_beh_case dut
(.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1),.y(y));
 initial begin
a = 0;
b = 1;
c = 0;
d = 1;
s0 = 0;
s1 = 0;

#10 s0 = 0; s1 = 0;
#10 s0 = 0; s1 = 1;
#10 s0 = 1; s1 = 0;
#10 s0 = 1; s1 = 1;

#10 $finish;
end

always @(y)
$display("y = %b", y);

endmodule
c. 1:4 DEMUX

Gate level :

module demux_1_to_4_gate(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);
wire s1n, s0n;

not(s1n, s1);
not(s0n, s0);

and(y0, d, s0n, s1n);

and(y1, d, s0, s1n);
and(y2, d, s0n, s1);
and(y3, d, s0, s1);
endmodule
Data flow :

module demux_1_to_4_dataflow(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);

assign y0 = (!s0 & !s1) ? d : 1'b0;

assign y1 = (s0 & !s1) ? d : 1'b0;
assign y2 = (!s0 & s1) ? d : 1'b0;
assign y3 = (s0 & s1) ? d : 1'b0;
endmodule
Behavioral Modeling :

module demux_1_to_4_behavioral(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);

always @ (d or s0 or s1) begin

case({s1, s0})
2'b00: begin
y0 = d;
y1 = 1'b0;
y2 = 1'b0;
y3 = 1'b0;
end
2'b01: begin
y0 = 1'b0;
y1 = d;
y2 = 1'b0;
 y3 = 1'b0;
end
2'b10: begin
y0 = 1'b0;
y1 = 1'b0;
y2 = d;
y3 = 1'b0;
end
2'b11: begin
y0 = 1'b0;
y1 = 1'b0;
y2 = 1'b0;
y3 = d;
end
default: begin
y0 = 1'b0;
y1 = 1'b0;
y2 = 1'b0;
y3 = 1'b0;
end
endcase
end
endmodule
TEST BENCH :

module demux_1_to_4_tb;
reg d;
reg s0;
reg s1;
wire y0;
wire y1;
wire y2;
wire y3;

demux_1_to_4_behavioral demux_inst(
.d(d),
.s0(s0),
.s1(s1),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3)
);

initial begin
d = 1'b1;
s0 = 1'b0;
 s1 = 1'b0;
#10;

s0 = 1'b1;
#10;

s1 = 1'b1;
#10;

d = 1'b0;
#10;

$finish;
end

always @(y0 or y1 or y2 or y3)

$display("y0=%b, y1=%b, y2=%b, y3=%b",
y0, y1, y2, y3);

endmodule
d. 3:8 Decoder

Gate level :

module decoder_3x8(a, b, c, d);

input a, b, c;
output [7:0] d;
wire na, nb, nc;

not n1(na, a);

not n2(nb, b);
not n3(nc, c);

and a1(d[0], na, nb, nc);

and a2(d[1], a, nb, nc);
and a3(d[2], na, b, nc);
and a4(d[3], a, b, nc);
and a5(d[4], na, nb, c);
and a6(d[5], a, nb, c);
and a7(d[6], na, b, c);
and a8(d[7], a, b, c);
endmodule
Data flow :

module decoder_3x8(a, b, c, d);

input a, b, c;
output [7:0] d;

assign d[0] = ~a & ~b & ~c;

assign d[1] = a & ~b & ~c;
assign d[2] = ~a & b & ~c;
assign d[3] = a & b & ~c;
assign d[4] = ~a & ~b & c;
assign d[5] = a & ~b & c;
assign d[6] = ~a & b & c;
assign d[7] = a & b & c;
endmodule
Behavioral Modeling :

module decoder_3x8(a, b, c, d);

input a, b, c;
output [7:0] d;

reg [7:0] d;

always @ (a or b or c)
begin
case({a, b, c})
3'b000: d = 8'b00000001;
3'b001: d = 8'b00000010;
3'b010: d = 8'b00000100;
3'b011: d = 8'b00001000;
3'b100: d = 8'b00010000;
3'b101: d = 8'b00100000;
3'b110: d = 8'b01000000;
3'b111: d = 8'b10000000;
default: d = 8'b00000000;
endcase
end
endmodule
TEST BENCH :

module decoder_3x8_tb;
reg a, b, c;
wire [7:0] d;
decoder_3x8 d8(a, b, c, d);

initial begin
// Initialize Inputs
#20 a = 0; b = 0; c = 0;
#20 a = 0; b = 0; c = 1;
#20 a = 0; b = 1; c = 0;
#20 a = 0; b = 1; c = 1;
#20 a = 1; b = 0; c = 0;
#20 a = 1; b = 0; c = 1;
#20 a = 1; b = 1; c = 0;
#20 a = 1; b = 1; c = 1;
#50 $stop;
end
endmodule
 LAB Task –3

Name: Omkar Jawalikar

Reg No: 22BCE2223

Course Code: BECE102P

Course Name: Digital Systems Design Lab

Faculty Name: Dr. Abhishek N. Tripathi

Q.1 Write Verilog code along with the Test bench of the following Data-path circuits:

a. 4-bit binary adder and subtractor

CODE:

module bitaddersub(A,B,mode,S,Cout);
input [3:0]A,B;
input mode;
output [3:0]S;
output Cout;
wire c0,c1,c2,b0,b1,b2,b3;
xorgate X1(mode,B[0],b0);
xorgate X2(mode,B[1],b1);
xorgate X3(mode,B[2],b2);
xorgate X4(mode,B[3],b3);
fulladder X5(A[0],b0,mode,S[0],c0);
fulladder X6(A[1],b1,c0,S[1],c1);
fulladder X7(A[2],b2,c1,S[2],c2);
fulladder X8(A[3],b3,c2,S[3],Cout);
endmodule

//testbench

module Fourbit_test();
reg [3:0]A,B;
reg mode;
wire [3:0]S;
wire Cout;

bitaddersub F3(A,B,mode,S,Cout);
initial
begin
#100 A=4'b1000;B=4'b0010;mode=1;
#100 A=4'b1101;B=4'b1001;mode=1;
#100 A=4'b1000;B=4'b0110;mode=0;
#100 A=4'b0001;B=4'b1110;mode=0;
#100 A=4'b1001;B=4'b1111;mode=1;
#100 A=4'b1011;B=4'b1101;mode=0;
#100 A=4'b0101;B=4'b1010;mode=1;
end
endmodule
OUTPUT:

b. Carry look ahead adder:

CODE:

module CarryLookAheadAdder(A, B, Cin, S,Cout);

input [3:0] A,B;
input Cin;
output [3:0] S;
output Cout;
wire [3:0] Ci; // Carry intermediate for intermediate computation
assign Ci[0] = Cin;
assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) & Ci[0]);
//assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & Ci[1]); expands to
assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])));
//assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & Ci[2]); expands to
assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) |
((A[0]^B[0]) & Ci[0])))));
//assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & Ci[3]); expands to
assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & ((A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) |
((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))))));
assign S = A^B^Ci;
endmodule
//testbench
module TB;
reg [3:0]A, B;
reg Cin;
wire [3:0] S;
wire Cout;
wire[4:0] add;
CarryLookAheadAdder cla(A, B, Cin, S, Cout);
assign add = {Cout, S};
initial begin
A = 1; B = 0; Cin = 0; #3;
A = 2; B = 4; Cin = 1; #3;
A = 4'hb; B = 4'h6; Cin = 0; #3;
A = 5; B = 3; Cin = 1;
end
endmodule

OUTPUT:
c. Multiplier

CODE:
module multiplier_4_x_4(product,inp1,inp2);

output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;

assign product[0]=(inp1[0]&inp2[0]);

wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;

HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);

HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);

HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);

endmodule

module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule
//testbench
module MULARR_tb();
reg [3:0]inp1;
reg [3:0]inp2;
wire [7:0]product;

multiplier_4_x_4 uut(.inp1(inp1),.inp2(inp2),.product(product));
initial
begin
inp1=10;
inp2=12;
#30 ;
inp1=13;
inp2=12;
#30 ;

inp1=10;
inp2=22;
#30 ;

inp1=11;
inp2=22;
#30 ;

inp1=12;
inp2=15;
#30 ;
end
endmodule

OUTPUT:
d. Comparator
1 BIT

CODE:
module comp_1bit(a,b,eq,lt,gt);
input a,b;
output eq,lt,gt;
assign eq=~(a^b);
assign lt= ~a&b;
assign gt=a& ~b;
endmodule
//testbench

module comp1bit_test();
reg atb,btb;
wire eqtb,lttb,gttb;
comp_1bit J1(atb,btb,eqtb,lttb,gttb);
initial
begin
#100 atb=0;btb=0;
#100 atb=0;btb=1;
#100 atb=1;btb=0;
#100 atb=1;btb=1;
end
endmodule

OUTPUT:
4 BIT:
CODE:
module comp_4bit(A,B,AeqB,AgtB,AltB);
input[3:0]A,B;
output AeqB,AgtB,AltB;
reg AeqB,AgtB,AltB;

always@(A or B)
begin
AeqB=0;AgtB=0;AltB=0;
if (A==B)
AeqB=1;
else if(A>B)
AgtB=1;
else
AltB=1;
end
endmodule
//testbench
module comp4bit_test();
reg [3:0]a,b;
wire aeqb,agtb,altb;
comp_4bit J2(a,b,aeqb,agtb,altb);
initial
begin
#100 a=3'b000;b=3'b000;
#100 a=3'b110;b=3'b000;
#100 a=3'b100;b=3'b101;
#100 a=3'b001;b=3'b100;
#100 a=3'b010;b=3'b011;
end
endmodule

OUTPUT:
6 BIT:
CODE:
module compare_6bit(A,B,AeqB,AgtB,AltB);
input [5:0]A,B;
output AeqB,AgtB,AltB;
reg AeqB,AgtB,AltB;
always @(A or B)
begin
AeqB=0;AgtB=0;AltB=0;
if (A==B)
AeqB=1;
else if(A>B)
AgtB=1;
else
AltB=1;
end
endmodule
//testbench
module comp6bit_test();
reg [5:0]a,b;
wire aeqb,agtb,altb;
compare_6bit J3(a,b,aeqb,agtb,altb);
initial
begin
#100 a=6'b001001;b=6'b000000;
#100 a=6'b110011;b=6'b111000;
#100 a=6'b100111;b=6'b100111;
#100 a=6'b010101;b=6'b101000;
#100 a=6'b010000;b=6'b101010;
end
endmodule

OUTPUT:
 LAB Task – 4

Name: Omkar Jawalikar

Reg No: 22BCE2223

Course Code: BECE102P

Course Name: Digital Systems Design Lab

Faculty Name: Dr. Abhishek N. Tripathi

Q.1 Write Verilog code along with the Test bench of the following sequential circuits:

a. Flip Flops: SR, JK, D, T

1 .SR Flipflop

Code :

module SR_FF(S, R, Clk, rst, Q, Qbar);

input S, R, Clk, rst;
output Q, Qbar;
reg Q, Qbar;
always @(posedge Clk) begin
if (rst) begin
Q <= 1'b0;
Qbar <= 1'b1;
end
else begin
case ({S, R})
2'b00: begin
Q <= Q;
Qbar <= Qbar;
end
2'b01: begin
Q <= 1'b0;
Qbar <= 1'b1;
end
2'b10: begin
Q <= 1'b1;
Qbar <= 1'b0;
end
2'b11: begin
Q <= 1'bX;
Qbar <= 1'bX;
end
endcase
end
end
endmodule
module SR_ff_tb();
reg clk,reset,s,r;
wire q,qb;

//testbench
SR_FF SR1(s, r, clk, reset, q, qb);

initial clk=1'b0;
 always #25 clk=~clk;
initial
begin
s = 1'b0;
r = 1'b0;
reset = 1;
#100 reset=0; s=1'b1; r=1'b0;
#100 reset=0; s=1'b0; r=1'b1;
#100 reset=0; s=1'b1; r=1'b1;
#100 reset=0; s=1'b0; r=1'b0;
#100 reset=0; s=1'b1; r=1'b0;
#100 reset=0; s=1'b0; r=1'b1;
#100 reset=0; s=1'b0; r=1'b0;
end
endmodule

OUTPUT :
2 .JK Flipflop

CODE :

module jk_flipflop(j,k,clk,reset,Q,Q_bar);
input j,k,clk,reset;
output reg Q,Q_bar;

always@(posedge clk)
begin
if({reset})
{Q,Q_bar}<={1'b0,1'b1};
else
begin
case({j,k})
2'b00:{Q,Q_bar}<={Q,Q_bar};
2'b01:{Q,Q_bar}<={1'b0,1'b1};
2'b10:{Q,Q_bar}<={1'b1,1'b0};
2'b11:{Q,Q_bar}<={~Q,Q};
endcase
end
end
endmodule

//testbench

module jk_ff_test_bench();
reg clk,rst,j,k;
wire q_n,q_n_bar;

jk_flipflop test_design(j,k,clk,rst,q_n,q_n_bar);

initial clk=0;
always #10 clk=~clk;
initial
begin
k=1'b0;j=1'b0;
rst=1;
#100 rst=0;
#100 j = 1'b0; k = 1'b0;
#100 j = 1'b0;k = 1'b1;
#100 j = 1'b1;k = 1'b0;
#100 j = 1'b1;k = 1'b1;
end
endmodule
OUTPUT :
3 .D Flipflop

CODE :
module d_ff(clk,d,q);
input clk,d;
output reg q;

always @ (posedge clk)

begin
q <= d;
end
endmodule

//testbench
module dff_test();
reg D, clk;
wire Q;
d_ff dut(.q(Q), .d(D), .clk(clk));
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
D <= 0;
#100; D <= 1;
#100; D <= 0;
#100; D <= 1;
end
endmodule

OUTPUT:
4 .T Filpflop

CODE:

module T_flipflop (clk,rst_n,t,q,qbar);

input clk, rst_n,t;
output reg q;
output qbar;
always@(posedge clk) begin
if(rst_n)
q<=1'b0;
else begin
q <= (t?~q:q);
end
end
assign qbar = ~q;
endmodule

module T_ff_tb();
reg clk,t,reset;
wire q,qb;
//testbench
T_flipflop TF1( .clk(clk), .rst_n(reset), .t(t), .q(q), .qbar(qb) );
initial
begin
clk=1'b0;
end
always #25 clk = ~clk;
initial
begin
reset=1'b1;
t=1'b1;
#100 reset=1; t=1'b0;
#100 reset=0; t=1'b1;
#100 reset=0;t=1'b1;
#100 reset=0;t=1'b0;
#100 reset=0;t=1'b1;
end
endmodule
OUTPUT:
b. Shift Registers: SISO, SIPO, PISO, PIPO

[Link]

CODE:

module siso(clk,clr,si,so);
input clk,clr,si;
output so;
reg so;
reg [3:0]temp;

always @(posedge clk)

begin
if(clr)
temp <= 4'b0000;
else
temp<=temp<<1;
temp[0]<=si;
so=temp[3];
end
endmodule
//testbench
module siso_tb();
reg clk,si,clear;
wire so;
siso s1 (.clk(clk), .clr(clear),.si(si),.so(so));
initial clk = 0;
always #5 clk=~clk;
initial begin
clear = 0;
si = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'bx;
end
endmodule
OUTPUT:
[Link]

CODE:

module sipo(clk,clr,si,po);
input clk,clr,si;
output po;
reg [3:0]temp,po;
always @(posedge clk)
begin
if(clr)
temp<=4'b0000;
else
temp <= temp<<1;
temp[0]<=si;
po=temp;
end
endmodule
//testbench
module sipo_tb();
reg clk,clr,si;
wire [3:0]po;
sipo SIPO1 (.clk(clk), .clr(clr), .si(si), .po(po));
always begin
#5 clk = ~clk;
end
initial begin
clk = 0;
clr = 0;
si = 0;
clr = 1;
#10 clr = 0;
si = 1;
#10 si = 0;
#10 si = 1;
#10 si = 0;
#10 si = 1;
clr = 1;
#10 clr = 0;
si = 1;
#10 si = 0;
#10 si = 1;
#10 si = 0;
#10 si = 1;
end
endmodule
OUTPUT:
[Link]

CODE:
module piso(so,in,load,clk,rst); output so;
input load,clk,rst;
input [3:0]in;
reg [3:0]q;
always @ (posedge clk or posedge rst) begin
if(rst)
q<=4'b0;
else if(load)
q<=in;
else
q<={1'b0,q[3:1]};
end
assign so=q[0];
endmodule

// testbench
module piso_test; wire so;
reg load,clk,rst; reg [3:0]in;
piso p1(so,in,load,clk,rst); always
#5 clk=~clk;
initial
begin load=1;clk=0;rst=1; in=4'b1001;
#10 rst=0;
#10 load=0;
#40 load=1;in=4'b0011; #10 load=0;
#50 $stop;
end
endmodule
OUTPUT:
[Link]

CODE:

module pipo(clk,clr,pi,po);
input clk,clr,pi;
output [3:0]po;
wire [3:0]pi;
reg [3:0]po;
always @(posedge clk)
begin
if(clr)
po<=4'b0000;
else
po<=pi;
end
endmodule
//testbench
module pipo_tb();
reg clk,clear;
reg [3:0] pi;
wire [3:0] po;
pipo P1(clk,clear,pi,po);
initial clk=1'b0;
always #5 clk=~clk;
initial
begin
clear = 0;
pi = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 pi=4'b1001;
#10 pi=4'b1010;
#10 pi=4'b1011;
#10 pi=4'b1110;
#10 pi=4'b1111;
#10 pi=4'b0000;
end
endmodule
OUTPUT :
 LAB Task – 5

Name: Omkar Jawalikar

Reg No: 22BCE2223

Course Code: BECE102P

Course Name: Digital Systems Design Lab

Faculty Name: Dr. Abhishek N. Tripathi

Q.1 Write Verilog code along with the Test bench of the following circuits:

a. Counters: Synchronous Up-down

CODE:
module upordown_counter(Clk,reset,UpOrDown,Count);
input Clk,reset,UpOrDown;
output [3 : 0] Count;
reg [3 : 0] Count = 0;
always @(posedge(Clk) or posedge(reset)) begin
if(reset == 1)
Count <= 0; else
if(UpOrDown == 1)
if(Count == 15)
Count <= 0; else
Count <= Count + 1; else
if(Count == 0)
Count <= 15; else
Count <= Count - 1; end
endmodule
//Testbench
moduletb_counter;
reg Clk;
reg reset;
reg UpOrDown;
wire [3:0] Count;
upordown_counter uut (.Clk(Clk), .reset(reset),
.UpOrDown(UpOrDown),.Count(Count));
initial Clk = 0;
always #5 Clk = ~Clk;
initial begin
reset = 0;
UpOrDown = 0;
#300;
UpOrDown = 1;
#300;
reset = 1;
UpOrDown = 0;
#100;
reset = 0;
end
endmodule
OUTPUT:
b. A sequence detector which produces output 1 after three consecutive 1’s
(overlapping allowed) using Mealy and Moore FSM

Mealy Overlap 111:

CODE:

module seq_mealy(y,i,clk,rst); output y;

input i,clk,rst; reg y;
reg [1:0] cs,ns;

parameter s0=2'b00;
parameter s1=2'b01;
parameter s2=2'b10;
parameter s3=2'b11;

always @(cs or i)
begin
y=1'b0;
case(cs) s0:begin if(i)
ns =s1; else
ns =s0; end s1:begin if(i)
ns =s1; else
ns =s2; end s2:begin if(i)
ns =s3; else
ns =s0;end s3:begin if(i)
ns =s1; else begin ns =s2;
y =1'b1;
end end endcase end

always @(posedge clk or posedge rst) begin

if(rst) cs <=s0; else cs<=ns;
end
endmodule

//TESTBENCH

module seq_mealy_test(); wire y;

reg i,clk,rst;
seq_mealy f1(y,i,clk,rst); always
#5 clk =~clk; initial
begin i=1;clk=0;rst=1; #10 rst=0;
#10 i=0;
#10 i=1;#10 i=0;
#10 i=1;
#10 i=0;
#50 $stop; end endmodule
OUTPUT :
2. Moore Overlap 111:

CODE:

module Seq_detect_111(clk,rst,inp,out);
input clk,rst,inp;
output reg out;
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
reg [1:0] state, nxt_state;
always@(posedge clk) begin
if(rst == 1)
state <= A;
else
state <= nxt_state;
end
always@(state , inp) begin
case(state)
A : begin
if(inp == 1'b1)
nxt_state <= B;
else
nxt_state <= A;
end
B : begin
if(inp == 1'b1)
nxt_state <= C;
else
nxt_state <= A;
end
C : begin
if(inp == 1'b1)
nxt_state <= D;
else
nxt_state <= A;
end
D : begin
if(inp == 1'b1)
nxt_state <= B;
else
nxt_state <= A;
end
default : nxt_state <= A;
endcase
end
always@(state) begin
case(state)
A : out <= 0;
B : out <= 0;
C : out <= 0;
D : out <= 1;
 default : out <= 0;
endcase
end
endmodule

//TESTBENCH

module SeqDet111_TB();
reg clk, rst_n, x;
wire z;

Seq_detect_111 SD1(clk, rst_n, x, z);

initial clk = 0;
always #2 clk = ~clk;

initial begin
x = 0;
#1 rst_n = 1;
#2 rst_n = 0;
#3 x = 0;
#4 x = 1;
#4 x = 1;
#4 x = 0;
#4 x = 0;
#4 x = 1;
#4 x = 1;
#4 x = 1;
#4 x = 1;
#4 x = 1;
#4 x = 1;
end
endmodule
OUTPUT :