INPUT OUTPUT
ORGANIZATION
VIJAY PRAKASH SHARMA
PERIPHERAL DEVICES
• The input-output subsystem of a computer, referred to as I/O.
• Provides an efficient mode of communication between the central system and the outside environment.
• Devices that are under the direct control of the computer are said to be connected on-line.
• Input or output device attached to the computer are also called peripherals.
• Input
• Output
• Input-output
Peripherals are electromechanical and electromagnetic device.
Video monitor, printer, magnetic tape, magnetic disk
ASYNCHRONOUS DATA TRANSFER
• Internal timing of CPU and I/O device is independent from the other in that each uses its own clock for internal
register.
• This Scheme is used when speed of I/O devices do not match with microprocessor, and timing characteristics of I/O
devices is not predictable. In this method, process initiates the device and check its status. As a result, CPU has to wait
till I/O device is ready to transfer data. When device is ready CPU issues instruction for I/O transfer. In this method
two types of techniques are used based on signals before data transfer.
• Two independent unit require control signals be transmitted between the communication unit to indicating the time at
which data is being transmitted.
• Strobe plus supplied by one of the unit to indicate to the other unit when transfer has to occure
• Handshaking : each data item being transferred with a control signal that indicate the presence of data in the bus
STROBE CONTROL
• Activated by either source or
destination.
• Strobe is a single line that informs
the destination unit when a valid
data word is available in the bus
• Source unit first places the data on the data bus. After the brief delay to ensure that the
data settle to a steady value, the source activated the strobe pulse. The information on
the data bus and the strobe signal remain in the active state for a sufficient time period
to allow the destination unit to receive unit.
• Destination activates the strobe pulse,
informing the source to provide the data.
• Source unit responds by placing the requested
binary information on the data bus.
DISADVANTAGE OF STROBE SIGNAL
• The disadvantage of the strobe method is that, the source unit initiates the transfer has no way of
knowing whether the destination unit has actually received the data item that was places in the
bus.
• Similarly, a destination unit that initiates the transfer has no way of knowing whether the source
unit has actually placed the data on bus. The Handshaking method solves this problem.
HANDSHAKING
• introducing a second control signal that provides a reply to the unit that initiates the transfer.
• One control line is in the same direction as the data flows in the bus from the source to destination. It is used by source
unit to inform the destination unit whether there a valid data in the bus. The other control line is in the other direction
from the destination to the source. It is used by the destination unit to inform the source whether it can accept the data.
The sequence of control during the transfer depends on the unit that initiates the transfer.
SOURCE INITIATED
DESTINATION INITIATED
ADVANTAGE OF THE HANDSHAKING METHOD
• The Handshaking scheme provides degree of flexibility and reliability because the successful
completion of data transfer relies on active participation by both units.
• If any of one unit is faulty, the data transfer will not be completed. Such an error can be detected
by means of a Timeout mechanism which provides an alarm if the data is not completed within
time.
MODE OF TRANSFER
• The data transfer can be handled by various modes. some of the modes use CPU as an
intermediate path, others transfer the data directly to and from the memory unit. Data transfer to
and from peripherals may be handled in one of the three possible modes:
• i. Programmed I/O
• ii. Interrupt-Initiated I/O
• iii. Direct Memory Access (DMA)
DIRECT MEMORY ACCESS (DMA)
• The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the
speed of the CPU. Removing the CPU from the path and letting the peripheral device manage the memory
buses directly would improve the speed of transfer. This transfer technique is called Direct Memory Access
(DMA).
• During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA Controller takes
over the buses to manage the transfer directly between the I/O device and memory.
• The CPU may be placed in an idle state in a variety of ways. One common method extensively used in
microprocessor is to disable the buses through special control signals such as:
• Bus Request (BR)
• Bus Grant (BG)
The Bus Request (BR) input is used by the DMA controller to request
the CPU. When this input is active, the CPU terminates the
execution of the current instruction and places the address bus,
data bus and read write lines into a high Impedance state. High
Impedance state means that the output is disconnected.
The CPU activates the Bus Grant (BG) output to inform the external
DMA that the Bus Request (BR) can now take control of the buses to
conduct memory transfer without processor.
When the DMA terminates the transfer, it disables the Bus Request
(BR) line. The CPU disables the Bus Grant (BG), takes control of the
buses and return to its normal operation.
• The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
i) DMA Burst :- In DMA Burst transfer, a block sequence consisting of a number of memory words is
transferred in continuous burst while the DMA controller is master of the memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA controller to transfer one data word at a time, after
which it must returns control of the buses to the CPU.
DMA CONTROLLER
i. Address Register :- Address Register contains an address to
specify the desired location in memory. After each word transfer
DMA increment its address register.
ii. Word Count Register :- WC holds the number of words to be
transferred. The register is decrement by one after each word
transfer and internally tested for zero.
iii. Control Register :- Control Register specifies the mode of
transfer
All register in the DMA appear to the CPU as I/O interface
registers. Thus the CPU can read from or write into the DMA
registers under program control via the data bus.
• The DMA communicates with the CPU via the data bus and control lines. The registers in the DMA are selected by the
CPU through the address bus by enabling the DS (DMA select) and RS (Register select) inputs.
• The RD (read) and WR (write) inputs are bidirectional.
• When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers through the data bus to read
from or write to the DMA registers.
• When BG =1, the DMA can communicate directly with the memory by specifying an address in the address bus and
activating the RD or WR control.
DMA TRANSFER
• Peripheral device sends a DMA request,
• DMA controller activates the BR line .(informing CPU to relinquish the buses)
• CPU responds with its BG line (informing DMA that its buses are disable)
• DMA puts its current value of its address register into the address bus, initiates the RD
and WR signal, and send DMA acknowledge to the peripheral device.