Analysis & Design of Digital Circuits

with HDL
Dr. Roopa J
Unit 3
 Unit 1 & 2

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 Unit 3-4-5

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 Sequential Circuits

◆ Combinational
⮚ The outputs depend only on the current input values
⮚ It uses only logic gates
◆ Sequential
⮚ The outputs depend on the current and past input values
⮚ It uses logic gates and storage elements
⮚ Example
✔ Vending machine
⮚ They are referred as finite state machines since they have a finite
number of states

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 Memory Elements

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 Memory Elements

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 Memory Elements

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A simple memory element with NOT Gates A simple memory element with NAND Gates

A simple memory element with NOR Gates

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 Basic Latch

A simple memory element with NOR Gates A simple memory element with NOR Gates

Set Reset

Reset

Set Q

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 Two Different Ways to Draw the Same Circuit

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 Timing Diagram for the Basic Latch with NOR
Gates
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Truth table

t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
(c) Timing diagram [ Figure 5.4 from the textbook ]

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 Circuit and Truth Table for the Basic Latch

NOR Gate Truth table

NOR Gate
x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 0

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 Syn / ASYN reset

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 Introduction: Latches and Flipflops

● The SR latch is a circuit with two cross-coupled NOR gates or two cross coupled NAND gates, and two inputs labeled S for set,
and R for reset.
● The latch has two useful states. When output Q=1 and Q′=0, the latch is said to be in the set state. When Q=0 and Q′=1, it is in
the reset state. Outputs Q and Q′ are normally the complement of each other.
● However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 (rather than be
mutually complementary) occurs.
● If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state.

Setting both inputs to 1 is forbidden.

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 SR Latch using NAND Gates

● The SR latch with two cross-coupled NAND gates. It operates with both inputs normally at 1,
unless the state of the latch has to be changed.
● The application of 0 to the S input causes output Q to go to 1, putting the latch in the set state.
When the S input goes back to 1, the circuit remains in the set state.
● After both inputs go back to 1, we are allowed to change the state of the latch by placing a 0 in
the R input. This action causes the circuit to go to the reset state and stay there even after both
inputs return to 1.
● The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the same
time, an input combination that should be avoided.

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 Controlled SR Latch using NAND Gates

● It consists of the basic SR latch and two additional NAND gates.

● The input En acts as an enable signal for the other two inputs. The outputs of the two additional
NAND gates stay at the logic-1 level as long as the enable signal remains at 0 (Quiescent condition).
● To change to the reset state, the inputs must be S=0, R=1, and En=1. In either case, when En
returns to 0, the circuit remains in its current state. The control input disables the circuit by applying
0 to En, so that the state of the output does not change regardless of the values of S and R
● An indeterminate condition occurs when all three inputs are equal to 1.

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 D-Latch(Transparent Latch)

● Undesirable Condition: Ensure that inputs S and R are never equal to 1 at the same time
● D- latch has only two inputs: D (data) and En (enable).
● As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level and the
circuit cannot change state regardless of the value of D.
● The D input is sampled when En=1. If D=1, the Q output goes to 1, placing the circuit in the set
state. If D=0, output Q goes to 0, placing the circuit in the reset state.
● The output follows changes in
the data input as long as the
enable input is asserted.
- Transparent latch.

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 Symbolic Representation.

● The graphic symbols for the various latches are shown in Fig. 5.7. A latch is designated by a
rectangular block with inputs on the left and outputs on the right

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 Types of Clock

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 Verilog code for SR Latch
Test-Bench

Behavioral

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SR FF Vs JK FF

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 SR FF Vs JK FF

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 Synchronous clocked sequential circuit

● The transition from one state to the next occurs only at predetermined intervals dictated by the clock
pulses.
● The value that is stored in a flip-flop when the clock pulse occurs is also determined by the inputs to
the circuit or the values presently stored in the flip-flop (or both).
● The new value is stored (i.e., the flip-flop is updated) when a pulse of the clock signal occurs.
● Prior to the occurrence of the clock pulse, the combinational logic forming the next value of the flip-
flop must have reached a stable value.

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 Controlled SR Latch using NAND Gates

● Storage elements that operate ● those controlled by a clock

with signal levels (rather than transition are flip-flops.
signal transitions) are referred to ● flip-flops are edge-sensitive
as latches; devices.
● Latches are said to be level-
sensitive devices;
The two types of storage elements are related because latches are the basic circuits from which all flip-flops are constructed.

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 D FF Without Set and Reset input control
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 D FF With Set and Reset input control
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JK Flip Flop
Race Around Condition
 Edge-Triggered D Flip-Flop using D Latch

● It consists of the basic SR latch and two additional NAND gates.

● Master–Slave flip-flop: The first latch is called the master and the second the slave.
● The circuit samples the D input and changes its output Q only at the negative edge of the
synchronizing or controlling clock (designated as Clk).

● The output may change only once, change in the output is triggered by the negative edge of the
clock and the change may occur only during the clock’s negative level
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 Edge-triggered D flip-flop using
3-SR latches
Two latches respond to the external D (data)
and Clk (clock) inputs.
The third latch provides the outputs for the
flip-flop.

When Clk is 0, no response and both S and R output latch

remains at 1 state. If D=0 when Clk goes 1 (During transistion), R changes to 0. This
But during Clock 1 hold state no change is causes the flip-flop to go to the reset state, making Q=0.
forwarded till next transition of Clk from 0-1 Similarly, do it for D=1, making Q=1
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happens.
● Set up time: which the D input must be maintained at a constant value prior to the occurrence
of the lock transition.
● Hold Time: which the D input must not change after the application of the positive transition of
the clock.
● Propagation delay: interval between the trigger edge and the stabilization of the output to a new
state.
● Some flip-flops have asynchronous inputs that are used to force the flipflop to a particular state
independently of the clock. The input that sets the flip-flop to 1 is called preset or direct set. The input
that clears the flipflop to 0 is called clear or direct reset.
● When power is turned on in a digital system, the state of the flip-flops is unknown. The direct inputs
are useful for bringing all flip-flops in the system to a known starting state prior to the clocked
operation.
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 Other FF using D-FF: JK using D FF

When J=1 and K=0, D=Q′+Q=1, so the next clock edge sets the output to 1.
When J=0 and K=1, D=0, so the next clock edge resets the output to 0.
When both J=K=1 and D=Q′ the next clock edge complements the output.
When both J=K=0 and D=Q, the clock edge leaves the output unchanged.
D=JQ′+K′Q

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 T-FF

D=T⊕Q=TQ′+T′Q
When T=0, D=Q and there is no change in the
output.
When T=1, D=Q′ and the output complements.

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 Flip flop Conversion

SR flip-flop to JK flip-flop
 Procedure

● Step 1: Write the characteristic table of the required flip-flop

● Step 2: Write the excitation table of the given flip-flop
● Step 3: Write the conversion table
● Step 4: Find the Boolean expressions for the inputs of the given flip-flop.
● Step 5: Draw the circuit for implementing JK flip-flop using SR flip-flop
 Hence you need to write the truth table of JK flip-flop

SR to JK:
Step 1: Write the characteristic table of the required flip-flop
 Hence you need to write the excitation table of SR Flip-Flop

SR to JK:
Step 2: Write the excitation table of the given flip-flop
 SR to JK:
Step 3: Write the conversion table
The conversion table, which is a combination of truth table and excitation table

Conversion Table
SR to JK:
Step 4: Find the Boolean expressions for the inputs of the given flip-flop.
SR to JK:
Step 5: Draw the circuit for implementing JK flip-flop using SR flip-
flop
Try out these conversion