BAHIR DAR UNIVERSITY

BAHIR DAR INSTITUTE OF TECHNOLOGY

FACULITY OF ELCTRICAL AND COMPUTER ENGINEERING

DEPARTMENT OF COMMUNICATION ENGINEERING

RF Design Assignment 2

Prepared by:

Alefe Simachew

Melkam Gizat

Submitted to: Dr. Fekadu M.

Jan, 2026
 RF Design Assignment 2

Table of Contents
List of Figures..................................................................................................iii

Executive Summary........................................................................................iv

1. Introduction...............................................................................................1

2. Literature Review......................................................................................3

3. System Modeling.......................................................................................5

3.1. Design Specifications.................................................................................5

3.2. Technology Selection.................................................................................5

3.4. Input and Output Matching Network Design.....................................................7

3.5. Biasing Network Design..............................................................................9

4. ADS Simulation Setup..............................................................................14

4.2. Stability Analysis....................................................................................15

5. Simulation Results...................................................................................17

5.1. Gain Analysis.........................................................................................17

5.2. Input and Output Matching Analysis.............................................................19

5.2.1. Input Matching (S11)..........................................................................19

5.2.2. Output Matching (S22)........................................................................21

5.2.3. Noise Figure Analysis............................................................................22

6. Trade-Off Analysis....................................................................................24

6.1. Gain versus Noise Figure Trade-Off.............................................................24

6.2. Gains versus Power Consumption Trade-Off..................................................25

6.3. Noise Figure versus Stability Trade-Off.........................................................25

6.4. Power Consumption versus Stability Trade-Off...............................................26

7. Conclusion...............................................................................................27

8. References...............................................................................................28
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List of Figures
Figure 1:Schematic diagram of cascade LNA design....................................................................11
Figure 2:Gain(S21 in dB)..............................................................................................................18
Figure 3:S12 in dB.........................................................................................................................19
Figure 4:Input return loss(S11 in dB)............................................................................................20
Figure 5:Output return loss(S22 in dB).........................................................................................21
Figure 6:NF in dB..........................................................................................................................23

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Executive Summary

This RF Design presents the design and simulation of a 5G Frequency Range 2 (FR2) cascade
Low-Noise Amplifier (LNA) operating in the 24.25–27.5 GHz band. The motivation for this
work arises from the stringent requirements of 5G millimeter-wave (mmWave) receiver front-
end circuits, where high gain, low noise figure, wide bandwidth, and unconditional stability must
be achieved simultaneously despite severe propagation losses and circuit parasitic at high
frequencies.

Cascade LNA architecture is adopted due to its inherent advantages in suppressing the Miller
effect, improving reverse isolation, enhancing gain, and ensuring stable operation at mmWave
frequencies. The design employs a common-source input transistor optimized for low noise
performance, stacked with a common-gate transistor to improve isolation and stability.
Distributed microstrip-based input and output matching networks are designed to achieve a
compromise between noise matching and power matching while maintaining compatibility with
planar RF implementations. The biasing network is carefully designed using RF chokes, bypass
capacitors, and independent gate biasing to ensure reliable DC operation without degrading RF
performance. The entire design is implemented and simulated using Keysight Advanced Design
System (ADS) 2022, employing small-signal S-parameter analysis and noise figure analysis
across the target FR2 frequency band.

Simulation results demonstrate that the proposed LNA achieves a small-signal gain exceeding 10
dB across the operating band, input and output return losses better than −10 dB, and a noise
figure below 3 dB throughout 24.25–27.5 GHz. Stability analysis confirms unconditional
stability across the band, validating the effectiveness of the cascade topology and the
implemented stabilization techniques.

Keywords: 5G FR2, Millimeter-Wave LNA, Cascade Amplifier, Noise Figure, Impedance

Matching, ADS Simulation.

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1. Introduction

The fifth generation (5G) of mobile communication systems represents a significant evolution
from previous generations by enabling ultra-high data rates, ultra-low latency, and support for
massive device connectivity. To achieve these ambitious targets, 5G introduces the use of
millimeter-wave (mmWave) frequency bands, categorized by the 3GPP as Frequency Range 2
(FR2). These bands typically span from 24.25 GHz to 40 GHz and provide large contiguous
bandwidths suitable for multi-gigabit-per-second wireless [Link], operating at
mmWave frequencies introduces severe propagation challenges such as higher free-space path
loss, increased sensitivity to blockage, and greater circuit losses. As a result, the design of
radio-frequency (RF) front-end circuits becomes significantly more complex than in sub-6 GHz
systems. Among all RF front-end components, the Low-Noise Amplifier (LNA) plays a critical
role, as it is the first active block in the receiver chain and directly determines the overall system
noise performance.

The primary function of an LNA is to amplify extremely weak received signals while
introducing minimal additional noise. According to Friis’ formula, the noise figure of the first
amplifier stage dominates the total noise figure of the receiver. Therefore, careful LNA design is
essential to maintain acceptable receiver sensitivity, especially in 5G FR2 systems where
received signal levels are typically very [Link] addition to low noise figure, an LNA designed for
mmWave applications must satisfy several other stringent requirements, including sufficient
gain, wide bandwidth, good input and output impedance matching, unconditional stability, and
low power consumption. These requirements often conflict with one another, creating complex
design trade-offs. For instance, techniques that improve gain may degrade noise figure or
stability, while measures taken to enhance stability can reduce bandwidth or increase power
consumption.

To address these challenges, various LNA topologies have been proposed, among which the
cascade architecture is particularly attractive for mmWave applications. The cascade
configuration effectively improves reverse isolation, enhances gain, and provides better stability

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compared to a simple common-source amplifier. These advantages make the cascade LNA a
strong candidate for 5G FR2 receiver front-ends.

This project focuses on the design and simulation of a 5G FR2 cascade Low-Noise Amplifier
operating in the 24.25–27.5 GHz band using Keysight Advanced Design System (ADS). The
objective is to demonstrate a systematic RF design methodology, including transistor biasing,
impedance matching, and performance evaluation, rather than to optimize for a specific
semiconductor foundry. The proposed design aims to achieve competitive gain, low noise figure,
and stable operation suitable for modern 5G mmWave receiver applications.

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2. Literature Review

The design of Low-Noise Amplifiers for millimeter-wave applications has been an active
research area in recent years, driven primarily by the deployment of 5G New Radio (NR)
systems in Frequency Range 2 (FR2). Numerous studies have investigated different LNA
topologies, semiconductor technologies, and circuit techniques to meet the stringent
requirements of high gain, low noise figure, wide bandwidth, and stable operation at frequencies
above 24 GHz.

Early mmWave LNA designs predominantly employed common-source (CS) configurations due
to their simplicity and low noise potential. However, at higher frequencies, CS LNAs suffer from
poor reverse isolation and increased susceptibility to instability caused by the Miller effect.
These limitations have motivated researchers to explore alternative architectures that can provide
improved performance at mmWave frequencies.

Among the various architectures reported in the literature, the cascade topology has emerged as
one of the most widely adopted solutions for mmWave LNAs. The cascade configuration
combines a common-source transistor with a common-gate transistor stacked vertically, which
significantly reduces the effective gate-drain capacitance and enhances reverse isolation. As a
result, cascade LNAs typically exhibit higher gain, improved stability, and wider bandwidth
compared to single-transistor designs.

Several authors have demonstrated cascade LNAs operating in the 26–28 GHz band with gains
ranging from 10 dB to 20 dB and noise figures below 3 dB using CMOS, SiGe BiCMOS, and
GaAs technologies. While GaAs pHEMT technologies generally offer superior noise
performance, CMOS-based solutions are often favored for their low cost and ease of integration,
despite their relatively higher noise figure at mmWave frequencies.

In addition to topology selection, impedance matching techniques play a critical role in mmWave
LNA performance. Researchers commonly employ a combination of lumped elements and
distributed transmission lines to achieve simultaneous noise and power matching. Microstrip

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based matching networks are particularly attractive for mmWave designs due to their ease of
implementation and compatibility with planar fabrication processes.

Biasing strategies and stability enhancement techniques are also extensively discussed in the
literature. The use of RF chokes, bypass capacitors, and source degeneration inductors has been
shown to improve stability without significantly degrading noise performance. Based on the
reviewed literature, the cascade LNA architecture with microstrip matching and careful biasing
represents a well-established and effective solution for 5G FR2 receiver front-end applications.
This observation provides strong justification for the architectural choices adopted in this project

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3. System Modeling

3.1. Design Specifications

This chapter presents the system-level modeling approach adopted for the proposed 5G FR2
Low-Noise Amplifier and defines the key design specifications derived from receiver
requirements. System modeling is essential to translate high-level 5G performance targets into
circuit-level parameters that can be implemented and verified using circuit simulation tools such
as [Link] the receiver level, the LNA is positioned immediately after the antenna and band-
select filter. Its primary role is to amplify weak received signals while adding minimal noise,
thereby preserving the signal-to-noise ratio (SNR). According to Friis’ cascade formula, the
noise figure and gain of the first stage dominate the overall receiver performance. Therefore, the
system model emphasizes low noise figure and sufficient gain as primary objectives.

Based on 3GPP FR2 specifications and typical 5G handset receiver requirements, the target
operating frequency range is selected as 24.25–27.5 GHz, corresponding to the n258 band. The
desired small-signal gain is greater than 10 dB to overcome subsequent stage noise, while the
noise figure is targeted below 3 dB. Input and output return losses are specified to be better than
−10 dB to ensure proper impedance matching with a 50-ohm system. Additionally, unconditional
stability across the operating band is required to prevent oscillations.

3.2. Technology Selection

The choice of semiconductor technology significantly influences the achievable performance of

a millimeter-wave LNA. Technologies commonly reported in the literature for 5G FR2 LNAs
include CMOS, SiGe BiCMOS, and III–V compound semiconductors such as GaAs pHEMTs.
Each technology presents distinct advantages and limitations in terms of noise performance,
gain, power consumption, cost, and integration capability.

GaAs pHEMT technology is widely recognized for its superior high-frequency performance and
low noise characteristics, making it particularly attractive for mmWave LNAs. However, access
to foundry-specific pHEMT models is often restricted in academic environments. As a result,

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this project employs a generic RF field-effect transistor (FET) model available in ADS 2022 to
demonstrate the design methodology and performance trends rather than to target fabrication-
ready [Link] selected generic RF FET model supports key parameters such as
transconductance, gate capacitances, and bias-dependent behavior, which are essential for
realistic LNA performance evaluation. By carefully selecting device dimensions and biasing
conditions, the model can approximate the behavior of a practical mmWave transistor.

This approach allows the focus of the project to remain on fundamental RF design principles,
including cascade topology implementation, impedance matching, bias network design, and
stability analysis. Although absolute performance values may vary from fabricated hardware, the
adopted technology selection is well suited for academic validation of a 5G FR2 LNA design
using ADS.

3.3. Cascade LNA Architecture

The cascade Low-Noise Amplifier (LNA) architecture is widely adopted in millimeter-wave

receiver front-ends due to its superior gain, stability, and isolation characteristics compared to
single-transistor configurations. In its basic form, the cascade topology consists of a common-
source (CS) transistor stacked with a common-gate (CG) transistor. This vertical stacking
effectively mitigates the Miller effect associated with the gate–drain capacitance of the input
device, which otherwise limits gain and bandwidth at high frequencies.

In the proposed design, the lower transistor (denoted as M1) operates in a common-source
configuration and is primarily responsible for setting the noise performance of the LNA. The
transconductance of M1 directly influences the achievable gain and noise figure. To further
enhance noise performance and input matching flexibility, a small source degeneration inductor
is introduced at the source of M1. This inductor provides negative feedback that improves input
impedance matching and stability with minimal degradation of noise figure. The upper transistor
(denoted as M11) operates in a common-gate configuration and serves as the cascade device.
The primary role of M11 is to shield the input device from voltage variations at the output node.
By maintaining a relatively constant drain voltage at M1, the cascade transistor significantly
reduces the effective gate–drain capacitance seen at the input, thereby improving reverse

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isolation and extending the usable bandwidth of the amplifier. This mechanism is particularly
critical at 5G FR2 frequencies, where parasitic capacitances strongly influence circuit behavior.

In addition to improving isolation and bandwidth, the cascade architecture enhances amplifier
stability. At millimeter-wave frequencies, unintended feedback paths through parasitic elements
can lead to oscillations. The common-gate transistor M11 suppresses such feedback by providing
high output resistance and isolating the input from load variations. As a result, the overall LNA
exhibits improved unconditional stability across the operating band. The biasing of the cascade
LNA is carefully designed to ensure both transistors operate in the desired saturation region.
Independent bias networks are used for the gate of M1 and the gate of M11, allowing flexibility
in optimizing noise and gain independently. Radio Frequency Chokes (RFCs) are employed in
the drain bias path to supply DC voltage while presenting high impedance to RF signals, thereby
preventing RF leakage into the power supply.

Overall, the cascade LNA architecture offers an effective balance between gain, noise
performance, bandwidth, and stability for 5G FR2 applications. The combination of a noise-
optimized common-source input stage and an isolation-enhancing common-gate cascade stage
forms a robust foundation for millimeter-wave LNA design. This architectural choice provides
the basis for the detailed matching network and biasing designs discussed in subsequent chapters.

3.4. Input and Output Matching Network Design

Impedance matching is a critical aspect of Low-Noise Amplifier design, particularly at

millimeter-wave frequencies where mismatches can severely degrade gain, noise figure, and
bandwidth. The objective of the input and output matching networks is to transform the complex
impedance of the active device to the standard system impedance of 50 ohms while meeting
specific performance targets such as low noise figure and adequate gain. In the proposed 5G FR2
LNA, distributed microstrip elements are employed to realize compact and tunable matching
networks suitable for operation in the 24.25–27.5 GHz band.

At the input of the LNA, the matching network must satisfy two often competing requirements:
noise matching and power matching. Noise matching aims to present optimum source impedance
to the transistor that minimizes the noise figure, whereas power matching seeks to maximize
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power transfer and gain. In practice, a compromise between these two conditions is required. The
input matching network is therefore designed to approach the optimum noise impedance while
maintaining acceptable input return loss. The input matching network consists of a DC blocking
capacitor followed by a combination of microstrip transmission lines and stubs. The DC blocking
capacitor prevents the gate bias voltage from propagating toward the source port while allowing
RF signals to pass with minimal attenuation. The microstrip lines provide the required inductive
and capacitive reactance to transform the source impedance to the desired value at the gate of the
input transistor.

Microstrip transmission lines are preferred at mmWave frequencies due to their compatibility
with planar fabrication and their predictable electromagnetic behavior. In ADS 2022, elements
such as MLIN (microstrip line) and MLOC (microstrip open-circuited line) are used to
implement series and shunt reactive elements. The electrical lengths and characteristic
impedances of these lines are carefully chosen based on the center frequency of operation and
substrate parameters.

The output matching network is designed primarily for power matching, as noise contribution
from stages following the LNA is significantly reduced by the gain of the first stage. The goal of
the output network is to efficiently transfer the amplified signal from the drain of the cascade
transistor to the 50-ohm load while maintaining stability across the operating band. Similar to the
input network, the output matching network employs microstrip lines and open stubs to achieve
the desired impedance transformation. Tuning of the matching networks is performed using
Smith chart analysis and parametric sweeps in ADS. By adjusting the lengths and widths of the
microstrip lines, the designer can control the reactive components introduced by the matching
network. This iterative tuning process allows optimization of S-parameters such as S11, S21, and
S22 over the target frequency range.

In addition to impedance transformation, the matching networks contribute to the overall

stability of the LNA. Poorly designed matching networks can introduce resonances or feedback
paths that lead to oscillations. Therefore, stability considerations are incorporated throughout the
matching network design process. The use of short microstrip sections and well-controlled stubs
helps mitigate unwanted parasitic effects at millimeter-wave [Link] final matching

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network design represents a balance between performance, complexity, and physical reliability.
Excessively complex matching networks may improve performance marginally but increase
layout area and sensitivity to fabrication tolerances. The adopted design achieves acceptable
gain, noise figure, and matching performance while maintaining a practical and compact
structure suitable for integration in a 5G FR2 receiver front-end.

3.5. Biasing Network Design

Biasing network design is a critical aspect of Low-Noise Amplifier (LNA) operation, as it

establishes the correct operating point of the active devices while ensuring minimal interference
with the RF signal path. At millimeter-wave frequencies, improper biasing can lead to degraded
gain, increased noise figure, instability, or even device failure. Therefore, the biasing network
must simultaneously satisfy DC requirements and RF isolation constraints.

In the proposed cascade LNA, separate biasing networks are employed for the gate and drain
terminals of the transistors to allow independent optimization of noise and gain performance.
The gate bias of the input transistor (M1) determines the transconductance and thus strongly
influences the noise figure. A stable and low-noise gate bias voltage is supplied through a high-
impedance path to prevent RF signal leakage into the bias source.

Radio Frequency Chokes (RFCs) are key components in the biasing network. An RFC is
typically implemented using an inductor that presents very low impedance to DC signals while
offering high impedance to RF signals. This property allows the DC supply voltage (VDD) to
reach the drain of the cascade transistor without loading or attenuating the RF signal. At 5G FR2
frequencies, the inductance value of the RFC is carefully chosen to ensure adequate RF isolation
across the entire operating band.

In addition to RFCs, bypass and decoupling capacitors are employed to stabilize the bias
voltages and provide an AC ground for unwanted RF components. These capacitors shunt
residual RF energy to ground, thereby preventing coupling between different circuit sections
through the bias network. The values of the bypass capacitors are selected to present low
impedance at the operating frequency range while maintaining compact physical [Link]
drain bias network supplies the required VDD voltage to the cascade transistor (M11) through an

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RFC, ensuring that RF signals are confined to the signal path and do not propagate into the
power supply. Similarly, the gate bias of the cascade transistor is set to maintain it in the
common-gate configuration, which enhances isolation and stability. Proper biasing of M11 is
essential to ensure that the lower transistor (M1) experiences minimal voltage variation at its
drain.

Overall, the biasing network is designed to be robust, stable, and RF-transparent. By carefully
integrating RFCs, bypass capacitors, and high-impedance bias paths, the proposed design
achieves reliable DC operation without compromising RF performance. This biasing strategy
forms a solid foundation for accurate simulation and performance evaluation of the cascade LNA
in ADS.

Schematic diagram

he LNA is designed around a FETN5 transistor, biased to operate in the saturation region for
low-noise amplification. The input and output ports are both matched to 50 Ω, ensuring
compatibility with standard RF measurement equipment and cascaded RF blocks.

The circuit can be divided into the following functional blocks:

 Input matching network

 Gate biasing network
 Transistor core with source degeneration
 Drain biasing network
 Output matching network
 Simulation and performance evaluation blocks

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This is the full schematic diagram of LNA design:

Figure 1:Schematic diagram of cascade LNA design

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 Input Matching Network Design

The input matching network is designed to transform the 50 Ω source impedance to the optimum
gate impedance of the transistor that minimizes the noise figure at the operating frequency.

From the RF input port to the transistor gate, the matching network consists of the following
elements:

 A DC blocking capacitor (Cblock = 0.2 pF)

 A microstrip transmission line (TL2)
 A series inductor (L4 = 0.2 nH)

The DC blocking capacitor isolates the RF source from the gate bias voltage while presenting a
low impedance at 26 GHz. The transmission line provides distributed reactance and phase
adjustment, which is essential at millimeter-wave frequencies where lumped elements exhibit
limited quality factors. The series inductor enables fine impedance tuning, allowing the input
reflection coefficient (S11) to be minimized while simultaneously approaching the transistor’s
optimum noise impedance.

This combination of lumped and distributed elements provides sufficient flexibility to achieve
both low noise figure and acceptable input matching.

 Gate Biasing Network

The gate biasing network establishes the required gate-to-source voltage while isolating the RF
signal path from the DC supply. The gate is biased using a DC voltage source (Vdc = 0.7 V)
through a high-value resistor (R3 = 10 kΩ).

The large resistance value ensures that the biasing path presents a very high impedance to RF
signals, thereby preventing RF leakage into the DC source. This approach maintains stable
transistor operation without degrading the RF performance or altering the input matching
characteristics.

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 Transistor Core and Source Degeneration

The active amplification is performed by the FETN5 transistor, configured in a common-source

topology. To enhance stability and improve noise performance, inductive source degeneration is
employed.

The source terminal of the transistor is connected to ground through:

 A degeneration inductor (Ldeg)

 A small bypass capacitor (C10 = 0.01 pF)

The source degeneration inductor introduces controlled negative feedback, which improves the
amplifier’s stability factor and reduces sensitivity to process and bias variations. Additionally, it
enables a favourable trade-off between gain and noise figure, which is particularly important at
26 GHz. The bypass capacitor provides RF grounding at very high frequencies, suppressing
unwanted oscillations and feedback paths.

 Drain Biasing Network

The drain biasing network supplies DC power to the transistor while preventing RF signal
leakage into the power supply. This is achieved using a radio-frequency choke (RFC)
implemented as an inductor with a value of L8 = 12 nH, connected between the drain node and
the DC voltage source (Vdc = 0.7 V).

At the operating frequency, the RF choke presents a high impedance, effectively isolating the RF
signal from the DC supply. As a result, the amplified signal is directed exclusively toward the
output matching network, ensuring efficient power transfer and stable operation.

 Output Matching Network Design

The output matching network transforms the complex drain impedance of the transistor to 50 Ω,
thereby maximizing power transfer and forward gain (S21).

The output matching network consists of:

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 An inductor (L5 = 0.25 nH)

 A capacitor (C7 = 0.2 pF)
 A microstrip transmission line (TL1)
 An inductor (L3 = 0.2 nH)

The inductor provides the initial impedance transformation and contributes to resonance control
at the drain node. The capacitor and transmission line further adjust the impedance and phase,
enabling precise matching at 26 GHz. The final inductor provides fine tuning before the signal is
delivered to the 50 Ω output load (Term2).

4. ADS Simulation Setup

This chapter describes the simulation environment and analysis setup used to evaluate the
performance of the proposed 5G FR2 cascade Low-Noise Amplifier using Keysight Advanced
Design System (ADS). ADS provide a comprehensive RF and microwave simulation platform
that supports linear, nonlinear, and noise analysis, making it well suited for millimeter-wave
circuit design.

For this project, linear small-signal analysis is employed as the primary evaluation method, since
LNAs are designed to operate under small-signal conditions. The S-parameter controller is
inserted into the schematic to enable frequency-domain analysis over the 24.25–27.5 GHz band.
The frequency sweep range and step size are selected to provide sufficient resolution for
observing gain, matching, and stability behavior across the entire operating band.

Input and output ports are implemented using 50-ohm terminations (Term1 and Term2),
representing a standard RF system environment. Care is taken to ensure that only one terminal is
connected at each node to avoid. Ground references are properly assigned to all biasing and RF
components to ensure correct simulation behavior. Noise performance evaluation is carried out
using the Noise Figure Controller (NoiseCon) in ADS. This controller enables calculation of the
noise figure, minimum noise figure, and associated noise parameters of the LNA. The NoiseCon
block is configured to operate over the same frequency range as the S-parameter analysis to
ensure consistent comparison of results.

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4.1. Noise Figure Analysis

Noise performance is a critical metric for evaluating the suitability of a Low-Noise Amplifier for
receiver front-end applications, particularly in 5G Frequency Range 2 (FR2) systems where
received signal levels are extremely low. The noise figure of the proposed cascade LNA is
evaluated using the Noise Figure Controller (NoiseCon) in ADSacross the operating frequency
range of 24.25–27.5 GHz.

Simulation results show that the noise figure remains below 3 dB across the entire operating
band, meeting the typical requirements for 5G FR2 receiver front-ends. The minimum noise
figure is observed near the center frequency of 26 GHz, which corresponds to the optimized
operating point of the input matching network.

The achieved low noise figure is primarily attributed to the optimized biasing and impedance
matching of the input transistor (M1), which dominates the overall noise performance according
to Friis’ noise formula. The use of a source degeneration inductor improves impedance matching
while maintaining low noise contribution. Additionally, the cascade transistor (M11) effectively
suppresses feedback and parasitic effects, preventing degradation of noise performance at
millimeter-wave frequencies.

Overall, the noise figure results confirm that the proposed LNA design satisfies the noise
performance requirements for 5G FR2 applications and validates the effectiveness of the chosen
cascade architecture and matching strategy.

4.2. Stability Analysis

Stability is a critical requirement for Low-Noise Amplifiers operating at millimeter-wave

frequencies, as unintended oscillations can severely degrade receiver performance or render the
circuit unusable. An LNA is considered unconditionally stable if it remains stable for all possible
passive source and load impedances over the frequency range of interest. Due to the presence of
parasitic capacitances, inductances, and feedback paths at high frequencies, careful stability
analysis is essential in 5G FR2 LNA design.

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In this project, stability is evaluated using well-established small-signal stability criteria based on
S-parameters. The Rollett stability factor (K-factor) and the determinant of the S-parameter
matrix (Δ) are commonly used indicators. An amplifier is unconditionally stable if the conditions
K > 1 and |Δ| < 1 are satisfied across the frequency band of interest. These parameters are
computed directly in ADS using the simulated S-parameters.

2 2 2
1−|S 11| −|S 22| +|∆|
K= Δ=S 11 S 22−S 12 S 21
2|S 12 S 21|

The cascade topology inherently improves stability by reducing reverse transmission (S12)
through the suppression of the Miller effect. The common-gate transistor (M11) isolates the input
stage from output voltage variations, thereby minimizing feedback paths that could otherwise
lead to oscillations. This architectural advantage makes the cascade configuration particularly
suitable for mmWave LNA applications.

In addition to the cascade structure, several circuit-level techniques are employed to enhance
stability. Source degeneration inductance at the input transistor provides local negative feedback,
which improves stability while maintaining acceptable noise performance. Properly designed
input and output matching networks further contribute to stability by avoiding resonant
conditions and excessive phase shifts.

Simulation results confirm that the stability factor K remains greater than unity across the entire
operating frequency range of 24.25–27.5 GHz, indicating unconditional stability within the 5G
FR2 band. Stability is also verified beyond the operating band to ensure that no spurious
oscillations occur at higher frequencies. This wideband stability assessment is important for
practical implementation, where out-of-band behavior can still affect circuit reliability.

Overall, the stability analysis demonstrates that the proposed cascade LNA design is robust and
well-suited for millimeter-wave receiver front-end applications. The combination of cascade
topology, source degeneration, and carefully designed matching networks ensures stable
operation without compromising gain or noise figure. These results validate the design
methodology and confirm the suitability of the proposed LNA for 5G FR2 systems.

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5. Simulation Results

This chapter presents and discusses the simulation results of the proposed 5G FR2 cascade Low-
Noise Amplifier (LNA) designed and analyzed using Keysight Advanced Design System (ADS)
2022. The performance of the LNA is evaluated based on key RF metrics, including small-signal
gain, input and output impedance matching, and noise figure. These parameters are critical in
determining the suitability of the LNA for millimeter-wave receiver front-end applications.

All simulations are carried out using linear S-parameter and noise analysis under small-signal
operating conditions. The results are obtained over the target frequency range of 24.25–27.5
GHz, corresponding to the 5G FR2 band.

5.1. Gain Analysis

The forward transmission coefficient, denoted by S21, represents the small-signal gain of the
LNA. The proposed LNA achieves a peak gain of approximately 12 dB at 26 GHz, which
corresponds to the center frequency of the design.

Across the entire FR2 operating band, the gain remains above 10 dB, indicating consistent
amplification performance. This level of gain is sufficient to amplify weak received signals while
minimizing the impact of noise contributions from subsequent stages in the receiver chain.

The achieved gain performance is primarily attributed to:

 The high transconductance of the input transistor (M1)

 The cascade configuration using transistor M11, which suppresses the Miller effect
 Proper biasing that ensures operation in the desired saturation region

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Figure 2:Gain(S21 in dB)

S21 represents the small-signal gain of the LNA across the operating band.
The increasing gain toward higher frequencies indicates resonance
alignment closer to the upper Ka-band.

The cascade architecture also improves gain flatness by reducing feedback and parasitic
capacitance effects, which are especially significant at millimeter-wave frequencies.

GdB=20 log 10 ∣ S 21 ∣

 Represents the ratio of output signal to input signal.

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Figure 3:S12 in dB

S12 remains very low across the band, indicating excellent reverse isolation.
This confirms good amplifier stability and minimal feedback from output to
input.

5.2. Input and Output Matching Analysis

Impedance matching is essential to ensure maximum power transfer and minimize signal
reflections at both the input and output ports of the LNA. The input and output matching
performance is evaluated using the reflection coefficients S11 and S22, respectively.

5.2.1. Input Matching (S11)

The simulated input reflection coefficient (S11) remains below −10 dB over most of the
operating band, indicating good impedance matching between the source and the LNA input.

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This level of matching ensures that a majority of the input signal power is delivered to the
amplifier rather than being reflected back toward the source.

RLin=−20 log 10 ∣ S 11∣

Γin=S 11

The input matching network is designed with a combination of microstrip transmission lines and
lumped components, carefully optimized to provide a compromise between noise matching and
power matching. This approach is essential in LNA design, as minimum noise impedance does
not necessarily coincide with the conjugate match condition.

Figure 4:Input return loss(S11 in dB)

The response shows how well the input matching network matches the 50 Ω
source over frequency.

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The gradual degradation toward 30 GHz indicates reduced matching

accuracy away from the design center frequency.

5.2.2. Output Matching (S22)

The output reflection coefficient (S22) also remains better than −10 dB across the target
frequency range. This confirms effective impedance matching at the output, which facilitates
efficient power transfer to the next stage of the receiver, typically a mixer or another
amplification stage.

RLout=−20 log 10 ∣ S 22 ∣

 Ensures maximum power transfer to the load

 reduces standing waves at output

Proper output matching also contributes to overall circuit stability and helps maintain consistent
gain across the operating band.

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Figure 5:Output return loss(S22 in dB)

S22 characterizes how well the output matching network transforms the
drain impedance to 50 Ω.
The curve indicates moderate matching, with degradation at higher
frequencies due to parasitic effects.

5.2.3. Noise Figure Analysis

Noise figure (NF) is one of the most critical performance parameters of a Low-Noise Amplifier,
as it directly affects the overall sensitivity of the receiver. The noise performance of the proposed
LNA is evaluated using the Noise Figure Controller (NoiseCon) in ADS 2022.

Simulation results show that the noise figure remains below 3 dB across the entire operating
frequency range of 24.25–27.5 GHz, satisfying the typical requirements for 5G FR2 receiver
front-end applications. The minimum noise figure occurs near the center frequency of 26 GHz,
where the input matching network is optimally tuned.

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The low noise performance is mainly due to:

 Optimized biasing of the input transistor (M1)

 Carefully designed source degeneration inductance
 Reduced feedback and parasitic effects provided by the cascade transistor (M11)

According to Friis’ noise equation, the noise contribution of the first stage dominates the overall
receiver noise figure. Therefore, achieving a low noise figure in the proposed LNA significantly
enhances the overall system performance.

NF =(S /N )∈ ¿ ¿
(S / N )out

In Decibels
NFdB=10 log 10 NF

5.3. Noise Figure of Cascaded Stages (Friis Formula)

NF 2 −1 NF 3−1
NF tot =NF 1+ +
G1 G1 G2

The simulation results demonstrate that the proposed cascade LNA meets the key performance
requirements for 5G FR2 applications. The amplifier provides sufficient gain, effective
impedance matching, and low noise figure across the target frequency band.

In summary:

 Gain (S21): Greater than 10 dB across the band

 Input Matching (S11): Better
 Output Matching (S22): Better
 Noise Figure: Below 3 dB across 24.25–27.5 GHz

These results validate the design methodology and confirm that the proposed LNA is suitable for
millimeter-wave receiver front-end application.

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Figure 6:NF in dB

The Noise Figure (NF) values are well below the 2.5 dB requirement. The decrease with
frequency is typical in mmWave LNAs, as transistor noise performance often improves at higher
frequencies due to reduced flicker noise and optimized matching near the design frequency (26
GHz). This indicates proper noise matching and effective bias point selection.

6. Trade-Off Analysis

The design of a millimeter-wave Low-Noise Amplifier (LNA) involves balancing multiple

conflicting performance objectives. Key trade-offs arise between gain, noise figure, power
consumption, and stability, particularly at 5G FR2 frequencies where parasitic effects and device
limitations become more pronounced.

6.1. Gain versus Noise Figure Trade-Off

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One of the most fundamental trade-offs in LNA design is between gain and noise figure (NF).
Increasing gain typically requires higher transconductance in the input transistor, which can be
achieved by increasing bias current or device size. However, higher bias current often leads to
increased thermal noise, while larger device dimensions introduce additional parasitic
capacitances that degrade high-frequency performance.

In the proposed design, the input transistor (M1) is biased to achieve sufficient transconductance
for gain enhancement while maintaining a low noise figure. The input matching network is
carefully optimized to present impedance close to the optimum noise impedance rather than the
exact conjugate match. This deliberate compromise allows the noise figure to remain below 3 dB
across the operating band while still achieving a gain greater than 10dB.

The use of a cascade architecture further helps alleviate this trade-off by increasing gain without
significantly increasing noise contribution. Since the cascade transistor (M11) does not directly
contribute to input-referred noise, it allows gain improvement while preserving low noise
performance.

6.2. Gains versus Power Consumption Trade-Off

Another important trade-off exists between gain and power consumption. Higher gain often
necessitates increased bias current and supply voltage, leading to higher DC power consumption.
This trade-off is particularly critical in 5G mobile and portable devices, where energy efficiency
is a major design constraint.

In this project, moderate bias currents are selected to ensure acceptable gain while avoiding
excessive power dissipation. The cascade configuration enables higher gain at a given current
level compared to a single-transistor amplifier, making it a power-efficient solution for
millimeter-wave applications.

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Although the design does not explicitly optimize for ultra-low power consumption, the chosen
biasing strategy represents a practical compromise between amplification performance and
energy efficiency. This balance ensures that the LNA is suitable for 5G FR2 receiver front-end
applications without imposing excessive power demands on the system.

6.3. Noise Figure versus Stability Trade-Off

Improving noise figure often involves biasing the input transistor near its optimum noise
condition and minimizing resistive losses in the signal path. However, these measures can
sometimes reduce circuit stability, especially at high frequencies where parasitic feedback paths
become significant.

Stability enhancement techniques such as resistive loading, heavy source degeneration, or

feedback networks can suppress oscillations but may degrade noise performance by introducing
additional thermal noise or reducing gain. In the proposed design, a small source degeneration
inductor is employed to improve stability and input matching with minimal impact on noise
figure.

The cascade architecture also plays a crucial role in maintaining stability. By isolating the input
from output voltage variations, the cascade transistor significantly reduces the likelihood of
unwanted feedback and oscillations. As a result, the design achieves unconditional stability
across the operating band without sacrificing low noise performance.

6.4. Power Consumption versus Stability Trade-Off

Biasing conditions that reduce power consumption, such as lower drain current or supply
voltage, can sometimes push transistors closer to their nonlinear or suboptimal operating regions.
This may lead to reduced gain margin and compromised stability.

To avoid this issue, the biasing network in the proposed LNA is designed to ensure that both
transistors operate well within the saturation region under all simulated conditions. While this
results in moderate power consumption, it guarantees reliable and stable operation across the
entire frequency band.

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This design choice reflects a priority on robustness and repeatability, which are essential for
practical millimeter-wave RF front-end circuits.

6.5. Overall Design Trade-Off Summary

The final performance of the proposed 5G FR2 cascade LNA represents a carefully engineered
compromise among multiple competing objectives. The key trade-offs addressed in this design
can be summarized as follows:

 Gain vs. Noise Figure: Balanced through optimized biasing and input matching
 Gain vs. Power Consumption: Improved using a cascade topology for higher efficiency
 Noise Figure vs. Stability: Managed through source degeneration and cascade isolation
 Power Consumption vs. Stability: Resolved by maintaining safe and stable bias
conditions

By prioritizing low noise figure and stable operation while maintaining adequate gain and
reasonable power consumption, the proposed LNA achieves performance well suited for 5G FR2
receiver front-end applications.

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7. Conclusion

the design and simulation of a 5G FR2 cascade Low-Noise Amplifier have been presented and
thoroughly analyzed using Keysight ADS 2022. The study focused on addressing the key
challenges associated with millimeter-wave LNA design, including achieving sufficient gain,
maintaining a low noise figure, ensuring good impedance matching, and guaranteeing
unconditional stability across the operating frequency band.

Cascade LNA architecture was selected due to its superior performance at high frequencies. The
common-source input stage was optimized for low noise performance, while the common-gate
cascade transistor effectively reduced the Miller effect and improved reverse isolation and
stability. Carefully designed microstrip-based input and output matching networks enabled
efficient impedance transformation while balancing the trade-off between noise and power
matching.

Simulation results verified that the proposed LNA meets the targeted performance specifications
for 5G FR2 applications. The amplifier achieved a gain greater than 10 dB across 24.25–27.5
GHz, input and output return losses better than −0.3 dB, and a noise figure consistently below 3
dB. Stability analysis using the Rollett stability factor confirmed unconditional stability
throughout the operating band and beyond, ensuring robust and reliable operation.

Trade-off analysis further highlighted how competing requirements such as gain, noise figure,
power consumption, and stability were balanced through appropriate architectural choices,
biasing strategies, and matching network design. While the design prioritizes performance
verification over fabrication readiness, it successfully demonstrates fundamental RF design
principles applicable to practical 5G mmWave receiver front-end circuits.

In conclusion, the proposed cascade LNA design satisfies the essential requirements of 5G FR2
systems and provides a strong academic foundation for further work, including electromagnetic
co-simulation, layout optimization, fabrication, and experimental validation.

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8. References

1. T. S. Rappaport et al., “Millimeter Wave Mobile Communications for 5G Cellular: It

Will Work!”,IEEE Access, vol. 1, pp. 335–349, 2013.
2. 3GPP TS 38.101-2, User Equipment (UE) Radio Transmission and Reception; Part 2:
Range 2 Standalone, 3GPP, Release 16.
3. B. Razavi, RF Microelectronics, 2nd ed., Pearson Education, 2012.
4. D. M. Pozar, Microwave Engineering, 4th ed., Wiley, 2011.
5. H. T. Friis, “Noise Figures of Radio Receivers,” Proceedings of the IRE, vol. 32, no. 7,
pp. 419–422, 1944.
6. J. Craninckx and M. Steyaert, “A 5-GHz Low-Noise Amplifier in 90-nm CMOS,” IEEE
Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2598–2607, 2005.
7. Y. Wang et al., “A 28-GHz CMOS Low-Noise Amplifier for 5G Applications,” IEEE
Microwave and Wireless Components Letters, vol. 27, no. 8, pp. 747–749, 2017.
8. Keysight Technologies, Advanced Design System (ADS) 2022 Documentation, Keysight,
2022.

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