Integration levels
Moore’s Law
Logic family
• Bipolar
– Saturated
• DL (Diode logic )
• RTL(Resistor-Transistor logic)
• DTL(Diode-Transistor logic)
• TTL(Transistor-Transistor logic)
– Non- saturated
• Schottky TTL
• ECL(Emitter Coupled logic)
• Unipolar
– PMOS(P-channel Metal Oxide Semiconductor )
– NMOS(N-channel Metal Oxide Semiconductor )
– CMOS(Complementary Metal Oxide Semiconductor logic)
Characteristics of Logic families
• Speed: The speed of a logic circuit is determined by the time
between the application of input and change in the output of
the circuit.
• Fan-in: It determines the number of inputs the logic gate can
handle.
• Fan-out: Determines the number of circuits that a gate can
drive.
• Noise Immunity: Maximum noise that a circuit can withstand
without affecting the output.
• Power dissipation: When a circuit switches from one state to
the other, power dissipates.
Characteristics: Voltage levels
Characteristics: Current levels
Fan- in
• Fan in is the number of inputs that can
practically be supported without degrading
practically input voltage level.
Fan - out
Propagation delay
Noise margin
TTL
TTL- NOT gate
• When the input A is low, the base-emitter junction of Q1 is
forward biased, and the base-collector junction is reverse
biased.
• So transistor Q2 and Q4 is cut off.
• Transistor Q3 goes to saturation and diode D2 starts
conducting and output is connected to Vcc and goes to logic
high.
• Similarly, when input is at logic high, the output is at logic
low.
TTL- NOR gate
TTL
• Three output configurations
– Open collector output
– Totem-pole output
– Tristate output
Open collector configurations
• The main feature is that its output is 0 when low
and floating when high.
• In the open collector TTL gate, the output stage does
not have the active pull-up transistor i.e. Q3 and
the output is taken at the collector of transistor Q4.
In order to generate required HIGH state, an external
pull-up resistor is connected to +Vcc from
the collector of Q4.
Totem pole configuration
• Totem Pole means the addition of an active
pull up the circuit in the output of the Gate
which results in a reduction of propagation
delay.
Tri-state configuration
• Low-level state when a lower transistor is ON and an upper
transistor is OFF.
• High-level state when the lower transistor is OFF and the
upper transistor is ON.
• Third state when both transistors are OFF.
Features of TTL family
• Logic low level is at 0 or 0.2V.
• Logic high level is at 5V.
• Typical fan out of 10. It means it can support at
most 10 gates at its output.
• A basic TTL device draws a power of almost
10mW, which reduces with the use of Schottky
devices.
• The average propagation delay is about 9ns.
• The noise margin is about 0.4V.
ECL
• Fastest of all logic families
• High speed is possible in ECL because transistors
are used in differential amplifier configuration,
never driven to saturation, storage delay time is
eliminated
• Transistors are driven either in cut off or in an
active region. This is achieved by using voltage
values close to each other.
• For logic one, it is -0.9 and for logic zero, it is -
1.75v.
ECL
• The difference between two logic states is
very small. This improves the speed of
operation.
• The propagation time for an ECL gate is 0.5 to
2ns, which is very less when compared to its
TTL counterpart.
ECL
• Drawbacks of ECL
– Low noise margin
– High power dissipation
– It uses negative voltage supply which makes it
difficult to use ECL in conjunction with TTL and
MOS circuits
CMOS
• CMOS -Complementary Metal Oxide
Semiconductor
• High noise immunity
• low static power dissipation
• CMOS has complementary and symmetrical
NMOS and PMOS transistors.
CMOS-NAND gate
• When both inputs A and B are at high,
transistors T1, T2 will be ON
and transistors T3, T4 will be OFF.
There is a direct connection
between output and ground through
transistor T3 and T4. The output is
pulled down to zero.
• When any of the input is low, either
transistor T3 or T4 will be off.
This breaks the connection between
the output terminal and the ground.
One of the PMOS transistors is ON, so there is a connection
between output and power supply. Now the output is pulled up to
logic high.
Digital logic circuits
• A logic circuit in which outputs are assumed to
be having finite number of distinct values are
called digital logic circuit. Two types
– Combinational logic: output at any instant of time
depends only on inputs present at that instant of
time. Do not have memory devices
– Sequential logic: output not only dependent on
the present input, but also on past inputs. Having
memory devices in order to store the past input
conditions.
Combinational logic circuits
CMOS-NOT gate
Adders
• Half adder: accepts two binary digits on its
inputs and produces two binary outputs- sum
and carry
• Full adder: accepts two binary inputs and an
input carry to produce sum and carry at the
output
Half adder
Binary Addition example
A2 A1 A0 +
B2 B1 B0
S 2 S1 S0
Full adder
Full adder
Full adder
Full adder
B Cin B Cin
00 01 11 10
A
0 1
1 1 1 1
Cout= A’ B Cin + A B’ Cin + AB Cin + AB Cin’
S= A’B’Cin +A’B Cin’+AB’ Cin’ + AB Cin
= Cin (A’B +AB’) + AB(Cin+Cin’ )
= Cin (A’B’ +AB) + Cin’ (A’B+ AB’)
=
= Cin ( ))))) )’ + Cin’ ( )
=
Subtractors
• Half subtractor
= A’B
Subtractors
• Full subtractor
Bin
= Bin
B
A
Full subtractor
Full subtractor
• Full subtractor using half subtractors
Comparators
• Compare the magnitude of two binary
quantities
1-bit magnitude comparator
2-bit comparator
4-bit comparator
Decoders
• Detects the presence of specified combination
of bits on its inputs and indicates the presence
of that code by a specified output level.
• Combinational circuit that has n-input lines
and maximum of 2n output lines; one of these
output line will be high depends upon the
combination of inputs present
• so called n line –to- 2n line decoder
2 to 4 decoder
• 2 inputs and 4 outputs.
2 to 4 decoder
• Boolean function for each output
3 to 8 decoder
• 3 inputs and eight outputs
3 to 8 decoder
3 to 8 decoder
3 to 8 decoder
Encoders
• Reverse operation of decoder
Octal to Binary encoder
• 8 inputs and 3 outputs
Octal to Binary encoder
• Circuit diagram
Decimal to BCD encoder
Decimal to BCD encoder
• Circuit diagram
Encoders
• Drawback of encoder
Code converters
• Combinational logic circuits to convert from one
code to another
• Binary- to- Gray conversion
• Gray- to-Binary conversion
• BCD- to- Binary conversion
Binary –to-Gray and Gray-to-Binary
conversion
Binary-to-BCD conversion
• Step 1: Convert the binary number to decimal
• Step 2: Convert the decimal to BCD
• Example (11101)2 to BCD
– Step 1 : convert to decimal
Binary-to-BCD conversion
• Step 2: convert to BCD
Truth table