Design and Implementation of Image

Processing Techniques on FPGA Using

Verilog HDL

A Thesis Submitted in Partial Fulfillment of the Requirements

for the Award of the Degree of

Bachelor of Technology
in
Electronics and Communication Engineering

Submitted by
NAME

Under the Guidance of

Dr. XXXXXXX

Department of Electronics and Communication Engineering

RK COLLEGE
2025–2026
 DECLARATION

I hereby declare that the thesis entitled “Design and Implementation of Image
Processing Techniques on FPGA Using Verilog HDL” is a bona fide record of
work carried out by me under the guidance of Dr. , and that this
thesis has not been submitted previously, in part or in full, to any other university or
institution for the award of any degree or diploma.

Place:

Date:

Signature of the Student

NAME
Register Number:
 CERTIFICATE

This is to certify that the thesis entitled “Design and Implementation of Im-
age Processing Techniques on FPGA Using Verilog HDL” submitted by Ashok
Chakravarthy (Register Number: ) to the Name of the Uni-
versity, in partial fulfillment of the requirements for the award of the degree of Master
of Technology in the Department of , is a bona fide record of
work carried out by him under my supervision and guidance during the academic year
2025–2026.

Supervisor

Dr.
Designation
Department of
Name of the Institution

Head of the Department

Dr.
Designation
Department of
Name of the Institution

Place: Date:
 ACKNOWLEDGEMENT

I express my sincere gratitude to my supervisor Dr. , for

his/her invaluable guidance, constant encouragement, and insightful suggestions through-
out the course of this research work. His/Her expertise and motivation played a crucial
role in the successful completion of this thesis.
I would like to thank the Head of the Department, Dr. ,
for providing the necessary facilities and a conducive research environment to carry out
this work.
I extend my heartfelt thanks to all the faculty members of the Department of
for their support, constructive feedback, and encouragement dur-
ing my academic tenure.
I am grateful to my friends and classmates for their cooperation, discussions, and
moral support throughout the project work. I also thank the technical and non-teaching
staff of the department for their assistance.
Finally, I express my deepest gratitude to my parents and family members for their
unconditional love, patience, and continuous encouragement, which have been the foun-
dation of my academic journey.

NAME
 ABSTRACT

Image processing plays a crucial role in modern embedded and real-time systems,
with applications ranging from medical imaging and surveillance to industrial automa-
tion and multimedia systems. Conventional software-based image processing approaches
implemented on general-purpose processors often face limitations in terms of processing
speed, power consumption, and real-time performance.
This thesis presents the design and implementation of an FPGA-based image process-
ing system using Verilog Hardware Description Language (HDL). The proposed system
focuses on the offline processing of bitmap (.bmp) images by converting image data into
a hexadecimal format suitable for FPGA memory initialization. The image pixels are
processed using dedicated hardware modules implemented in Verilog, enabling efficient
parallel execution of image processing operations.
Basic image processing techniques such as image inversion, brightness adjustment, and
thresholding are implemented and verified through simulation. The system architecture
is designed to be modular and scalable, allowing easy integration of additional image
processing functions. Functional correctness is validated using simulation tools, and the
processed output images demonstrate the effectiveness of the hardware-based approach.
The results highlight the advantages of FPGA-based image processing in terms of
parallelism, deterministic performance, and resource efficiency. The proposed design
serves as a foundation for developing real-time image and video processing systems by
extending the architecture to support camera interfaces, display modules, and advanced
image processing algorithms.

Keywords: NIR-II Imaging, NIR-IIB, Image Enhancement, Generative Adversarial Net-

works, Explainable AI, Unpaired Learning, Biomedical Imaging
Contents

1 Introduction 10
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 FPGA in Image Processing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Objectives of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 Scope of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.7 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Literature Review 14
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 FPGA for Image Processing: Advantages and Trends . . . . . . . . . . . 14
2.3 Design Methodologies and Toolflows . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Memory and I/O considerations . . . . . . . . . . . . . . . . . . . 15
2.4 BMP / Hex-based FPGA Implementations (Practical Examples) . . . . . 15
2.5 Hardware IPs and Soft-Processor Approaches . . . . . . . . . . . . . . . 15
2.6 Theses and Academic Implementations . . . . . . . . . . . . . . . . . . . 15
2.7 Performance Metrics and Evaluation Practices . . . . . . . . . . . . . . . 16
2.8 Gap Analysis and Motivation for the Present Work . . . . . . . . . . . . 16
2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 System Architecture 17
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Overall System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Input Image Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Control and Address Generation Unit . . . . . . . . . . . . . . . . . . . . 18
3.5 Image Processing Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Output Image Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Module-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Implementation 22
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Image Preprocessing and Data Conversion . . . . . . . . . . . . . . . . . 22
4.4 Image Loader Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4.1 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 23

5
 4.5 Control Unit and Address Generation . . . . . . . . . . . . . . . . . . . . 23
4.6 Image Processing Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6.1 Image Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6.2 Brightness Adjustment . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6.3 Thresholding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 Output Image Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 Top-Level Module Integration . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9 Simulation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Results and Output Images 26

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Input Image Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 Image Inversion Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5 Brightness Adjustment Results . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 Thresholding Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Conclusion and Future Scope 30

6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of Figures

1.1 Digital image representation using pixel matrices . . . . . . . . . . . . . 10

1.2 General architecture of an FPGA . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Comparison between CPU-based and FPGA-based image processing . . . 12
1.4 Basic FPGA-based image processing flow . . . . . . . . . . . . . . . . . . 13

3.1 Overall FPGA-based image processing system architecture . . . . . . . . 18

3.2 FPGA image processing pipeline . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Verilog module-level architecture of the system . . . . . . . . . . . . . . . 20

5.1 Original input grayscale image . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Output image after inversion operation . . . . . . . . . . . . . . . . . . . 28
5.3 Output image after brightness adjustment . . . . . . . . . . . . . . . . . 29
5.4 Output image after thresholding . . . . . . . . . . . . . . . . . . . . . . . 29
List of Tables
 LIST OF ABBREVIATIONS

NIR Near Infrared

NIR-II Second Near-Infrared Window
NIR-IIBExtended Second Near-Infrared Window (1500–1700 nm)
GAN Generative Adversarial Network
CycleGAN
Cycle-Consistent Generative Adversarial Network
xAI Explainable Artificial Intelligence
CNN Convolutional Neural Network
FID Fréchet Inception Distance
MRI Magnetic Resonance Imaging
CT Computed Tomography
GPU Graphics Processing Unit
DL Deep Learning
Chapter 1

Introduction

1.1 Background
Digital image processing is a rapidly growing field that involves the manipulation and
analysis of digital images to improve their visual quality or to extract useful information.
A digital image is represented as a two-dimensional array of pixels, where each pixel
corresponds to an intensity or color value. Figure 1.1 illustrates the basic concept of
pixel-based image representation.
Image processing techniques are widely used in applications such as medical diagnos-
tics, satellite imaging, surveillance systems, industrial inspection, robotics, and multi-
media systems. These applications often require high-speed processing and low latency,
especially in real-time environments.
Traditional image processing systems are implemented using software platforms such
as CPUs and GPUs. Although these platforms offer flexibility, they are often limited by
sequential execution, high power consumption, and unpredictable timing behavior when
handling large volumes of image data.

1.2 FPGA in Image Processing

Field Programmable Gate Arrays (FPGAs) are reconfigurable hardware devices composed
of logic blocks, programmable interconnections, and input/output modules. Unlike fixed-
function processors, FPGAs allow designers to implement custom hardware architectures
tailored to specific applications. A general FPGA architecture is shown in Figure 1.2.
One of the major advantages of FPGAs is their ability to perform parallel process-
ing. In image processing, operations on multiple pixels can be executed simultaneously,

Figure 1.1: Digital image representation using pixel matrices

10
 Figure 1.2: General architecture of an FPGA

resulting in significant performance improvements. Additionally, FPGA-based systems

provide deterministic timing and low latency, making them suitable for real-time image
processing applications.

1.3 Motivation
The motivation for this thesis arises from the increasing demand for efficient, high-speed,
and low-power image processing systems. Software-based approaches often struggle to
meet real-time constraints due to limited parallelism and high computational overhead.
FPGA-based image processing provides a promising solution by exploiting fine-grained
parallelism at the hardware level. Figure 1.3 highlights the difference between serial
processing in CPUs and parallel processing in FPGAs.
By implementing image processing algorithms using Verilog HDL, designers gain full
control over hardware resources, enabling optimized performance and efficient utilization
of FPGA logic elements.

1.4 Problem Statement

Despite the widespread use of image processing algorithms, many existing systems rely on
software implementations that are not suitable for real-time and embedded applications.
These systems often suffer from high latency, excessive power consumption, and limited
scalability.
The problem addressed in this thesis is the design and implementation of an FPGA-
based image processing system using Verilog HDL. The system aims to efficiently process
bitmap images by reading pixel data, applying selected image processing operations, and
generating a processed output image.

1.5 Objectives of the Thesis

The main objectives of this thesis are:

• To study fundamental concepts of digital image processing.

11
 Figure 1.3: Comparison between CPU-based and FPGA-based image processing

• To understand FPGA architecture and Verilog HDL design methodology.

• To design an FPGA-based image processing framework.

• To implement basic image processing operations such as inversion, brightness ad-

justment, and thresholding.

• To verify the design through simulation and analyze system performance.

1.6 Scope of the Work

This work focuses on offline image processing using bitmap (.bmp) images. The input
image is converted into a hexadecimal format and loaded into FPGA memory for pro-
cessing. The output image is reconstructed after applying the selected image processing
operation.
Figure 1.4 illustrates the basic flow of FPGA-based image processing implemented in
this work.
The proposed system is scalable and can be extended to real-time applications by
integrating camera modules, VGA or HDMI displays, and external memory interfaces.

12
 Figure 1.4: Basic FPGA-based image processing flow

1.7 Organization of the Thesis

The thesis is organized as follows:

• Chapter 2 presents a comprehensive literature review on FPGA-based image pro-

cessing systems.

• Chapter 3 describes the system architecture and design methodology.

• Chapter 4 explains the implementation details and Verilog modules.

• Chapter 5 discusses experimental results and performance analysis.

• Chapter 6 concludes the thesis and outlines future enhancements.

13
Chapter 2

Literature Review

2.1 Introduction
This chapter reviews prior work and relevant literature in the area of FPGA-based image
processing. It covers (a) general FPGA advantages for image processing, (b) common
design approaches and toolflows, (c) practical implementations that read and process
BMP images on FPGA using Verilog, (d) hardware IP/processor solutions for image
tasks, and (e) a gap analysis that motivates the present thesis.

2.2 FPGA for Image Processing: Advantages and

Trends
Field Programmable Gate Arrays (FPGAs) offer fine-grained parallelism, deterministic
timing, and reconfigurability — attributes that make them well suited to image-processing
tasks that require low latency and high throughput [?]. Several survey and review articles
demonstrate FPGA implementations of filters (median, convolution), morphological op-
erations, edge detection, and more complex pipelines, often showing significant speed and
latency advantages over CPU-based implementations, and competitive power efficiency
compared to GPUs for certain embedded tasks [?, ?].

2.3 Design Methodologies and Toolflows

Two common development approaches are observed in literature:

1. RTL/HDL-based design: Direct implementation in Verilog or VHDL to create

custom pixel pipelines, line buffers, and FSM-based controllers. This approach
yields highly optimized designs but requires substantial low-level hardware expertise
[?].

2. High-level/Model-based design: Use of high-level synthesis (HLS), System

Generator (Simulink/Xilinx), or soft-core processors to accelerate design and re-
duce development time at some cost of resource overhead [?, ?].

14
2.3.1 Memory and I/O considerations
Image processing on FPGA typically requires careful memory planning: on-chip block
RAMs (BRAM) for line buffers, external DDR/SDRAM for large frames, and DMA/host
interfaces for streaming designs. Many educational and prototype projects use offline ap-
proaches where a BMP image is converted to a hex/text file and loaded into an FPGA
memory via ‘readmemh‘duringsimulationorROM initialization; thissimplif iestestingandverif ication

2.4 BMP / Hex-based FPGA Implementations (Prac-

tical Examples)
A frequently-cited practical workflow for learning and prototyping is:

1. Convert a ‘.bmp‘ file to a hexadecimal or binary memory initialization file using

MATLAB/Python scripts.

2. Use ‘readmemh‘or‘readmemb‘ in Verilog testbenches or ROM modules to initialize

pixel data in simulation/Synthesizable ROM.

3. Implement pixel-processing blocks (inversion, brightness, thresholding, basic filters)

and write out processed data, then convert back to BMP for result visualization
[?, ?, ?].

Educational resources and sample projects demonstrating this flow are widely avail-
able and are particularly useful when starting hardware implementations of basic image
operations [?].

2.5 Hardware IPs and Soft-Processor Approaches

Several research works propose soft-core or IP-based image processors to balance pro-
grammability and performance. The Image Processing Processor (IPPro) and related
soft-core designs permit running image kernels at high frequency and offer a software-like
programming model while retaining the benefits of FPGA acceleration. These approaches
are useful for accelerating more algorithmic workloads where frequent algorithm changes
are expected [?, ?].

2.6 Theses and Academic Implementations

Full theses and academic dissertations provide deeper design case-studies:

• Sreejith’s thesis, “Development of an FPGA Based Image Processing Intellectual

Property Core,” provides an IP-centric approach and implementation details for
FPGA image cores, including test methodology and resource analysis [?].

• Shaonan Zhang’s thesis, “Real Time Image Processing on FPGAs,” explores SoC/FPGAs
and streaming real-time design trade-offs on low-cost devices and is useful for un-
derstanding practical real-time constraints and platform selection [?].

15
 • Classic Verilog/HDL educational projects (e.g., Nelson’s work and many community
tutorials) document hands-on examples for implementing BMP read/process/write
flows and basic algorithm hardware implementations [?, ?].

2.7 Performance Metrics and Evaluation Practices

The literature consistently evaluates FPGA image-processing designs using:

• Throughput (pixels/second) and latency (per-frame or per-pixel).

• Resource utilisation: LUTs, FFs, BRAM, DSP blocks.

• Power consumption and clock frequency trade-offs.

• Quality metrics: PSNR/SSIM when compared to floating-point/software refer-

ence implementations for filters and transforms.

Benchmarking against software (MATLAB/CPU) and reporting a clear methodology

(test images, input resolution, clock domain) is important for reproducible results [?, ?].

2.8 Gap Analysis and Motivation for the Present

Work
From the reviewed literature, the following gaps are noted:

• Many educational projects demonstrate BMP-to-hex workflows and implement sim-

ple operators but do not provide resource-optimised, parameterisable RTL modules
suitable for moderate-resolution images in constrained FPGAs [?].

• Several IP/processor solutions target performance but add software complexity

and resource overhead; a balanced RTL implementation that is both modular and
resource-aware remains a valuable contribution [?, ?].

• Real-time, camera-driven pipelines with robust memory interfaces and timing clo-
sure on low-cost boards are addressed in PhD-level work but remain challenging for
undergraduate or small MTech projects; an intermediate, well-documented HDL
implementation with clear verification flow adds educational and practical value
[?, ?].

2.9 Summary
This chapter surveyed prior work in FPGA-based image processing, practical BMP/hex
workflows for Verilog-based prototypes, IP/soft-processor approaches, and academic the-
ses addressing real-time FPGA pipelines. The literature confirms that FPGA implemen-
tations offer significant benefits for image-processing tasks and highlights where a focused
Verilog-based, resource-aware implementation (with clear verification and reproducible
results) can contribute to both educational and applied research contexts.

16
Chapter 3

System Architecture

3.1 Introduction
This chapter describes the overall architecture and design methodology of the proposed
FPGA-based image processing system. The system is designed using Verilog Hardware
Description Language (HDL) and focuses on offline processing of bitmap images. The
architecture is modular in nature, enabling scalability and ease of extension for additional
image processing operations.

3.2 Overall System Overview

The proposed system processes a bitmap image by reading pixel data from memory,
applying selected image processing operations, and generating a processed output im-
age. Figure 3.1 shows the high-level block diagram of the FPGA-based image processing
system.
The major functional blocks of the system include:

• Input Image Memory

• Control and Address Generation Unit

• Image Processing Core

• Output Image Memory

• File Input/Output Interface (Simulation Level)

3.3 Input Image Memory

The input image is initially stored in bitmap (.bmp) format and converted into a hex-
adecimal file using external tools such as MATLAB or Python. This hexadecimal file is
loaded into the FPGA memory using the Verilog system task $readmemh.
The input memory stores pixel intensity values sequentially and provides them to
the processing core based on the generated memory addresses. This approach simplifies
testing and verification of the image processing algorithms.

17
 system_overview.png

Figure 3.1: Overall FPGA-based image processing system architecture

3.4 Control and Address Generation Unit

The control unit is responsible for coordinating data flow between different modules.
It generates memory addresses for reading input pixels and writing processed pixels to
output memory.
A finite state machine (FSM) is employed to manage different stages of operation, such
as initialization, pixel reading, processing, and writing. The address generator ensures
that pixels are processed in the correct order.

3.5 Image Processing Core

The image processing core performs pixel-level operations on the input image. Figure 3.2
illustrates the internal processing pipeline.
The core supports multiple image processing operations, including:

• Image inversion

18
 processing_pipeline.png

Figure 3.2: FPGA image processing pipeline

• Brightness adjustment

• Thresholding

The operation mode is selected using control parameters defined in the Verilog de-
sign. Each pixel is processed independently, allowing parallelism and efficient hardware
utilization.

3.6 Output Image Memory

After processing, the output pixel values are stored in output memory. This memory
holds the processed image data in hexadecimal format.
The output memory contents are later written to an output file during simulation,
which can be converted back to bitmap format for visual verification of results.

3.7 Module-Level Architecture

Figure 3.3 shows the module-level organization of the proposed system.

19
 module_architecture.png

Figure 3.3: Verilog module-level architecture of the system

The system is divided into the following Verilog modules:

• Image Loader Module

• Processing Module

• Controller Module

• Image Writer Module

Each module is designed independently and interconnected at the top level, improving
readability and maintainability of the design.

3.8 Design Considerations

Key design considerations include:

• Efficient memory usage using on-chip resources

20
 • Modular and scalable architecture

• Ease of verification through simulation

• Compatibility with future real-time extensions

3.9 Summary
This chapter presented the architecture of the FPGA-based image processing system. The
modular design enables efficient pixel-level processing and provides a strong foundation
for extending the system to real-time image and video processing applications. The next
chapter details the implementation of the proposed architecture using Verilog HDL.

21
Chapter 4

Implementation

4.1 Introduction
This chapter presents the implementation details of the proposed FPGA-based image pro-
cessing system. The system is implemented using Verilog Hardware Description Language
(HDL) following the modular architecture described in Chapter 3. The implementation
focuses on offline processing of bitmap images by loading pixel data into FPGA memory,
applying image processing operations, and generating the processed output.

4.2 Design Flow

The implementation follows a structured design flow consisting of the following steps:
• Conversion of bitmap image into hexadecimal format
• Loading image data into FPGA memory
• Pixel-level image processing using Verilog modules
• Writing processed image data to output memory
• Simulation and verification of results

4.3 Image Preprocessing and Data Conversion

Since Verilog HDL does not directly support bitmap file handling, the input image is first
converted into a hexadecimal format using external tools such as MATLAB or Python.
Each pixel intensity value is extracted and stored sequentially in a text file.
This hexadecimal file is later used to initialize the input image memory in the FPGA
design using the Verilog system task $readmemh. This approach simplifies testing and
enables efficient verification during simulation.

4.4 Image Loader Module

The image loader module is responsible for reading pixel values from the hexadecimal file
and storing them in memory. The memory is implemented using registers or block RAM
depending on FPGA resource availability.

22
4.4.1 Memory Initialization
The following Verilog code snippet illustrates the initialization of image memory:
reg [7:0] image_mem [0:IMAGE_SIZE-1];

initial begin
$readmemh("input_image.hex", image_mem);
end
This module provides pixel data to the processing core based on address signals gen-
erated by the control unit.

4.5 Control Unit and Address Generation

The control unit coordinates the entire processing operation. It generates read and write
addresses for memory access and controls the sequence of operations using a finite state
machine (FSM).
The FSM consists of states such as:
• IDLE
• READ PIXEL
• PROCESS PIXEL
• WRITE PIXEL
This structured control flow ensures correct synchronization between memory access
and pixel processing.

4.6 Image Processing Core

The image processing core performs pixel-level operations on the input image. Each pixel
is processed independently, allowing efficient parallel execution.

4.6.1 Image Inversion

Image inversion is implemented by subtracting the pixel value from the maximum inten-
sity level. For an 8-bit grayscale image, the maximum value is 255.
assign pixel_out = 8’d255 - pixel_in;

4.6.2 Brightness Adjustment

Brightness adjustment is achieved by adding or subtracting a constant value to the input
pixel. Saturation logic is included to prevent overflow or underflow.
if (pixel_in + BRIGHTNESS > 255)
pixel_out = 255;
else
pixel_out = pixel_in + BRIGHTNESS;

23
4.6.3 Thresholding
Thresholding converts a grayscale image into a binary image based on a predefined thresh-
old value.

if (pixel_in > THRESHOLD)

pixel_out = 255;
else
pixel_out = 0;

The desired operation is selected using control parameters defined in the design.

4.7 Output Image Memory

The processed pixel values are stored in output memory. This memory mirrors the
structure of the input image memory and stores pixel values sequentially.

reg [7:0] output_mem [0:IMAGE_SIZE-1];

always @(posedge clk) begin

if (write_enable)
output_mem[addr] <= pixel_out;
end

During simulation, the contents of the output memory are written to a file and later
converted back to bitmap format for visualization.

4.8 Top-Level Module Integration

All functional modules are instantiated and connected in the top-level module. This
module integrates the image loader, control unit, processing core, and output memory.

image_loader u1 (...);
controller u2 (...);
image_core u3 (...);
image_writer u4 (...);

The modular design improves scalability and simplifies debugging.

4.9 Simulation and Verification

Functional verification of the system is carried out using simulation tools such as Model-
Sim or Vivado Simulator. Testbenches are written to apply clock signals, reset conditions,
and control parameters.
Waveform analysis confirms correct memory access, pixel processing, and output gen-
eration. The processed images generated during simulation validate the correctness of
the implemented image processing operations.

24
4.10 Summary
This chapter detailed the implementation of the FPGA-based image processing system
using Verilog HDL. The modular approach enables efficient pixel-level processing and sim-
plifies future extensions. The next chapter presents experimental results and performance
analysis of the implemented system.

25
Chapter 5

Results and Output Images

5.1 Introduction
This chapter presents the experimental results obtained from the FPGA-based image
processing system implemented using Verilog HDL. The correctness and effectiveness of
the proposed system are validated through simulation and visual analysis of the processed
output images. The results demonstrate the successful implementation of basic image
processing operations such as image inversion, brightness adjustment, and thresholding.

5.2 Experimental Setup

The experiments were conducted using a simulation-based approach. The input bitmap
image was converted into a hexadecimal format and loaded into the FPGA memory
during simulation. The system was simulated using standard HDL simulation tools such
as ModelSim or Vivado Simulator.
The processed image data stored in the output memory was written to a file and
converted back into bitmap format for visualization and comparison with the original
image.

5.3 Input Image Description

The input image used for experimentation is a grayscale bitmap image with 8-bit pixel
depth. Each pixel intensity ranges from 0 to 255. The image is processed pixel by pixel
using the proposed FPGA architecture.
Figure 5.1 shows the original input image used for testing.

5.4 Image Inversion Results

Image inversion transforms each pixel intensity value by subtracting it from the maximum
intensity level. This operation enhances contrast in certain regions of the image.
Figure 5.2 shows the output image obtained after applying image inversion.
The results confirm that the inversion operation has been correctly implemented in
hardware, as the bright regions of the original image appear dark and vice versa.

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 input_image.png

Figure 5.1: Original input grayscale image

5.5 Brightness Adjustment Results

Brightness adjustment modifies the pixel intensity by adding a predefined constant value.
Saturation logic ensures that pixel values remain within the valid range.
Figure 5.3 shows the output image after brightness enhancement.
The output image demonstrates increased overall intensity, validating the proper func-
tioning of the brightness control logic.

5.6 Thresholding Results

Thresholding converts the grayscale image into a binary image based on a predefined
threshold value. Pixels above the threshold are set to white, while others are set to black.
Figure 5.4 illustrates the thresholded output image.
The resulting binary image clearly highlights object boundaries and confirms the
correct operation of the thresholding module.

5.7 Performance Analysis

The performance of the proposed system is evaluated in terms of correctness, hardware
efficiency, and scalability. Since pixel operations are independent, the system supports
parallel processing, making it suitable for real-time extensions.
Key observations include:

• Correct processing of all pixels without data loss

• Efficient utilization of FPGA resources

• Deterministic processing behavior due to hardware implementation

27
 inversion_output.png

Figure 5.2: Output image after inversion operation

5.8 Discussion
The experimental results demonstrate that FPGA-based image processing using Verilog
HDL is effective for implementing basic image processing operations. The modular design
allows easy extension to more complex operations such as filtering, edge detection, and
real-time video processing.
Compared to software-based implementations, the proposed hardware approach offers
improved predictability and potential performance benefits.

5.9 Summary
This chapter presented the results obtained from the FPGA-based image processing sys-
tem. The output images validate the correctness of the implemented algorithms. The
results confirm that the proposed system provides a reliable and efficient foundation for
further development of real-time and advanced image processing applications.

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 brightness_output.png

Figure 5.3: Output image after brightness adjustment

threshold_output.png

Figure 5.4: Output image after thresholding

29
Chapter 6

Conclusion and Future Scope

6.1 Conclusion
This thesis presented the design and implementation of an FPGA-based image processing
system using Verilog Hardware Description Language (HDL). The primary objective of
the work was to demonstrate the feasibility and effectiveness of implementing basic image
processing operations directly in hardware using an FPGA platform.
The proposed system successfully performs offline processing of bitmap images by con-
verting image data into hexadecimal format, loading it into FPGA memory, and applying
pixel-level operations such as image inversion, brightness adjustment, and thresholding.
The modular architecture and Verilog-based implementation enable efficient parallel pro-
cessing and deterministic operation, which are key advantages of FPGA-based systems.
Simulation results and output image analysis confirm the correctness of the imple-
mented image processing algorithms. The results demonstrate that hardware-based im-
age processing provides predictable performance and serves as a reliable alternative to
software-based approaches, particularly for embedded and real-time applications.
Overall, the work establishes a strong foundation for understanding FPGA-based
image processing and highlights the potential of Verilog HDL in developing efficient and
scalable hardware architectures for digital image processing applications.

6.2 Future Scope

Although the proposed system focuses on offline image processing, several enhancements
can be explored to extend its functionality and applicability. Possible future directions
include:

• Integration of real-time image acquisition by interfacing camera modules with the

FPGA.

• Implementation of video processing pipelines with VGA or HDMI display output.

• Extension of the processing core to support advanced image processing algorithms

such as edge detection, filtering, morphological operations, and feature extraction.

• Optimization of the design for higher image resolutions using external memory
interfaces such as SDRAM or DDR.

30
 • Performance and power analysis on actual FPGA hardware platforms.

• Incorporation of High-Level Synthesis (HLS) or soft-core processors for hybrid

hardware-software image processing solutions.

The proposed architecture is scalable and adaptable, making it suitable for future
research and development in real-time vision systems, embedded imaging, and hardware-
accelerated computer vision applications.

31
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33