Dual-Current Output, Parallel Input, 16-/14-Bit

Multiplying DACs with 4-Quadrant Resistors

Data Sheet AD5547/AD5557
FEATURES FUNCTIONAL BLOCK DIAGRAM
R1A RCOMA VREFA ROFSA
Dual channel
16-bit resolution: AD5547 RFBA

14-bit resolution: AD5557 VDD

DAC A
D0..D15 INPUT DAC A IOUTA
2- or 4-quadrant, 6.8 MHz BW multiplying DAC D0 TO D15
(AD5547)
OR REGISTER REGISTER
D0..D13 RS RS AGNDA
±1 LSB DNL D0 TO D13
(AD5557)
±1 LSB INL AGNDB

Operating supply voltage: 2.7 V to 5.5 V INPUT DAC B

REGISTER DAC B IOUTB
Low noise: 12 nV/√Hz DAC A
REGISTER
RS RS
Low power: IDD = 10 µA max WR DAC B RFBB
0.5 µs settling time A0, A1 ADDR POWER
ROFSB
ON
Built-in RFB facilitates current-to-voltage conversion DECODE
RESET
AD5547/AD5557

04452-013
Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,
DGND RS MSB LDAC R1B RCOMB VREFB
or ±10 V outputs
Figure 1.
2 mA full-scale current ± 20%, with VREF = 10 V
Extended automotive operating temperature range GENERAL DESCRIPTION
−40°C to +125°C
The AD5547/AD5557 are dual precision, 16-/14-bit, multiplying,
Selectable zero-scale/midscale power-on presets
low power, current-output, parallel input, digital-to-analog
Compact 38-lead TSSOP package
converters (DACs). They are designed to operate from single
+5 V supply with ±10 V multiplying references for 4-quadrant
APPLICATIONS outputs with 6.8 MHz bandwidth.
Automatic test equipment The built-in, 4-quadrant resistors facilitate resistance matching
Instrumentation and temperature tracking, which minimize the number of
Digitally controlled calibration components needed for multiquadrant applications. In addition,
Digital waveform generation the feedback resistor (RFB) simplifies the I-to-V conversion with
an external buffer.
The AD5547/AD5557 are available in a compact, 38-lead TSSOP
package and operate at the extended automotive temperature
range of −40°C to +125°C.
VREF
U1
–VREF

C1

R1A RCOMA VREFA ROFSA RFBA

C2
R1 R2 ROFS RFB
IOUTA U2

AD5547/AD5557 16-/14-BIT VOUTA

16/14 DATA DAC A AGNDA
–VREF TO +VREF
POWER-ON
RESET

WR LDAC RS MSB A0, A1

WR
2 (ONE CHANNEL SHOWN ONLY)
04452-002

LDAC
RS
MSB
A0, A1

Figure 2. 16-/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Is Shown)

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2012 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support [Link]
AD5547/AD5557 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 DAC Section................................................................................ 12
Applications ....................................................................................... 1 Digital Section ............................................................................ 13
Functional Block Diagram .............................................................. 1 PCB Layout, Power Supply Bypassing, and Ground
General Description ......................................................................... 1 Connections ................................................................................ 13

Revision History ............................................................................... 2 Applications Information .............................................................. 14

Specifications..................................................................................... 3 Unipolar Mode ........................................................................... 14

Electrical Characteristics ............................................................. 3 Bipolar Mode .............................................................................. 16

Absolute Maximum Ratings ............................................................ 5 Reference Selection .................................................................... 18

ESD Caution .................................................................................. 5 Amplifier Selection .................................................................... 18

Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 20

Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 20

Circuit Operation ........................................................................... 12

REVISION HISTORY
11/12—Rev. C to Rev. D Added Table 12 ............................................................................... 19
Changes to Figure 22 ...................................................................... 15
9/09—Rev. 0 to Rev. A
11/11—Rev. B to Rev. C Changes to Features Section ............................................................1
Added Figure 14; Renumbered Sequentially .............................. 11 Changes to Static Performance, Relative Accuracy,
Grade: AD5547C Parameter, Table 1 ..............................................3
4/10—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 19
Changes to Features Section and General Description Section . 1
Changes to Table 1 ............................................................................ 3 1/04—Revision 0: Initial Version
Deleted Figure 17 and Figure 18; Renumbered Sequentially ... 10
Changes to Figure 15 and Figure 16............................................. 11
Changes to Figure 20 ...................................................................... 14
Added Reference Selection Section, Amplifier Selection Section,
Table 10, and Table 11; Renumbered Sequentially ..................... 18

Rev. D | Page 2 of 20
Data Sheet AD5547/AD5557

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, IOUT = virtual GND, GND = 0 V, VREF = −10 V to +10 V, TA = −40°C to +125°C, unless otherwise noted.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
STATIC PERFORMANCE 1
Resolution N AD5547, 1 LSB = VREF/216 = 153 µV at VREF = 10 V 16 Bits
AD5557, 1 LSB = VREF/214 = 610 µV at VREF = 10 V 14 Bits
Relative Accuracy INL Grade: AD5557C ±1 LSB
Grade: AD5547B ±2 LSB
Grade: AD5547C ±1 LSB
Differential Nonlinearity DNL Monotonic ±1 LSB
Output Leakage Current IOUT Data = zero scale, TA = 25°C 10 nA
Data = zero scale, TA = TA maximum 20 nA
Full-Scale Gain Error GFSE Data = full scale ±1 ±4 mV
Bipolar Mode Gain Error GE Data = full scale ±1 ±4 mV
Bipolar Mode Zero-Scale Error GZSE Data = full scale ±1 ±3 mV
Full-Scale Temperature Coefficient 2 TCVFS 1 ppm/°C
REFERENCE INPUT
VREF Range VREF −18 +18 V
REF Input Resistance REF 4 5 6 kΩ
R1 and R2 Resistance R1 and R2 4 5 6 kΩ
R1-to-R2 Mismatch Δ(R1 to R2) ±0.5 ±1.5 Ω
Feedback and Offset Resistance RFB, ROFS 8 10 12 kΩ
Input Capacitance2 CREF 5 pF
ANALOG OUTPUT
Output Current IOUT Data = full scale 2 mA
Output Capacitance2 COUT Code dependent 200 pF
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage VIL VDD = 5 V 0.8 V
VDD = 3 V 0.4 V
Logic Input High Voltage VIH VDD = 5 V 2.4 V
VDD = 3 V 2.1 V
Input Leakage Current IIL 10 µA
Input Capacitance2 CIL 10 pF
INTERFACE TIMING2, 3 See Figure 3
Data to WR Setup Time tDS VDD = 5 V 20 ns
VDD = 3 V 35 ns
Data to WR Hold Time tDH VDD = 5 V 0 ns
VDD = 3 V 0 ns
WR Pulse Width tWR VDD = 5 V 20 ns
VDD = 3 V 35 ns
LDAC Pulse Width tLDAC VDD = 5 V 20 ns
VDD = 3 V 35 ns
RS Pulse Width tRS VDD = 5 V 20 ns
VDD = 3 V 35 ns
WR to LDAC Delay Time tLWD VDD = 5 V 0 ns
VDD = 3 V 0 ns

Rev. D | Page 3 of 20
AD5547/AD5557 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE 2.7 5.5 V
Positive Supply Current IDD Logic inputs = 0 V 10 μA
Power Dissipation PDISS Logic inputs = 0 V 0.055 mW
Power Supply Sensitivity PSS ∆VDD = ±5% 0.003 %/%
AC CHARACTERISTICS4
Output Voltage Settling Time tS To ±0.1% of full scale, data cycles from zero scale 0.5 μs
to full scale to zero scale
Reference Multiplying BW BW VREF = 100 mV rms, data = full scale 6.8 MHz
DAC Glitch Impulse Q VREF = 0 V, midscale – 1 to midscale −3.5 nV-s
Multiplying Feedthrough Error VOUT/VREF VREF = 100 mV rms, f = 10 kHz −78 dB
Digital Feedthrough QD WR = 1, LDAC toggles at 1 MHz 7 nV-s
Total Harmonic Distortion THD VREF = 5 V p-p, data = full scale, f = 1 kHz −104 dB
Output Noise Density eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz
Analog Crosstalk CAT Signal input at Channel A and measures the −95 dB
output at Channel B, f = 1 kHz
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is
tied to the amplifier output. The +IN pin of the OP97 is grounded, and the IOUT of the DAC is tied to the OP97’s −IN pin. Typical values represent average readings
measured at 25°C.
2
Guaranteed by design; not subject to production testing.
3
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used.

Timing Diagram
tWR

WR

DATA

tDH
tDS
tLWD
LDAC

tLDAC
tRS
04452-018

RS

Figure 3. AD5547/AD5557 Timing Diagram

Rev. D | Page 4 of 20
Data Sheet AD5547/AD5557

ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter Rating Stresses above those listed under Absolute Maximum Ratings
VDD to GND −0.3 V to +8 V may cause permanent damage to the device. This is a stress
RFB, ROFS, R1, RCOM, and VREF to GND −18 V to +18 V rating only; functional operation of the device at these or any
Logic Inputs to GND −0.3 V to +8 V other conditions above those indicated in the operational
V(IOUT) to GND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute
Input Current to Any Pin except Supplies ±50 mA maximum rating conditions for extended periods may affect
Thermal Resistance (θJA)1 device reliability.
Maximum Junction Temperature (TJ MAX) 150°C
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
ESD CAUTION
Lead Temperature
Vapor Phase, 60 sec 215°C
Infrared, 15 sec 220°C
1
Package power dissipation = (TJ MAX − TA)/θJA.

Rev. D | Page 5 of 20
AD5547/AD5557 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D1 1 38 D2
D0 2 37 D3
ROFSA 3 36 D4
RFBA 4 35 D5
R1A 5 34 D6
RCOMA 6 33 D7
VREFA 7 32 D8
IOUTA 8 31 D9
AGNDA 9 AD5547 30 D10
DGND 10 TOP VIEW 29 VDD
(Not to Scale) 28 D11
AGNDA 11
IOUTB 12 27 D12
VREFB 13 26 D13
RCOMB 14 25 D14
R1B 15 24 D15
RFBB 16 23 RS
ROFSB 17 22 MSB
21 LDAC

04452-003
WR 18
A0 19 20 A1

Figure 4. AD5547 Pin Configuration

Table 3. AD5547 Pin Function Descriptions

Pin No. Mnemonic Function
1, 2, 24 to D0 to D15 Digital Input Data Bits D0 to D15. Signal level must be ≤ VDD + 0.3 V.
28, 30 to
38
3 ROFSA Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA
ties to R1A and the external reference.
4 RFBA Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion.
5 R1A 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do
not connect when operating in unipolar mode.
6 RCOMA Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the associated VREFA pin. Do not connect if
operating in unipolar mode.
7 VREFA DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the
reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external
reference amplifier.
8 IOUTA DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output.
9 AGNDA DAC A Analog Ground.
10 DGND Digital Ground.
11 AGNDB DAC B Analog Ground.
12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output.
13 VREFB DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured
with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF.
14 RCOMB Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREFB pin. Do not connect if operating in
unipolar mode.
15 R1B 4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not
connect if operating in unipolar mode.
16 RFBB Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion.
17 ROFSB Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB
ties to R1B and an external reference.
18 WR Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge.
Signal level must be ≤VDD + 0.3 V.

Rev. D | Page 6 of 20
Data Sheet AD5547/AD5557
Pin No. Mnemonic Function
19 A0 Address Pin 0. Signal level must be ≤VDD + 0.3 V.
20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V.
21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be ≤VDD + 0.3 V.
23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.
Signal level must be ≤VDD + 0.3 V.
29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Rev. D | Page 7 of 20
AD5547/AD5557 Data Sheet
NC 1 38 D0
NC 2 37 D1
ROFSA 3 36 D2
RFBA 4 35 D3
R1A 5 34 D4
RCOMA 6 33 D5
VREFA 7 32 D6
IOUTA 8 31 D7
AGNDA 9 AD5557 30 D8
DGND 10 TOP VIEW 29 VDD
(Not to Scale) 28 D9
AGNDB 11
IOUTB 12 27 D10
VREFB 13 26 D11
RCOMB 14 25 D12
R1B 15 24 D13
RFBB 16 23 RS
ROFSB 17 22 MSB
WR 18 21 LDAC

04452-004
A0 19 20 A1

NC = NO CONNECT

Figure 5. AD5557 Pin Configuration

Table 4. AD5557 Pin Function Descriptions

Pin No. Mnemonic Function
1, 2 NC No Connection. Do not connect anything other than the dummy pads to these pins.
3 ROFSA Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA
ties to R1A and the external reference.
4 RFBA Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion.
5 R1A 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do
not connect when operating in unipolar mode.
6 RCOMA Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the VREFA pin. Do not connect if operating
in unipolar mode.
7 VREFA DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the
reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external
reference amplifier.
8 IOUTA DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage
output.
9 AGNDA DAC A Analog Ground.
10 DGND Digital Ground.
11 AGNDB DAC B Analog Ground.
12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output.
13 VREFB DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured
with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF.
14 RCOMB Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREFB pin. Do not connect if operating
in unipolar mode.
15 R1B 4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do
not connect if operating in unipolar mode.
16 RFBB Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion.
17 ROFSB Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB
ties to R1B and an external reference.
18 WR Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge.
Signal level must be ≤VDD + 0.3 V.
19 A0 Address Pin 0. Signal level must be ≤VDD + 0.3 V.
20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V.
21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be ≤VDD + 0.3 V.
Rev. D | Page 8 of 20
Data Sheet AD5547/AD5557
Pin No. Mnemonic Function
23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.
Signal level must be ≤VDD + 0.3 V.
24 to 28, D13 to D0 Digital Input Data Bits D13 to D0. Signal level must be ≤VDD + 0.3 V.
30 to 38
29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Table 5. Address Decoder Pins

A1 A0 Output Update
0 0 DAC A
0 1 None
1 0 DAC A and DAC B
1 1 DAC B

Table 6. Control Inputs

RS WR LDAC Register Operation
0 X X Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1.
1 0 0 Load the input register with data bits.
1 1 1 Load the DAC register with the contents of the input register.
1 0 1 The input and DAC registers are transparent.
1 When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register
on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse.
1 1 0 No register operation.

Rev. D | Page 9 of 20
AD5547/AD5557 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 1.0

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

DNL (LSB)
INL (LSB)

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

04452-010
–1.0 –1.0

04452-019
0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE (Decimal) CODE (Decimal)

Figure 6. AD5547 Integral Nonlinearity Error Figure 9. AD5557 Differential Nonlinearity Error

1.0 1.5
VREF = 2.5V
0.8 TA = 25°C
1.0
0.6 LINEARITY ERROR (LSB)

0.4
0.5
0.2
DNL (LSB)

INL

0 0
DNL
–0.2
–0.5
–0.4

–0.6
–1.0
GE
–0.8

–1.0 –1.5

04452-022
04452-020

0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 2 4 6 8 10

CODE (Decimal) SUPPLY VOLTAGE VDD (V)

Figure 7. AD5547 Differential Nonlinearity Error Figure 10. Linearity Error vs. Supply Voltage, VDD

1.0 5
VDD = 5V
0.8 TA = 25°C
0.6 4
SUPPLY CURRENT IDD (LSB)

0.4

0.2 3
INL (LSB)

–0.2 2

–0.4

–0.6 1

–0.8

–1.0 0
04452-021

04452-023

0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CODE (Decimal) LOGIC INPUT VOLTAGE VIH (V)

Figure 8. AD5557 Integral Nonlinearity Error Figure 11. Supply Current vs. Logic Input Voltage

Rev. D | Page 10 of 20
Data Sheet AD5547/AD5557
3.0

2.5 LDAC
1
SUPPLY CURRENT (mA)

2.0
0x5555

1.5 2

0x8000
1.0
0xFFFF
0x0000 VOUT
0.5

04452-025
CH1 5.00V CH2 2.00V M 200ns A CH1 2.70V
B CH1 –6.20V
400.00ns
0

04452-024
10k 100k 1M 10M 100M
CLOCK FREQUENCY (Hz)

Figure 12. AD5547 Supply Current vs. Clock Frequency Figure 15. Settling Time from Full Scale to Zero Scale

90 –3.85

VDD = 5V ± 10%
80
VREF = 10V –3.90

70
–3.95
60
PSRR (–dB)

VOUT (V) –4.00

50

40 –4.05

30
–4.10
20
–4.15
10
04452-014

04452-0016
0 –4.20
10 100 1k 10k 100k 1M –20 –10 0 10 20 30 40
FREQUENCY (Hz) TIME (ns)
Figure 13. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 16. AD5547 Midscale Transition and Digital Feedthrough

20 2

0 0

–20 –2
POWER SPECTRUM (dB)

–4
–40
–6
GSIN (dB)

–60
–8
–80
–10
–100
–12
–120
–14
–140 –16

–160 –18
04452-114

04452-017

0 5 10 15 20 25 10k 100k 1M 10M 100M

FREQUENCY (kHz) FREQUENCY (Hz)
Figure 14. AD5547/AD5557 Analog Total Harmonic Distortion (THD) Figure 17. AD5547 Unipolar Reference Multiplying Bandwidth

Rev. D | Page 11 of 20
AD5547/AD5557 Data Sheet

CIRCUIT OPERATION
DAC SECTION The reference voltage inputs exhibit a constant input resistance
of 5 kΩ ± 20%. The impedance of IOUT, the DAC output, is code
The AD5547/AD5557 are 16-/14-bit, multiplying, current- dependent. External amplifier choice should take into account
output, parallel input DACs. The devices operate from a single the variation of the AD5547/AD5557 output impedance. The
2.7 V to 5.5 V supply and provide both unipolar (0 V to –VREF feedback resistance in parallel with the DAC ladder resistance
or 0 V to +VREF) and bipolar (±VREF) output ranges from –18 V dominates output voltage noise. To maintain good analog
to +18 V references. In addition to the precision conversion RFB performance, it is recommended that the power supply is
commonly found in current output DACs, there are three addi- bypassed with a 0.01 µF to 0.1 µF ceramic or chip capacitor in
tional precision resistors for 4-quadrant bipolar applications. parallel with a 1 µF tantalum capacitor. Also, to minimize gain
The AD5547/AD5557 consist of two groups of precision R-2R error, PCB metal traces between VREF and RFB should match.
ladders, which make up the 12/10 LSBs, respectively. Furthermore, Every code change of the DAC corresponds to a step function;
the 4 MSBs are decoded into 15 segments of resistor value 2R. gain peaking at each output step may occur if the op amp has
Figure 18 shows the architecture of the 16-bit AD5547. Each of limited GBP and excessive parasitic capacitance present at the
the 16 segments and the R-2R ladder carries an equally weighted inverting node of the op amp. A compensation capacitor, therefore,
current of one-sixteenth of full scale. The feedback resistor RFB may be needed between the I-to-V op amp inverting and output
and 4-quadrant resistor ROFS have values of 10 kΩ. Each 4-quadrant nodes to smooth the step transition. Such a compensation capacitor
resistor, R1 and R2, equals 5 kΩ. In 4-quadrant operation, R1, should be found empirically, but a 20 pF capacitor is generally
R2, and an external op amp work together to invert the reference adequate for the compensation.
voltage and apply it to the VREF input. With ROFS and RFB
connected as shown in Figure 2, the output can swing from The VDD power is used primarily by the internal logic to drive
−VREF to +VREF. the DAC switches. Note that the output precision degrades if
the operating voltage falls below the specified voltage. Users
should also avoid using switching regulators because device
power supply rejection degrades at higher frequencies.

VREF
R2 2R 2R 2R 2R
5kΩ 80kΩ 80kΩ 80kΩ 80kΩ
RCOM
R1 4 MSB
5kΩ 15 SEGMENTS
R1
R R R R R R R R
40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ

2R 2R 2R 2R 2R 2R 2R 2R 2R
80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ

8-BIT R2R

ROFS
RA R R R R
RFB
2R 2R 2R 2R 2R
RB 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 10kΩ 10kΩ
4-BIT R2R

IOUT
AGND
15 8 4

ADDRESS DECODER

LDAC LDAC DAC REGISTER RS RS

WR WR INPUT REGISTER RS
04452-011

D15 D14 D0

Figure 18. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown

Rev. D | Page 12 of 20
Data Sheet AD5547/AD5557
DIGITAL SECTION The voltage reference temperature coefficient (TC) and long-
The AD5547/AD5557 have 16-/14-bit parallel inputs. The devices term drift are primary considerations. For example, a 5 V
are double buffered with 16-/14-bit registers. The double buffered reference with a TC of 5 ppm/°C means the output changes by
feature allows the simultaneous update of several AD5547s/ 25 µV/°C. As a result, a reference operating at 55°C contributes
AD5557s. For the AD5547, the input register is loaded directly an additional 750 µV full-scale error.
from a 16-bit controller bus when WR is brought low. The DAC Similarly, the same 5 V reference with a ±50 ppm long-term
register is updated with data from the input register when LDAC drift means the output may change by ±250 µV over time.
is brought high. Updating the DAC register updates the DAC Therefore, it is practical to calibrate a system periodically to
output with the new data (see Figure 18). To make both registers maintain its optimum precision.
transparent, tie WR low and LDAC high. The asynchronous RS PCB LAYOUT, POWER SUPPLY BYPASSING, AND
pin resets the part to zero scale if MSB = 0 and to midscale if GROUND CONNECTIONS
MSB = 1.
It is a good practice to employ a compact, minimum lead length,
ESD Protection Circuits PCB layout design. The leads to the input should be as short as
All logic input pins contain back-biased ESD protection Zeners possible to minimize IR drop and stray inductance.
connected to ground (DGND) and VDD, as shown in Figure 19. The PCB metal traces between VREF and RFB should also be
As a result, the voltage level of the logic input should not be matched to minimize gain error.
greater than the supply voltage.
It is also essential to bypass the power supply with quality
VDD
capacitors for optimum stability. Supply leads to the device
DIGITAL should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic
INPUTS
5kΩ
capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
04452-026

DGND
To minimize the digital ground bounce, the AD5547/AD5557
Figure 19. Equivalent ESD Protection Circuits
DGND terminal should be joined with the AGND terminal at
Amplifier Selection a single point. Figure 20 illustrates the basic supply bypassing
In addition to offset voltage, the bias current is important in configuration and AGND/DGND connection for the
op amp selection for precision current output DACs. A 30 nA AD5547/AD5557.
input bias current in the op amp contributes to 1 LSB in the
full-scale error of the AD5547. The OP1177 and AD8628 op + C2
VDD
C1
amps are good candidates for the I-to-V conversion. 5V AD5547/AD5557
– 1µF 0.1µF
Reference Selection AGND

The initial accuracy and rated output of the voltage reference

determine the full-span adjustment. The initial accuracy of DGND
the reference is usually a secondary concern because it can be
04452-015

trimmed. Figure 25 shows an example of a trimming circuit.

The zero-scale error can also be minimized by standard op amp Figure 20. Power Supply Bypassing
nulling techniques.

Rev. D | Page 13 of 20
AD5547/AD5557 Data Sheet

APPLICATIONS INFORMATION
UNIPOLAR MODE In this case, the output voltage polarity is opposite the VREF
2-Quadrant Multiplying Mode, VOUT = 0 V to –VREF polarity (see Figure 21). Table 7 shows the negative output vs.
code for the AD5547.
The AD5547/AD5557 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op Table 7. AD5547 Unipolar Mode Negative Output vs. Code
amp to convert the unipolar mode of the output voltage to D in Binary VOUT (V)
VOUT = −VREF × D/65,536 (AD5547) (1) 1111 1111 1111 1111 –VREF (65,535/65,536)
1000 0000 0000 0000 –VREF/2
VOUT = −VREF × D/16,384 (AD5557) (2)
0000 0000 0000 0001 –VREF (1/65,536)
where D is the decimal equivalent of the input code. 0000 0000 0000 0000 0

+5V 2
C1 C2 U3 ADR03
1µF 0.1µF VIN
5
TRIM
6
VOUT +2.5V
GND
VREFA
4
R1A RCOMA ROFSA RFBA
C6 6.8pF
VDD R1 R2 ROFS RFB
C3
0.1µF 2.5V IOUTA
AD5547/AD5557 +V VOUTA
16-/14-BIT AD8628
AGNDA
U1 –V –2.5V TO 0V
16/14 DATA
C4
WR LDAC RS MSB A0, A1
0.1µF
WR C5
LDAC 2
RS 1µF

04452-007
MSB –5V
A0, A1

Figure 21. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to –VREF

Rev. D | Page 14 of 20
Data Sheet AD5547/AD5557
2-Quadrant Multiplying Mode, VOUT = 0 V to +VREF Table 8 shows the positive output vs. code for the AD5547.
The AD5547/AD5557 are designed to operate with either Table 8. AD5547 Unipolar Mode Positive Output vs. Code
positive or negative reference voltages. As a result, a positive
D in Binary VOUT (V)
output can be achieved with an additional op amp, (see
1111 1111 1111 1111 +VREF(65,535/65,536)
Figure 22); the output becomes
1000 0000 0000 0000 +VREF/2
VOUT = +VREF × D/65,536 (AD5547) (3) 0000 0000 0000 0001 +VREF(1/65,536)
VOUT = +VREF × D/16,384 (AD5557) (4) 0000 0000 0000 0000 0

U2

AD8628
+5V 2
C1 C2 U3 C8
0.1µF
1µF 1µF VIN 5
TRIM
6
VOUT C9
GND 1µF
–5V
4 ADR03 C7 –2.5V

+2.5V +5V
C4 1µF
R1A RCOMA VREFA ROFSA RFBA
C6 C5 0.1µF
VDD U2B
R1 R2 ROFS RFB
C3
0.1µF IOUTA
16-/14-BIT +V
AD8628 VOUTA
AD5547/AD5557 AGNDA
–V
16/14 DATA
0V TO +2.5V
WR LDAC RS MSB A0, A1

WR
LDAC 2

04452-005
RS
MSB
A0, A1

Figure 22. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to +VREF

Rev. D | Page 15 of 20
AD5547/AD5557 Data Sheet
BIPOLAR MODE
4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF Table 9 shows some of the results for the 16-bit AD5547.
The AD5547/AD5557 contain on-chip all the 4-quadrant Table 9. AD5547 Output vs. Code
resistors necessary for precision bipolar multiplying operation.
D in Binary VOUT
Such a feature minimizes the number of exponent components
1111 1111 1111 1111 +VREF (32,767/32,768)
to only a voltage reference, dual op amp, and compensation
1000 0000 0000 0001 +VREF (1/32,768)
capacitor (see Figure 23). For example, with a +10 V reference,
1000 0000 0000 0000 0
the circuit yields a precision, bipolar –10 V to +10 V output.
0111 1111 1111 1111 –VREF (1/32,768)
VOUT = (D/32768 − 1) × VREF (AD5547) (5) 0000 0000 0000 0000 –VREF
VOUT = (D/16384 − 1) × VREF (AD5557) (6)

+15V 2

C1 C2 U3
1µF 0.1µF VIN 5
TRIM
6
VOUT
GND
U2A
4 ADR01

AD8512

C8
–10V +10V

R1A RCOMA VREFA ROFSA RFBA

+5V
VDD ROFS RFB +15V C4 1µF
R1 R2
C9
C5 0.1µF
U2B
C3
0.1µF IOUTA
AD5547/AD5557 16-/14-BIT +V VOUT
DAC A
AD8512
U1 –V
16/14 DATA AGNDA
C6 0.1µF –10V TO +10V

WR LDAC RS MSB A0, A1 C7 1µF

WR
LDAC 2 –15V
RS
04452-006

MSB
A0, A1

Figure 23. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF

Rev. D | Page 16 of 20
Data Sheet AD5547/AD5557
AC Reference Signal Attenuator System Calibration
Besides handling the digital waveform decoded from the The initial accuracy of the system can be adjusted by trimming
parallel input data, the AD5547/AD5557 can also handle low the voltage reference ADR0x with a digital potentiometer (see
frequency ac reference signals for signal attenuation, channel Figure 25). The AD5170 provides a one-time programmable
equalization, and waveform generation applications. The (OTP), 8-bit adjustment that is ideal and reliable for such
maximum signal range can be up to ±18 V (see Figure 24). calibration. Analog Devices, Inc., OTP digital potentiometer
comes with programmable software that simplifies factory
calibration.

U2A

OP2177

+10V C7

–10V +15V
C4 1µF
R1A RCOMA VREFA ROFSA RFBA
+5V C6
C5 0.1µF
VDD R1 R2 ROFS RFB U2B
C1 C2
1µF 0.1µF IOUTA
AD5547/AD5557 16-/14-BIT +V VOUTA
OP2177
AGNDA
U1 –V
16/14 DATA
WR LDAC RS MSB A0, A1 C8 1µF

WR C9 0.1µF
LDAC 2

04452-008
RS
MSB –15V
A0, A1

Figure 24. Signal Attenuator with AC Reference

+5V 2 AD5170
C1 C2 U3
1µF 0.1µF U4
VIN R3
5
TRIM 10kΩ
470kΩ B
VOUT U2
6
GND R7 1kΩ

4 ADR03 AD8628

C7 –2.5V
+2.5V
+5V
C4 1µF
R1A RCOMA VREFA ROFSA RFBA
C6
U2B C5 0.1µF
VDD R1 R2 ROFS RFB
C3
0.1µF IOUTA
AD5547/AD5557 16-/14-BIT +V VOUTA
AGNDA AD8628
U1 –V 0V TO +2.5V
16/14 DATA
WR LDAC RS MSB A0, A1

WR
LDAC 2
REF 01/AD RS
04452-009

MSB
A0, A1

Figure 25. Full-Span Calibration

Rev. D | Page 17 of 20
AD5547/AD5557 Data Sheet
REFERENCE SELECTION The input bias current of an op amp also generates an offset at
When selecting a reference for use with the AD55xx series of the voltage output because of the bias current flowing in the
current output DACs, pay attention to the output voltage, feedback resistor, RFB.
temperature coefficient specification of the reference. Choosing Common-mode rejection of the op amp is important in voltage-
a precision reference with a low output temperature coefficient switching circuits because it produces a code-dependent error
minimizes error sources. Table 10 lists some of the references at the voltage output of the circuit.
available from Analog Devices, Inc., that are suitable for use Provided that the DAC switches are driven from true wideband
with this range of current output DACs. low impedance sources (VIN and AGND), they settle quickly.
AMPLIFIER SELECTION Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
The primary requirement for the current-steering mode is an
minimum settling time in this configuration, minimize capacitance
amplifier with low input bias currents and low input offset voltage.
at the VREF node (the voltage output node in this application) of
Because of the code-dependent output resistance of the DAC,
the DAC. This is done by using low input capacitance buffer
the input offset voltage of an op amp is multiplied by the variable
amplifiers and careful board design.
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output Analog Devices offers a wide range of amplifiers for both precision
voltage due to the amplifier’s input offset voltage. This output dc and ac applications, as listed in Table 11 and Table 12.
voltage change is superimposed upon the desired change in output
between the two codes and gives rise to a differential linearity error,
which, if large enough, can cause the DAC to be nonmonotonic.

Table 10. Suitable Analog Devices Precision References

Maximum Temperature
Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) ISS (mA) Output Noise (µV p-p) Package(s)
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-5, SC70-5
ADR02 5.0 0.06 3 1 10 SOIC-8
ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5
ADR03 2.5 0.1 3 1 6 SOIC-8
ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5
ADR06 3.0 0.1 3 1 10 SOIC-8
ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5
ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8
ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8
ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8
ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8
ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8
ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8
ADR391 2.5 0.16 9 0.12 5 TSOT-5
ADR395 5.0 0.10 9 0.12 8 TSOT-5

Table 11. Suitable Analog Devices Precision Op Amps

VOS Maximum IB Maximum 0.1 Hz to 10 Hz
Part No. Supply Voltage (V) (µV) (nA) Noise (µV p-p) Supply Current (µA) Package(s)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8
AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8
AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8
ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5
AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5
AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8
AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5
AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5
AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8

Rev. D | Page 18 of 20
Data Sheet AD5547/AD5557
Table 12. Suitable Analog Devices High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) VOS (Max) (µV) IB (Max) (nA) Package(s)
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5
AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8
AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8
AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8
AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8
AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8
AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8
AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8

Table 13 lists the latest DACS available from Analog Devices.

Table 13. ADI Current Output DACs

Model Bits Outputs Interface Package Comments
AD5425 8 1 SPI, 8-Bit Load MSOP-10 Fast 8-bit load; see also AD5426
AD5426 8 1 SPI MSOP-10 See also AD5425 fast load
AD5450 8 1 SPI TSOT-8 See also AD5425 fast load
AD5424 8 1 Parallel TSSOP-16
AD5429 8 2 SPI TSSOP-16
AD5428 8 2 Parallel TSSOP-20
AD5432 10 1 SPI MSOP-10
AD5451 10 1 SPI TSOT-8
AD5433 10 1 Parallel TSSOP-20
AD5439 10 2 SPI TSSOP-16
AD5440 10 2 Parallel TSSOP-24
AD5443 12 1 SPI MSOP-10 See also AD5452 and AD5444
AD5452 12 1 SPI TSOT-8 Higher accuracy version of AD5443; see also AD5444
AD5445 12 1 Parallel TSSOP-20
AD5444 12 1 SPI MSOP-10 Higher accuracy version of AD5443; see also AD5452
AD5449 12 2 SPI TSSOP-16
AD5415 12 2 SPI TSSOP-24 Uncommitted resistors
AD5447 12 2 Parallel TSSOP-24
AD5405 12 2 Parallel LFCSP-40 Uncommitted resistors
AD5453 14 1 SPI TSOT-8
AD5553 14 1 SPI MSOP-8
AD5556 14 1 Parallel TSSOP-28
AD5446 14 1 SPI MSOP-10 MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426
AD5555 14 2 SPI TSSOP-16
AD5557 14 2 Parallel TSSOP-38
AD5543 16 1 SPI MSOP-8
AD5546 16 1 Parallel TSSOP-28
AD5545 16 2 SPI TSSOP-16
AD5547 16 2 Parallel TSSOP-38

Rev. D | Page 19 of 20
AD5547/AD5557 Data Sheet

OUTLINE DIMENSIONS
9.80
9.70
9.60

38 20

4.50
4.40
4.30
6.40 BSC
1 19

PIN 1
1.20
MAX
0.15
0.05
8°
0.50 0.27 0° 0.70
COPLANARITY BSC SEATING 0.20
0.17 PLANE 0.60
0.10 0.09
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-BD-1

Figure 26. 38-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-38)
Dimension s shown in millimeters

ORDERING GUIDE
DNL INL Package Ordering
Model 1 Resolution (Bits) (LSB) (LSB) Temperature Range Package Description Option Quantity
AD5547BRU 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 50
AD5547BRU-REEL7 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 1,000
AD5547BRUZ 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 50
AD5547CRUZ 16 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50
AD5547CRUZ-REEL7 16 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 1,000
AD5557CRU 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50
AD5557CRU-REEL7 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 1,000
AD5557CRUZ 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50
1
Z = RoHS Compliant Part.

©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04452-0-11/12(D)

Rev. D | Page 20 of 20