Cambridge Alevel
Candidate
ame
Student
S 9618
e 2024 2025
4
AS Level
INSTRUCTIONS
● Scan the Assignment using A e or e or attem t the assignment ll using i ad
or simi ar e ui ment
● ocument to be submitted ia
● rite our e and e in the bo es at the to o the age.
● Ans er ll uestions.
● se a b ac or dar b ue en. ou ma use an enci or an diagrams or gra hs.
● rite our ans er to each uestion in the s ace ro ided.
● ou ma use a ca cu ator.
● ou shou d sho a our or ing and use a ro riate units.
INFORMATION
● The total mark for this paper is 62.
● The number of marks for each question or part question is shown in brackets [ ].
[Turn over
1
1 A computer system is designed using the basic Von Neumann model.
Registers and buses are components in the Von Neumann model.
(a) (i) Identify three other components in the Von Neumann model of a computer system.
Do not include registers or buses in your answers.
1 ........................................................................................................................................
2 ........................................................................................................................................
3 ........................................................................................................................................
[3]
(ii) Identify two differences between special purpose registers and general purpose
registers.
1 ........................................................................................................................................
...........................................................................................................................................
2 ........................................................................................................................................
...........................................................................................................................................
[2]
2
(b) The following incomplete table contains steps of the Fetch-Execute (F-E) cycle and their
descriptions.
Complete the table by writing the missing steps using register transfer notation and the
missing descriptions.
Step Description
............................................................................. The address in PC is incremented.
.............................................................................
MDR [[MAR]]
.............................................................................
.............................................................................
.............................................................................
MAR [PC]
.............................................................................
.............................................................................
............................................................................. The contents of MDR are copied into CIR.
[4]
3
(d) The following statements describe the stages that the CPU performs when an interrupt is
detected.
There are three missing statements.
Write the letter of the missing statements from the table in the correct place to complete the
description.
1 At the end of each Fetch-Execute (F-E) cycle, the processor checks if an interrupt flag is
set.
2 ......................................................
3 If the interrupt priority is high enough, the processor saves the current contents of the
registers.
4 ......................................................
5 When servicing of the interrupt is complete, the processor restores the registers.
6 ......................................................
Letter Stage
The address of the Interrupt Service (ISR) handling routine is loaded into the
A
Program Counter (PC).
B Lower priority interrupts are re-enabled.
C The device causing the interrupt transfers data to the CPU.
The processor identifies the source of the interrupt and checks the priority of
D
the interrupt.
E The ISR is incremented.
[3]
4
The Central Processing Unit (CPU) of the basic Von Neumann model for a computer system
contains several special purpose registers.
(b) Describe what is meant by the Immediate Access Store (IAS) in a computer system.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
............................................................................................................................................. [2]
5
(c) A computer has a single 2.1 GHz CPU.
(i) Describe how increasing the clock speed to 4 GHz can increase the performance of the
computer.
...........................................................................................................................................
...........................................................................................................................................
..................................................................................................................................... [1]
(ii) A second computer has a CPU with two 2.1 GHz cores.
Explain why the second computer does not always run twice as fast as the computer
with one 2.1 GHz CPU.
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..................................................................................................................................... [4]
6
(a) Identify the purpose of the first pass of a two-pass assembler.
...................................................................................................................................................
............................................................................................................................................. [1]
(b) The following table shows part of the instruction set for a processor. The processor has two
registers, the Accumulator (ACC) and the Index Register (IX).
Instruction
Explanation
Opcode Operand
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare the contents of ACC with number n
JPE <address> Following a compare instruction, jump to <address> if the compare was True
OUT Output to the screen the character whose ASCII value is stored in ACC
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
(i) Give one example of an instruction that belongs to each of the following instruction
groups.
Only use the instructions given in the table. Each instruction must have a suitable
operand.
Data movement .................................................................................................................
Arithmetic operation ..........................................................................................................
Conditional instruction .......................................................................................................
[3]
(ii) The instruction LDR #2 uses immediate addressing.
Give one similarity and one difference between direct addressing and indexed addressing.
Similarity ............................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
Difference ..........................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
[2]
7
(iii) Identify one other mode of addressing.
...........................................................................................................................................
..................................................................................................................................... [1]
(c) The following table shows another part of the instruction set for the same processor.
Instruction
Explanation
Opcode Operand
AND Bn Bitwise AND operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the operand
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
(i) The current contents of the ACC are:
0 1 0 0 1 1 1 1
Show the contents of the ACC after the execution of the following instruction.
AND B10100101
...........................................................................................................................................
...........................................................................................................................................
[1]
(ii) The current contents of the ACC are:
0 0 0 1 0 1 1 1
Show the contents of the ACC after the execution of the following instruction.
LSR #3
...........................................................................................................................................
...........................................................................................................................................
[1]
8
(iii) The current contents of the ACC are:
1 1 1 1 0 1 1 1
Show the contents of the ACC after the execution of the following instruction.
XOR B00100101
...........................................................................................................................................
...........................................................................................................................................
[1]
9
(b) The computer has a Control Unit (CU), system clock and control bus.
Explain how the CU, system clock and control bus operate to transfer data between the
components of the computer system.
...................................................................................................................................................
...................................................................................................................................................
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............................................................................................................................................. [4]
10
5 A program is written in assembly language.
(a) The program is converted into machine code by a two‑pass assembler.
Draw one or more lines to identify the pass or passes in which each action takes place.
Action Pass
generates object code
first
reads the source code one line at a time
removes white space
second
adds labels to the symbol table
[3]
(b) Assembly language statements can use different modes of addressing.
Complete the following description of addressing modes.
............................................ addressing is when the operand holds the memory address of
the data.
............................................ addressing is when the operand holds a memory address that
stores the memory address of the data.
............................................ addressing is when the operand is the data.
[3]
11
6 A student has purchased a new laptop.
(a) The laptop is designed using the Von Neumann model for a computer system.
Identify two types of signal that a control bus can transfer.
1 ................................................................................................................................................
2 ................................................................................................................................................
[2]
(b) Describe two ways the hardware of a laptop can be upgraded to improve the performance
and explain how each upgrade improves the performance.
1 ................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
[ ]
12
(c) Peripherals are connected to the laptop using ports.
(i) A printer is connected to a Universal Serial Bus (USB) port.
Describe how data is transmitted through a USB port.
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
..................................................................................................................................... [1]
(ii) A monitor is connected to the laptop using a different type of port.
Identify one other type of port that can be used to connect the monitor.
..................................................................................................................................... [1]
13
(a) A Central Processing Unit (CPU) contains several special purpose registers and other
components.
(ii) State when interrupts are detected during the Fetch-Execute (F-E) cycle.
...........................................................................................................................................
..................................................................................................................................... [1]
(b) A computer system contains a system clock.
Describe the purpose of the system clock.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
............................................................................................................................................. [2]
14
8 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents
of the index register. Copy the contents of this calculated address to
ACC
LDR #n Immediate addressing. Load the number n to IX
MOV <register> Moves the contents of the accumulator to the given register (IX)
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
SUB #n Subtract the denary number n from the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP #n Compare the contents of ACC with number n
CMI <address> Indirect addressing. The address to be used is at the given address.
Compare the contents of ACC with the contents of this second
address
JPE <address> Following a compare instruction, jump to <address> if the compare
was True
JPN <address> Following a compare instruction, jump to <address> if the compare
was False
OUT Output to the screen the character whose ASCII value is stored in
ACC
END Return control to the operating system
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
15
(a) The current contents of main memory and selected values from the ASCII character set are
given.
(i) Trace the program currently in memory using the trace table.
Instruction Memory address
Address Instruction ACC IX Output
address 100 101 110 111 112
75 LDR #0
76 LDD 100
1 0 97 98 97
77 CMP #2
78 JPE 91
79 LDX 110
80 SUB #32
81 CMP #65
82 JPN 86
83 LDM #1
84 ADD 101
85 STO 101
86 LDM #1
87 ADD 100
88 STO 100
89 INC IX
90 JMP 76
91 LDD 101
92 ADD #48
93 OUT
94 END
100 1
101 0
110 97
111 98
112 97
ASCII Character
value
49 1
50 2
51 3
52 4
65 A
66 B
67 C
68 D
[4]
16
(ii) Explain the purpose of relative addressing in an assembly language program.
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
..................................................................................................................................... [2]
(b) The following table shows another part of the instruction set for the processor.
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND Bn Bitwise AND operation of the contents of ACC with the binary number n
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR Bn Bitwise OR operation of the contents of ACC with the binary number n
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
(i) The current contents of the ACC are:
0 0 1 1 0 1 1 0
Show the contents of the ACC after the execution of the following instruction.
AND B01001100
...........................................................................................................................................
...........................................................................................................................................
[1]
17
(ii) The current contents of the ACC are:
1 0 0 1 0 1 0 1
Show the contents of the ACC after the execution of the following instruction.
OR B01001111
...........................................................................................................................................
...........................................................................................................................................
[1]
(iii) The current contents of the ACC are:
1 0 0 1 1 1 0 1
Show the contents of the ACC after the execution of the following instruction.
LSR #2
...........................................................................................................................................
...........................................................................................................................................
[1]
18
(a) State what is meant by the stored program concept in the Von Neumann model of a
computer system.
...................................................................................................................................................
............................................................................................................................................. [1]
(b) A Central Processing Unit (CPU) contains several special purpose registers and other
components.
(i) State the role of the following registers.
Program Counter (PC) ......................................................................................................
...........................................................................................................................................
...........................................................................................................................................
Index Register (IX) ............................................................................................................
...........................................................................................................................................
...........................................................................................................................................
Status Register (SR) .........................................................................................................
...........................................................................................................................................
...........................................................................................................................................
[3]
(ii) Tick () one box in each row to identify the system bus used by each CPU component.
CPU component Data bus Address bus Control bus
System clock
Memory Address Register (MAR)
[1]
19
(c) Describe the purpose of an interrupt in a computer system.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
............................................................................................................................................. [2]
(d) Identify two causes of a software interrupt.
1 ................................................................................................................................................
...................................................................................................................................................
2 ................................................................................................................................................
...................................................................................................................................................
[2]