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Unit 2 Notes

The document outlines the steps involved in a PCI bus transaction, starting from bus idle to the release of the bus. It details the phases including master claiming the bus, address phase, target selection, data phase, and the conditions for data transfer. The process concludes with the end of the transaction and the bus returning to an idle state for potential new requests from other masters.

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5 views2 pages

Unit 2 Notes

The document outlines the steps involved in a PCI bus transaction, starting from bus idle to the release of the bus. It details the phases including master claiming the bus, address phase, target selection, data phase, and the conditions for data transfer. The process concludes with the end of the transaction and the bus returning to an idle state for potential new requests from other masters.

Uploaded by

barveymb
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

PCI Bus Transaction —

1. Bus Idle

 All control signals are de-asserted (FRAME#, IRDY#, TRDY# high)

 No device is using the bus

2. Master claims the bus

 Master wins arbitration

 On the next clock edge, FRAME# is asserted LOW

 This marks the start of a PCI transaction

3. Address Phase

 AD lines carry the address

 C/BE# lines carry the bus command


(e.g., Memory Read / Memory Write)

 Address and command are valid for one clock cycle only

4. Target selection

 Addressed device decodes the address

 Target asserts DEVSEL# LOW


→ “I am the selected device”

5. Data Phase begins

 AD lines now carry DATA-1

 C/BE# lines switch role to Byte Enable

 Master asserts IRDY# LOW when it is ready

 Target asserts TRDY# LOW when it is ready

6. Data transfer condition

Actual data transfer occurs only when:

IRDY# = 0 AND TRDY# = 0

 If either is HIGH → Wait state

 This allows fast and slow devices to coexist

7. Burst data transfer

 Multiple data phases occur:

o DATA-1

o DATA-2

o DATA-3
 Address is not repeated

 One data word transferred per successful clock

8. End of transaction

 Master de-asserts FRAME# HIGH

 Indicates last data phase

 Final data transfer completes

9. Bus release

 IRDY#, TRDY#, DEVSEL# de-assert

 Bus returns to idle state

 Another master may request the bus

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