B M S INSTITUTE OF TECHNOLOGY & MANAGEMENT

AVALAHALLI, YELAHANKA, BENGALURU-560 064

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Subject: Microprocessors and Microcontrollers Subject code: 18CS44

Faculty: Ashwini N Sem: 4th

Module-1
Question 1:

What do you mean by RISC architecture?

Answer:

Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy
based on the insight that a simplified instruction set provides higher performance when combined
with a microprocessor architecture capable of executing those instructions using single and fewer
microprocessor cycles per instruction.
The design complexity of RISC and CISC is shown below:

In RISC the Complexity is resided in compiler where as in CISC it is at the hardware. Hence when
we use RISC hardware change is not required only the changes is at complier and is vice versa for
CISC.
Question 2:

Differentiate CISC and RISC architecture.

Answer

Question 3:

Explain the important design rules of RISC philosophy.

Answer

RISC has four major design rules:

1. Instructions—
• Has a reduced number of instruction classes.

• These classes provide simple operations that can each execute in a single
cycle.
• Complicated instructions are synthesized by combining simpler instructions.
(for example, a divide operation)
• Each instruction has fixed length- For Pipelining concept.
Note: In CISC –variation in length and no. of cycles for execution.
2. Pipelines:

– The processing of instructions is broken down into smaller units that can be
executed in parallel by pipelines.

– Ideally the pipeline advances by one step on each cycle for maximum throughput.

– Instructions can be decoded in one pipeline stage.

Note: In CISC – An instruction is executed by a mini program called microcode.

3. Registers

– RISC machines have a large general-purpose register set.

– Any register can contain either data or an address.

– Registers act as the fast local memory store for all data processing operations.

Note: In CISC – dedicated registers for specific purposes.

4. Load-store architecture:

– The processor operates on data held in registers.

– Separate load and store instructions transfer data between the register bank and
external memory.

– As memory accesses are costly, they perform operations only on register data.

Note: In CISC – data processing operations can act on memory directly.

Question 4:

Which are the different features of ARM instruction set that make it suitable for
embedded applications.

Answer
• Physical features of ARM processor design:
1. Power: The ARM processor has been specifically designed to be small to reduce
power consumption and extend battery operation
 This is essential for applications such as mobile phones and personal digital
assistants (PDAs).
 2. High Code Density: since embedded systems have limited memory
 Due to cost and/or physical size restrictions.
3. Price sensitive :
 As it uses slow and low-cost memory devices.
4. Reduce the area of the die :
 For a single-chip solution, the smaller the area used by the embedded
processor, the more available space for specialized peripherals.
 This in turn reduces the cost.
5. Debug technology within the processor:
 So the software engineers can view what is happening while the processor is
executing code. With greater visibility.
 Software engineers can resolve issues faster
 Hence reduces development costs.

Question 5:

With a neat diagram explain the different hardware components of an embedded

device based on ARM core.

Answer

• The device into four main hardware components:

– ARM processor
– Controllers
 – Peripherals
– Bus
1. ARM Processor :
– An ARM processor comprises a core (the execution engine that processes
instructions and manipulates data)
– It is surrounded with components that interface it with a bus.
– These components can include memory management and caches.
2. Controllers:
– Controllers are specialized peripherals that implement higher level of functionality
within an embedded system.
– 2 Controllers:
• Interrupt controllers-Deals with interrupts operations.
• Memory controllers-Deals with memory operations.
3. Peripherals:
– Required for input-output operation external to the chip
– Embedded system that interact with the outside world need some form of peripheral
device.
– Peripherals range from a simple serial communication device to a more
complex 802.11 wireless device.
– All ARM peripherals are memory mapped – the programming interface is a set of
memory addressed register.
–
4. A bus :
– Used to communicate between different parts of the device
– Embedded systems use different bus technologies than those designed for x86 PC.
Embedded device use an on-chip bus
– Core is master who initiates a data transfer.
– A Bus has two architecture levels
– The First is a physical level that covers the electrical characteristics and bus
width (16, 32, or 64 bits).
– The Second level deals with protocol.– the logical rules governing the
communication between processor and peripheral.
– ARM seldom implements the electrical characteristics of the bus, but it routinely
specifies the bus protocol.

Question 6:

Explain the AMBA bus protocol.

Answer
• Embedded systems use different bus technologies than those designed for x86 PC.
– Embedded device use an on-chip bus
– Core is master who initiates a data transfer.
• A Bus has two architecture levels
 – The First is a physical level that covers the electrical characteristics and bus width
(16, 32, or 64 bits).
– The Second level deals with protocol.– the logical rules governing the
communication between processor and peripheral.
• ARM seldom implements the electrical characteristics of the bus, but it routinely specifies
the bus protocol.
• AMBA: Advanced Micro controller Bus Architecture
– 1996, it’s introduced and widely adopted as the on-chip bus architecture for ARM
processors.
– The first AMBA buses introduced were
• ASB : ARM System Bus, and
• APB : ARM Peripheral Bus
– Later, ARM introduced another bus design
• AHB: ARM High-performance Bus
• Using AMBA,
– Peripheral designers can reuse the same design on multiple projects (with different
processor architecture).
– Plug-and-play
• AHB
– provides higher data throughput than ASB.
• Because it use a Centralized Multiplexed Bus Scheme (rather than ASB’s
bi-direction bus).
• This change allows the AHB bus to run at higher clock speed.
• 64/128 bits width.
–
– Two variations on the AHB bus
• Multi-layer AHB, and
• allows multiple active bus masters,
• AHB-Lite: only one master

Question 7:

Give a detailed account of different types of memories that can be used in embedded
systems based on the hierarchy, width and speed.

Answer
• Memory is necessary

– An embedded system has to have some form of memory to store and execute code.

• You have to consider

– price, performance, and power consumption

• Specific memory characteristics are:

– Hierarchy

– Width

– Type

1. Memory(Hierarchy):
 Cache
o Is used to speed up data transfer between Core and Main Memory (DRAM);
 But,
o It makes the performance unpredicted
o It doesn’t help Real-Time system response;
o Note that many small embedded systems do not require the benefit of a cache.
2. Memory(Width):

a. In number of bits the memory returns on each access

i. 8, 16, 32, or 64 bits.
b. 32-bitARM instructions and 16-bit-wide memory chips:
i. Then the processor will have to make two memory fetches per instruction. Each
fetch requires two 16-bit loads.
c. Hence it is better to have 16-bit Thumb instructions with 16-bit-wide memory .

3. Memory(Types):
 DRAM
o the most commonly used RAM for devices;
 o Dynamic: need to have its storage cells refreshed and given a new electronic charge
every few milliseconds, so you need to set up a DRAM controller before using the
memory.
a. SRAM
i. Is faster than the more traditional DRAM (SRAM does not require a pause
between data access).
b. SDRAM
i. Is one of many subcategories of DRAM.
ii. Accessed pipelined, transferred in a burst.

Question 8:

What are memory controllers and interrupt controllers?

Answer
• Memory Controllers: Connect different types of memory to the processor bus.

– On power-up a memory controller is configured in hardware to allow certain memory

device to be active. These memory devices allow the initialization code to be executed.

– Some memory devices must be set up by software.

• e.g. When using DRAM, you first have to set up the memory timings and refresh
rate before it can be accessed.

• Interrupt controller

– When a peripheral or device requires attention,

• it raise an interrupt to the processor. provides a programmable governing policy

– There are two types of interrupt controller available for the ARM processor

– Standard interrupt controller

• Sends an interrupt signal; Can be programmed to ignore or mask an individual or

set of devices.

• It’s interrupt handler determines which device requiring service.

– Vector interrupt controller (VIC)

• Associate a “priority” and a “handler address” to each interrupt.

 • Depending on its type, VIC will either call the standard interrupt exception handler
(loading the handler address from VIC) or cause core to jump to the handler for
the device directly.

Question 9:

With a neat diagram explain the different software components of an embedded

system.
OR
Give different applications of ARM processors.
OR
Give the significance of initialization code in an embedded system software.

Answer
• An embedded system needs software to drive it.

• There are four typical software components required to control an embedded device.

• Each software component in the stack uses a higher level of abstraction to

separate the code from the hardware device.

– Initialization Code (e.g. Boot loader)

– Operating System

– Device Drivers

– Application

1. Initialization code (or boot code)

– takes the processor from the reset state to a state (where the operating system can run).

• Configuring memory controller, caches

 • Initializing some devices

• * Debug Monitor (replace OS in simple system)

2. Three phases

– Initial hardware configuration

• Satisfy the requirements of the booted image

– e.g. re-organization of the memory map

– Diagnostics

• Fault identification and isolation

– Booting

• Loading an image and handing control over to the image

• The boot process may be complicated if the system must boot different operating
systems or different versions of the same operating system.

2. OS organizes the system resources

– peripherals, memory, and processing time

• With an OS controlling these resources, they can be efficiently used by different

applications running within the OS environment.

• ARM processors support over 50 OSes

– Two main categories: RTOS, platform OS

 • RTOS: guarantee response times to event

• platform OS: require MMU(Memory Mgmt Unit ) and tend to have secondary
storage (for large application).

– N.B., These two categories of OSes are not mutually exclusive.

– ARM has developed a set of processor cores that specially target each category.

3. The OS schedules applications

– Code dedicated to handling a particular task.

– ARM processors are found in numerous market segments, including

– Networking, automotive, mobile and consumer devices, mass storage, and imaging.

– In contrast, ARM processors are not found in applications that require leading-edge high
performance.(Because they will be low volume and high cost)

Question 10:

With a neat diagram explain the different general purpose registers of ARM
processors.

Answer
 1. Orthogonal Registers
a. We say R0~R13 are orthogonal, for given
instruction, if it can use R0, then others can also be
used.
2. SPRs
a. R13(stack pointer), R14(link register), R15(program
counter)
3. Current PSR/Saved PSR:
a. Condition Codes: N, Z, C, V
b. Interruption mask: I(IRQ), F(FIQ)
c. Thumb Enable Bit
d. Mode(5-bit)

Question 11:

Explain ARM data flow model.

Answer

• ALU
• Sources: Rn, Rm(shifted);
• Destination: Rd
• Shifter
• Helps to Extend the scope of data or address
• Sign-extend
• LOAD data from Main memory
Question 12:

Explain current program status register with neat diagram.

OR
Which are the different conditional flags of ARM processor.

Answer
Current Program Status Register (CPSR):

• The cpsr : Dedicated 32-bit register and resides in the register file

• cpsr :

1. Divided into four fields, each 8 bits wide:

• flags, status, extension, and control.

2. The control field contains the processor mode, state, and interrupt mask bits.

3. The flags field contains the condition flags.

 • Condition Codes: N, Z, C, V

• Interruption mask: I(IRQ), F(FIQ)

• Thumb Enable Bit

• Mode(5-bit)

• Determines which registers are active and the access rights to the cpsr register

• Two modes: either privileged or nonprivileged

1. A privileged mode allows full read-write access to the cpsr.

2. In nonprivileged mode only allows read access to the control field in the cpsr but still
allows read-write access to the condition flags.

• There are seven processor modes in total:

1. six privileged modes

• abort, fast interrupt request, interrupt request, supervisor, system, and

undefined) one nonprivileged mode

2. one nonprivileged mode

 • user

Question 13:

What are banked registers?

Answer

Banked Registers:

• 37 registers in the register file:

– 20 registers are hidden
• (Banked Registers-shaded in diagram)
When there is change of mode from user->IRQ

• Values of register changes as follows:

Question 14:

Explain ARM 7 pipeline.

Answer

• A pipeline is the mechanism a RISC processor uses to execute instructions.

– Using a pipeline speeds up execution by fetching the next instruction

while other instructions are being decoded and executed.
Pipeline(Example)

Pipeline Executing Characteristics:

Question 15:
What are interrupts or exceptions? How are they handled in ARM processors?
Answer

1. When an exception or interrupt occurs:

– The processor sets the pc to a specific memory address.

– The address is within a special address range called the vector table. The
entries in the vector table are instructions that branch to specific
routines designed to handle a particular exception or interrupt.

2. The memory map address 0x00000000

– Is reserved for the vector table, a set of 32-bit words.

– the vector table can be optionally located at a higher address in memory

(starting at the offset 0xffff0000)

3. Each vector table entry contains a form of branch instruction pointing to the
start of a specific routine:

• Reset vector

– It is the location of 1st instruction after power-up;

• Undefined instruction vector

– Is used when processor cannot decoded instruction.

• Software interrupt vector is called when:

– SWI instruction being executed(To invoke OS routine)

• Prefetch Abort vector (PABT) occurs :

– try to access invalid address for instruction;

• Data Abort (DABT)

– Try to access invalid address for data;

• IRQ
• FIQ
Question 16:

What are the different techniques of core extensions?

Answer

1. Cache & Tightly Coupled Memory(TCM)

– Unified vs. I/D

– TCM: fast SRAM, very near Core (unwired with AMBA)

– Two architectures w.r.t cache

• Von Neumann architecture

• Harvard architecture

2. Memory Management interface

– No MM: for simple embedded system;

– MPU(Memory Protect Unit): section protection;

– MMU is an h/w available on ARM: Translation table to provide Fine-

grain protection on memory (Virtual- Physical address Map)

3. Coprocessor interface
 The coprocessor can be accessed through a group of dedicated ARM
instructions that provide a load-store type interface.

– By Extend Instruction Set vs. CSR register;

– E.g.

• CP15: cache, TCM and MMU via load/store like instr.

Question 17:

Differentiate ARM and Thumb instruction set features.

Answer

There are three instruction sets: ARM, Thumb, and Jazelle.