Unit 2:

PLD Architectures

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Syllabus:
PROM, PLA, PAL: Architectures and applications. Software Design Flow, CPLD Architecture,
Features, Specifications, Applications, FPGA Architecture, Features, Specifications,
Applications

Course Outcome:
CO2: Differentiate between CPLD and FPGA Architectures

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2.1 Introduction:
A programmable logic device is an IC that is user configurable and is capable of
implementing logic functions. It is an LSI chip that contains a ‘regular’ structure and
allows the designer to customize it for any specific application, i.e. it is programmed
by the user to perform a function required for his application.
A PLD contains a large number of gates, flip-flops, and registers that are
interconnected on the chip. Many of the connections, however, are fusible links that
can be broken. The IC is said to be programmable because the specific function of
the IC for a given application is determined by the selective breaking of some of the
interconnections while leaving others intact. The ‘fuse blowing’ process can be done
either by the manufacturer in accordance with the customer’s instructions, or by the
customer himself. This process is called ‘programming’ because it produces the
desired circuit pattern interconnecting the gates, flip-flops, registers, and so on. PLDs
can be reprogrammed in a few seconds and hence give more flexibility to experiment
with designs. The reprogramming feature of PLDs also makes it possible to accept
changes/modifications in the previously designed circuits. All these advantages make
PLDs very popular in digital design.

The advantages of PLDs over fixed function ICs are as follows:

1. Low development cost
2. Less space requirement
3. Less power requirement
4. High reliability
5. Easy circuit testing
6. Easy design modification
7. High design security
8. Less design time
9. High switching speed

PLDs have many of the advantages of ASICs as given below:

1. Higher densities
2. Lower quantity production costs
3. Design security
4. Reduced power requirement
5. Reduced space requirement
PLD allows designers more flexibilities to experiment with designs. They are useful
in prototyping ASIC designs. PLD designs have lesser power consumption, fewer IC
count and more reliable than discrete logic designs.
Programmable logic devices are available in many different types. The current range
of devices span from small devices capable of implementing only a handful of logic
equations to huge FPGAs that can hold an entire processor core and peripherals. In
addition to this incredible difference in size, there are many variations in the
architecture.
Programmable logic devices can be divided into three distinct architectural groups.
 Simple Programmable Logic Devices – SPLDs
 Complex Programmable Logic Devices – CPLDs
 Field Programmable Gate Arrays – FPGAs

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 2.2 Simple Programmable Devices:
SPLDs are the simplest, smallest and least-expensive type of programmable logic
device. These devices typically have logic gates laid out in arrays where the
interconnection between these arrays is configurable by the user.
The term SPLD covers several types of device:
 ROM
 Programmable Logic Array (PLA) – This device has both programmable
AND and OR planes.
 Field Programmable Logic Array (FPLA) – Same as PLA but can be
erased and reprogrammed
 Programmable Array Logic (PAL) – This device has a programmable AND
plane and a fixed OR plane
 Generic Array Logic (GAL) – This device has the same logical properties as
the PAL but can be erased and reprogrammed

The figure shows a general structure of an SPLD. The connection link across two
wires can either be predefined or programmable depending on the type of SPLD.

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 General PLDs have a set of inputs (Logic variables) and set of outputs (Logic
functions). The job of the designer is to simply program switches so that gates can
perform the defined functions. It can be represented as follows

ROM, PAL and PLA are the three varieties that are quite similar to each other. They
all have an input connection matrix, which connects the inputs of the device to an
array of AND-gate. They all have an output connection matrix, which connect the
outputs of the AND-gates to the inputs of OR-gates which drive the outputs of the
device. The given logic SOP function can be implemented using AND and OR
arrays.

The differences between the first three categories are these:

 In a ROM, the input connection matrix is hardwired. The user can

modify the output connection matrix.

 In a PAL/GAL the output connection matrix is hardwired. The user can

modify the input connection matrix.

 In a PLA the user can modify both the input connection matrix and the
output connection matrix.

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 2.2.1 Programming

Techniques: Fusible
link technology

Anti-fuse Technology:

In antifuse technologies , the un-programmed device has links which are very high in
resistance. It is exactly complement of fusible link technology. An antifuse initially provides
insulation between two conductors, but a conducting path is formed when a sufficient
programming voltage is applied across it.

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 Comparison of programming technologies:

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 PLD Notations:

2.3 ROM as PLD:

A read-only memory (ROM) is essentially a memory device in which permanent
binary information is stored. The binary information must be specified by the
designer and is then embedded in the unit to form the required interconnection
pattern. Once the pattern is established, it stays within the unit when the power is
turned off and on again.
A ROM which can be programmed is called a PROM. The process of entering
information in a ROM is known as programming. ROMs are used to store
information which is of fixed type, such as tables for various functions, fixed data
and instructions.

The advantages of using a ROM as a PLD are the following:

1. Ease of design since no simplification or minimization of logic function is required.
2. Designs can be changed, modified rapidly.
3. It is usually faster than discrete MSI/SSI circuit.
4. Cost is reduced.

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 There are a few disadvantages also of ROM based circuits, such as:
1. Non-utilization of complete circuit
2. Increased power requirement
3. Enormous increase in size with increase in the number of input variables making it
impractical

A block diagram of a ROM is shown in Figure below which consists of k inputs and
n outputs. The inputs provide the address for the memory and the outputs give the
data bits of the stored word which is selected by the address. The number of words in
a ROM is determined from the fact that k address input lines are needed to specify 2k

words.

For example, 32*8 Rom which consists 32 words of 8 bits. Its internal architecture
can be shown as below. 5 t0 32 decoder is used to select 32 address lines. Each
output of the decoder is connected to one of the inputs of each OR gate. Since each
OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32 × 8
= 256 internal connections.

Combinational Circuit Implementation using ROM:

By choosing connections for the minterms that are included in the function, the ROM
outputs can be programmed to represent the Boolean functions of the output
variables in a combinational circuit.

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 EX 1: Design a combinational circuit using a ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of the input
number.
Solution:
1. Derive the truth table of the combinational circuit
2. Calculate input and output lines required - Three inputs and six outputs
are needed to accommodate all possible binary numbers.
3. We note that output B0 is always equal to input A0; so there is no need to
generate B0 with a ROM since it is equal to an input variable. Moreover,
output B1 is always 0, so this output is a known constant.
4. The minimum size ROM needed must have three inputs and four outputs.
Three inputs specify eight words, so the ROM must be of size 8 × 4.
Truth table is as shown below

Truth table for ROM is as shown in fig.a and block diagram in fig b

In general, a P variable, N outputs logic function can be implemented using ROM of

size 2P x N since all the 2P minterms are effectively generated.

Ex 2: Give the logic implementation of a 8 × 4 bit ROM using a decoder of a suitable size.
Solution:
An 8 × 4 bit ROM is to be implemented. It consists of eight words of four bits each. 8
words can be addressed by 3 bits. Hence 3 to 8 decoder can be used to implement the

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 logic.

2.4 Programmable Array Logic (PAL):

A PAL (programmable array logic) consists of a programmable array of AND gates that
connects to a fixed array of OR gates. Generally, PALs are implemented with fuse process
technology and are, therefore, one-time programmable (OTP). Because only the AND gates
are programmable, the PAL is easier to program but is not as flexible as the PLA.
The PAL structure allows any sum-of-products (SOP) logic expression with a defined number
of variables to be implemented. Figure below shows a small example of the basic structure.
The fuse symbols represent fusible links that can be burned open using equipment similar to a
PROM programmer.

The PAL abbreviated connection is as shown below which consists It is a 3-input 3-wide
AND- OR structure.
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 For example to implement the following functions which can be implemented using
combinational circuit as shown in fig a and it can be redrawn to implement it with
PAL using fig b

PAL Programming Table:

The fuse map of a PAL can be specified in a tabular form. The PAL programming table
consists of three columns. The first column lists the product terms numerically. The second
column specifies the required paths between inputs and AND gates. The third column
specifies the outputs of the OR gates.
For each product term the inputs are marked with 1, 0, or – (dash). If a variable in the product
term appears in its true form, the corresponding input variable is marked with a 1. If it appears
in complemented form, the corresponding input variable is marked with a 0. If the variable is
absent in the product term, it is marked as a – (dash).
For n inputs, k product terms, and m outputs the internal logic of the PAL consists of n buffer
inverter gates, k AND gates, and m OR gates.
When implementing a combinational circuit with a PAL, careful investigation must be
undertaken in order to reduce the number of distinct product terms. Since a PAL has a finite
number of AND gates, this can be done by simplifying each Boolean function (K-map) to a
minimum number of terms.
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Ex3: Implement the following Boolean functions using PAL with four inputs and 3-wide AND-
OR structure. Also write the PAL programming table.
F1(A, B, C, D) = ∑ m(2, 12, 13)
F2(A, B, C, D) = ∑ m(7, 8, 9, 10, 11, 12, 13, 14, 15)
F3(A, B, C, D) = ∑ m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
F4(A, B, C, D) = ∑ m(1, 2, 8, 12, 13).
Solution:
1. Find the simplified Boolean equation for each function using K-map
2. Write the truth table for programming PAL
3. Using PAL programming table implement circuit

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2.5 Programmable Logic Array (PLA):
The PLA represents another type of programmable logic which combines the characteristics
of the PROM and the PAL. It provides both a programmable OR array and a programmable
AND array, i.e. in a PLA both AND gates and OR gates have fuses at the inputs. A third set
of fuses in the output inverters allows the output function to be inverted if required. Usually
X-OR gates are used for controlled inversion. This feature makes it the most versatile of the
three PLDs.
PLA can be mask programmable or field programmable. With a mask programmable PLA,
the user must submit a PLA programming table to the manufacturer. This table is used by
the vender to produce a user made PLA that has the required internal paths between inputs
and outputs. A second type of PLA available is called a field programmable logic array or
FPLA. The FPLA can be programmed by the user by means of certain recommended
procedures. FPLAs can be programmed with commercially available programmer units.

EX : Show how the PLA circuit would be programmed to implement the sum and carry outputs
of a full adder.
Solution:
The truth table of a full-adder is shown in Figure Below with the K-maps for the sum and
carry-out terms and minimizing them, the minimal expressions for the sum and carry-out
terms are:
The sum is

And carry is given by

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 Ex: Show how the PLA circuit in can be programmed to implement the 3-bit binary-
to-gray conversion.
Solution:
1. Prepare the truth table for 3 bit binary to gray convertor
2. Draw K map for G3, G2 and G1
3. Minimize the boolean equations for gray bits
4. Implement the circuit
The conversion table of 3-bit binary (B3, B2, B1)-to-gray (G3, G2, G1) is shown in
Figure below. From the conversion table we observe that the expressions for the
outputs are:
G3 = ∑ m(4, 5, 6, 7)
G2 = ∑ m(2, 3, 4, 5)
G1 = ∑ m(1, 2, 5, 6)
minimal expressions for G3, G2, and G1 are:

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PLA Programming Table:
The fuse map of a PLA can be specified in a tabular form. The PLA programming
table consists of three columns. The first column lists the product term numerically.
The second column specifies the required paths between inputs and AND gates. The
third column specifies the paths between the AND and OR gates. For each output
variable, we may have a T (for true) or C (for complement) for programming the X-
OR gate
The product terms listed on the left are not part of the table; they are included for
reference only. For each product term the inputs are marked with 1, 0, or – (dash). If
a variable in the product term appears in its true form, the corresponding input
variable is marked with a 1. If it appears complemented, the corresponding input
variable is marked with a 0. If the variable is absent in the product term, it is marked
as a – (dash).
The size of a PLA is specified by the number of inputs, the number of product terms,
and the number of outputs. For n inputs, k product terms, and m outputs the internal
logic of the PLA consists of n buffer inverter gates, k AND gates, m OR gates, and m
X-OR gates.
When implementing a combinational circuit with a PLA, careful investigation must
be undertaken in order to reduce the number of distinct product terms. Since a PLA
has a finite number of AND gates this can be done by simplifying each Boolean
function to a minimum number of terms. Both the true and the complement of each
function should be simplified to see which one can be expressed with a fewer
product terms and which one provides product terms that are common to other

functions.

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 Ex: Implement the following two Boolean
functions with a PLA: F1(A, B, C) = ∑ m(0, 1, 2,
4)
F2(A, B, C) = ∑ m(0, 5, 6, 7)
Solution: CC

Product term Inputs Output

1 𝐴̅ 𝐶̅
A B C F1 F2

2 𝐵̅𝐶̅
0 - 0 1 -

3 𝐴̅ 𝐵̅
- 0 0 1 -

4 𝐴̅ 𝐵̅ 𝐶̅
0 0 - 1 -
0 0 0 - 1
5 AB 1 1 - - 1
6 AC 1 - 1 - 1

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Improved Solution with minimised terms:
1. Find the K-maps for the functions F1 and F2, their minimization, and the
minimal expressions for both the true and complement forms of those in sum
of products.
2. For finding the minimal in complement form consider the 0s on the map.

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 Ex: EXAMPLE 8.11 Tabulate the PLA programming table for the four
Boolean functions listed below.
A(x, y, z) = ∑ m(1, 2, 4, 6) B(x, y, z) = ∑ m( 0, 1, 6, 7)
C(x, y, z) = ∑ m(2, 6) D(x, y, z) = ∑ m(1, 2, 3, 5, 7)

Solution:

Observing the expressions in true and complement form for A, B, C and D, we

notice that the combination that gives a minimum number of product terms is:

Which gives the six distinct terms

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 2.6 Complex Programmable Logic Devices (CPLD):
The SPLD devices like PLA, PAL, PROM, GAL have a limited number of inputs,
product terms and outputs. These devices support only 32 I/O numbers. For
implementation of more I/O we can use multiple SPLD devices. But using multiple
SPLD have disadvantages as follows:
1. PCB size increases with number of chips
2. Connecting wires will result in adverse capacitive effect
3. Power requirement increases with number of chips
4. Cost increases
Designing PLD using the architecture of SPLD also increases the capacitive effect,
increases leakage current, decreases speed and increases cost. To overcome these
disadvantages CPLD was evolved.
The complex programmable logic device (CPLD) is basically a single device
containing multiple SPLDs and providing more capacity for larger logic designs. A
CPLD (complex programmable logic device) consists basically of multiple SPLD
arrays with programmable interconnections. Generic CPLD is as shown below

CPLDs contain multiple circuit blocks on a single chip. Each block is like a PAL:
PAL-like block and connections are provided between PAL-like blocks via an
interconnection network that is programmable. Each block is connected to an I/O
block as well.

Xilinx 9500 CPLD:

The XC9500 CPLD family provides advanced in-system programming and test capabilities for
high performance, general purpose logic integration. All devices are in-system programmable

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 for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan
support is also included on all family members. The logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. The XC9500
family is fully pin-compatible allowing easy design migration across multiple density options
in a given package footprint. The XC9500 architectural features address the requirements
of in-system
programmability. Enhanced pin-locking capability avoids costly board rework. An expanded
JTAG instruction set allows version control of programming patterns and in-system debugging.
In-system programming throughout the full device operating range and a minimum of 10,000
program/erase cycles provide worry-free reconfigurations and system field upgrades.
Advanced system features include output slew rate control and user-programmable ground pins
to help reduce system noise. I/Os may be configured for 3.3V or 5V operation. All outputs
provide 24 mA drive

The architecture of 9500 is as as follows

Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O
Blocks (IOBs) fully interconnected by the Fast CONNECT™ switch matrix. The IOB provides
buffering for device inputs and outputs. Each FB provides programmable logic capability with
36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input
signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and
associated output enable signals drive directly to the IOBs.

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Function Block:
Each Function Block, as shown in below, is comprised of 18 independent macrocells, each
capable of implementing a combinatorial or registered function. The FB also receives global
clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the Fast
CONNECT switch matrix. These 18 outputs and their corresponding output enable signals also
drive the IOB. Logic within the FB is implemented using a sum-of-products representation.
Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to
form 90 product terms. Any number of these product terms, up to the 90 available, can be
allocated to each macrocell by the
product term allocator. Each FB (except for the XC9536) supports local feedback paths that
allow any number of FB outputs to drive into its own programmable AND-array without going
outside the FB. These paths are used for creating very fast counters and state machines where
all state registers are within the same FB.

Macrocell:
Each XC9500 macrocell may be individually configured for a combinatorial or registered
function. The macrocell and associated FB logic is shown in below. Five direct product terms
from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs including clock, set/reset, and output
enable. The product term allocator associated with each macrocell selects how the five direct
terms are used. The macrocell register can be configured as a D-type or T-type flip-flop, or it
may be bypassed for combinatorial operation. Each register supports both asynchronous set and
reset operations. During power-up, all user registers are initialized to the user-defined preload
state (default to 0 if unspecified). All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable signals.

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Product Term Allocator
The product term allocator controls how the five direct product terms are assigned to each
macrocell. For example, all five direct terms can drive the OR function. The product term
allocator can re-assign other product terms within the FB to increase the logic capacity of a
microcell beyond five direct terms. Any macrocell requiring additional product terms can
access uncommitted product terms in other macrocells within the FB. Up to 15 product terms
can be available to a single macrocell with only a small incremental delay of TPTA

In system Programming:
XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol (IEEE 1149.1
boundary-scan (JTAG), as shown below. In-system programming offers quick and efficient
design iterations and liminates package handling. The Xilinx development system provides the
programming data sequence using a Xilinx download cable, a third-party JTAG development
system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the
JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during
in- system programming. If a particular signal must remain Low during this time, then a

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pulldown resistor may be added to the pin.

Xilinx 9500 Features:

 High-performance
- 5 ns pin-to-pin logic delays on all pins
- fCNT to 125 MHz
 Large density range
- 36 to 288 macrocells with 800 to 6,400 usable gates
 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
 Enhanced pin-locking architecture
 Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
- Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
- Programmable power reduction mode in each macrocell
- Slew rate control on individual outputs
- User programmable ground pin capability
- Extended pattern security features for design protection
- High-drive 24 mA outputs
- 3.3V or 5V I/O capability
-Advanced CMOS 5V FastFLASH™ technology
- Supports parallel programming of multiple XC9500 devices

Applications:
Owing to their less flexible internal architecture leading to predictable timing
performance, high speed and a range of logic capacities, CPLDs find extensive use
in a wide assortment of applications. These include the implementation of random
glue logic in prototyping small gate arrays, implementing critical control designs
such as graphics controllers, cache control, UARTs, LAN controllers and many
more.
Complex designs using a large number of SPLDs can be replaced with a CPLD-

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 based design with a much smaller number of devices. This is particularly attractive
in portable applications such as mobile phones, digital assistants and so on. CPLD
architecture particularly suits those designs that exploit wide AND/OR gates and do
not require a large number of flip-flops. The reprogramming feature of CPLDs
makes the incorporation of design changes very easy.

2.7 Field Programmable Gate Array (FPGA):

It is not practical to increase the logic capacity with a CPLD architecture beyond a certain
point. the classic CPLD architecture consists of PAL/GAL or PLA-type logic blocks with
programmable interconnections. Basically, the FPGA (field-programmable gate array)
differs in architecture, does not use PAL/PLA type arrays, and has much greater densities
than CPLDs. A typical FPGA has many times more equivalent gates than a typical CPLD.
The logic-producing elements in FPGAs are generally much smaller than in CPLDs, and
there are many more of them. Also, the programmable interconnections are generally
organized in a row and column arrangement in FPGAs.
The first FPGA was introduced by Xilinx in 1985. It has arrays of logic blocks which are
programmable. It is surrounded by PROGRAMMABLE ROUTING RESOURCES, which
allows the user to define the interconnections between the logic blocks. It also has lots of
very flexible input and output circuits (programmable for TTL, CMOS and other interface
standards).

The configurable logic blocks (CLBs) in an FPGA are not as complex as the LABs or
function blocks (FBs) in a CPLD, but generally there are many more of them. When the

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 CLBs are relatively simple, the FPGA architecture is called fine grained. When the CLBs are
larger and more complex, the architecture is called coarse grained. The I/O blocks around the
perimeter of the structure provide individually selectable input, output, or bidirectional access
to the outside world. The distributed matrix of programmable interconnections provide for
interconnection of the CLBs and connection to inputs and outputs. Large FPGAs can have
tens of thousands of CLBs in addition to memory and other resources.
FPGAs are reprogrammable and use SRAM or antifuse process technology for the
programmable links. Densities can range from hundreds of logic modules to hundreds of
thousands of logic modules in packages with up to over 1,000 pins. DC supply voltages are
typically 1.8 V to 5 V, depending on the specific device

Configurable Logic Blocks:

Typically, an FPGA logic block consists of several smaller logic modules that are the basic
building units, Somewhat analogous to macrocells in a CPLD. Figure below shows the
fundamental configurable logic blocks (CLBs) within the global row/column programmable
interconnects that are used to connect logic blocks. Each CLB (also known as logic array
block, LAB) is made up of multiple smaller logic modules and a local programmable
interconnect that is used to connect logic modules within the CLB.

Logic Module:
A logic module consists of LUT (Look Up Table), a D Flipflop and a Multiplexer. Most of
the FPGAs are having 4 input LUT. Output of the LUT may become direct output of Logic
module or input to D FF. Thus the output can be combinational or registered through FF.

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 A LUT consists of programmable memory and it can be used to generate logic function in
SOP form. A memory can generate canonical product form. A LUT consists a memory and a
MUX. The limit on the size of the truth table is N, where N represents the number of inputs to
the LUT. For the general N-input LUT, the number of memory locations accessed by the
table is 2N. This allows the table to implement 2 N^N functions. Note that a typical value for N
in Xilinx FPGAs is 6.

Programmable I/O
The programmable I/O pads are used to interface the logic blocks and routing architecture to
the external components. The I/O pad and the surrounding logic circuit form as an I/O cell.

Programming Technologies
There are a number of programming technologies that have been used for reconfigurable
architectures. Each of these technologies have different characteristics which in turn have
significant effect on the programmable architecture. Some of the well known technologies
include static memory (SRAM), flash and anti-fuse.

Applications of FPGA:
FPGAs have gained rapid growth over the past decade because they are useful for a wide
range of applications. Specific application of an FPGA includes digital signal processing,

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 bioinformatics, device controllers, software-defined radio, random logic, ASIC prototyping,
medical imaging, computer hardware emulation, integrating multiple SPLDs, voice
recognition, cryptography, filtering and communication encoding and many more.
Some More Common FPGA Applications are: Aerospace and Defense, Medical Electronics,
ASIC Prototyping, Audio, Automotive, Broadcast, Consumer Electronics, Distributed
Monetary Systems, Data Center, High Performance Computing, Industrial, Medical,
Scientific Instruments, Security systems, Video & Image Processing, Wired
Communications, Wireless Communications.

Difference Between CPLD and FPGA:

Parameter CPLD FPGA
Cost It is less expensive It is more expensive
Power Consumption Low High
Flexibility Less More
Security High Low
Basic Building Blocks PLD CLB
Functionality implementation PAL-And OR logic LUT
Complexity Less More
Density of gates 10000 to 1 milllion Upto 10000
Speed High High
Delays Predictable Non predictable
Programability Reprogrammed for limited Reprogrammed for as possible
times as
Application Simple applications Complex applications

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