9. What are input/output and interrupts? How do they work in a system? 10.

10. explain fetch cycle and interrupt cycle . also give micrro operation and 11. Explain the instruction cycle and the role of control signals.
Ans- Input/Output (I/O) refers to the process of transferring data between the control signal? Ans- The Instruction Cycle is the sequence of steps a CPU follows to fetch,
computer system and external devices, such as keyboards, mice, monitors, Ans - 1. Fetch Cycle decode, execute, and store instructions from memory. It defines how a
printers, and storage drives. : The Fetch Cycle is the process of retrieving an instruction from memory and processor executes machine-level instructions.
Types of I/O Devices: preparing it for execution. It is the first phase of the Instruction Cycle. Each instruction cycle consists of multiple micro-operations, which are
I. Input Devices: Used to send data to the computer. Ex: Keyboard, Mouse, Steps in the Fetch Cycle: controlled by control signals to manage data flow between CPU component
Scanner, Microphone. a. Fetch the instruction from memory (using the Program Counter - PC) Phases of the Instruction Cycle
Ii . Output Devices: Used to receive data from the computer. Ex: Monitor, Printer, b. Increment the PC (to point to the next instruction). A) Fetch Cycle (Fetching the Instruction)
[Link]. Storage Devices: Store data for long-term use. Ex: Hard Disk, SSD, c. Decode the instruction (identify the operation to be performed). The CPU retrieves an instruction from memory.
USB Drives. Micro-Operations in Fetch Cycle: The Program Counter (PC) holds the address of the next instruction to fetch.
i. MAR ← PC : Move the Program Counter (PC) value to the Memory Address The instruction is then placed into the Instruction Register (IR).
Types of I/O Operations: Register (MAR) to fetch the instruction. Control Signals in Fetch Cycle:
[Link] I/O: CPU directly controls I/O operations using instructions. ii. MDR ← Memory[MAR] : Read the instruction from memory and store it in 1. PCout → MARin (Transfers address from PC to MAR).
*Slower because CPU must wait for I/O operations to complete. the Memory Data Register (MDR). 2. Read (Fetch instruction from memory).
Ex: CPU checks printer status before sending data. Iii. PC ← PC + 1 : Increment the PC to point to the next instruction. 3. MDRout → IRin (Transfer instruction to IR).
[Link]-Driven(I/O) :CPU executes other tasks while waiting for I/O iv. IR ← MDR : Store the fetched instruction in the Instruction Register (IR). 4. PCout, Add, PCin (Increment PC)
completion. When I/O is ready, it sends an interrupt to the CPU. Control Signals in Fetch Cycle: B) Decode Cycle (Interpreting the Instruction)
Ex: Keyboard press generates an interrupt for CPU to process input. 1. Memory Read (Read): Enables memory to send data to MDR. The Control Unit (CU) decodes the instruction stored in the Instruction Register
[Link] Memory Access (DMA):A special controller transfers data between 2. PC Enable (PCout, PCin): Transfers address from PC to MAR. (IR).It identifies the operation type (e.g., arithmetic, logic, memory access).
memory and I/O devices without CPU involvement. Increases efficiency by 3. MAR Enable (MARin): Loads address from PC into MAR. The opcode and operands are extracted.
reducing CPU workload. Ex: Transferring data from HDD to RAM via DMA. 4. IR Enable (IRin): Loads instruction from MDR into IR. Control Signals in Decode Cycle:
1. IRout → Control Logic (Sends instruction to CU).
Interrupts: An interrupt is a signal sent to the CPU when an event requires Interrupt Cycle: 2. Control Signal Generation (CU determines control signals for
immediate attention, temporarily stopping current execution. The Interrupt Cycle occurs when an interrupt signal is received, causing the CPU execution).
Types of Interrupts: to pause current execution and handle the interrupt before resuming normal C) Execute Cycle (Performing the Operation)
[Link] Interrupts: Generated by external devices (e.g., keyboard, printer, operation. The CPU executes the instruction based on the decoded operation.
mouse).Ex: Pressing a key generates a keyboard interrupt. Steps in the Interrupt Cycle: Data is fetched from registers/memory and processed by the ALU (if
ii Software Interrupts: Generated by software programs to request CPU services. [Link] the current program state (store PC and status registers). arithmetic/logical).
Example: System calls (e.g., printing a document). B .Jump to the Interrupt Service Routine (ISR) to handle the interrupt. Control Signals in Execute Cycle:
iii. Internal Interrupts (Exceptions):Generated by the CPU due to errors (e.g., c.. Execute the ISR and return control to the main program. 1. ALU Control Signals (Add, Sub, And, Or, etc.).
division by zero). Example: Segmentation fault in memory access. Micro-Operations in Interrupt Cycle: 2. Register Select Signals (R1in, R2out).
[Link] PC to Stack - Store the PC value in the stack to resume later. 3. Memory Read/Write Signals (Read, Write).
Working of Interrupts in a System: [Link] ← Interrupt Vector Address - Load the address of the interrupt service 4. PC Update Signals (PCin, PCout, JUMP).
1. Event Occurs: A device (e.g., keyboard) or system condition routine (ISR). D) Store Cycle : The result of execution is stored in a register or memory
triggers an interrupt. [Link] ISR- Perform interrupt-specific operations. location.
2. Interrupt Signal Sent to CPU: he interrupts controller signals the [Link] PC from Stack - Retrieve PC from stack after ISR execution. Used mainly for LOAD, STORE, and arithmetic operations.
CPU to handle the event. Control Signals in Interrupt Cycle: Control Signals in Store Cycle:
3. CPU Saves Current State: Registers and program counter values 1. Interrupt Request (INT): Notifies CPU of an interrupt. 1. MDRout → Memory Write (Writes data to memory).
are stored to resume execution later. 2. Interrupt Acknowledge (INTA): CPU acknowledges and 2. Register Selection Signals (Rin, Rout)
4. Interrupt Service Routine (ISR) Execution: The CPU executes the processes the interrupt. Key Functions of Control Signals:
ISR (predefined routine) to handle the interrupt. 3. Stack Write (Stackin, Stackout): Stores and retrieves PC. ✔ Data Transfer (PCout, MARin, MDRin, IRin) – Moves data between CPU
5. CPU Restores Previous State: After handling, the CPU resumes 4. Jump to ISR (PCin, MARin): Transfers control to ISR. components.
the interrupted task. ✔ Memory Access (Read, Write) – Fetches or stores data in RAM.
✔ ALU Control (Add, Sub, And, Or) – Directs ALU operations.
✔ Control Flow (Jump, Branch) – Changes execution sequence.
✔ I/O Communication (Input, Output) – Handles device interactions

12. What is a hardwired control unit? Explain its working 14. What is program control? Explain its importance 15. Compare Reduced Instruction Set Computer (RISC) and Complex
Ans- A Hardwired Control Unit is a control mechanism in a CPU where control Ans- Program Control refers to the mechanism by which the sequence of Instruction Set Computer (CISC).
signals are generated using fixed electronic circuits (combinational logic gates, execution of instructions in a computer system is managed. It ensures Ans- RISC is a CPU design philosophy that uses a small set of simple and
flip-flops, and counters). It directly translates the instruction opcode into that instructions are fetched, decoded, executed, and stored in the general-purpose instructions. The architecture focuses on fast execution,
control signals required for execution. Working of a Hardwired Control Unit
correct order. This process is primarily managed by the Control Unit (CU) pipelining, and efficient use of registers.
[Link] Fetch & Decode: The instruction is fetched from memory and
of the CPU. Importance of Program Control Characteristics of RISC:
stored in the Instruction Register (IR) The opcode is sent to the control logic.
[Link] Signal Generation: A decoder converts the opcode into corresponding [Link] Proper Execution Order i. Simple and Fixed-Length Instructions:- Uses fewer instructions, each
control [Link] signals activate the required CPU components (ALU, --Program control maintains the logical flow of execution by following taking a single clock cycle. Instructions are of fixed size, making decoding
registers, memory, etc.). the instruction cycle (Fetch → Decode → Execute → Store). easier.
[Link]: The ALU, registers, and memory perform the specified operation. --It ensures that branching, looping, and sequential execution happen ii. Load-Store Architecture
If a jump or branch instruction is executed, the Program Counter (PC) is updated correctly. Only Load (LDR) and Store (STR) instructions access memory; all other
accordingly. [Link] Decision Making (Branching & Looping) operations work with registers.
[Link] Completion: The next instruction cycle begins. --Program control manages conditional and unconditional jumps (e.g., IF- Reduces memory access time, improving speed.
Components of a Hardwired Control Unit: ELSE, WHILE loops). iii. Pipeline-Friendly
[Link] Decoder: Decodes opcode from the instruction register. [Link] Interrupts & Exceptions Simple instructions allow faster execution using instruction pipelining.
[Link] Signal Generator:Uses combinational logic to generate control signals.
--If an interrupt (external event) occurs, program control pauses Higher Instruction Per Cycle (IPC).
[Link] Logic:Uses counters and flip-flops to maintain execution order.
execution, handles the event, and resumes execution. iv More Registers
ivTiming and Control Logic:Ensures proper synchronization between fetch,
decode, execute, and store cycles. Advantages of Hardwired Control Unit Example: When pressing a key on a keyboard, the CPU must interrupt its Uses a large number of general-purpose registers to reduce memory
✔ Fast Execution: Uses combinational logic, making it faster than process to capture the keystroke. access.
microprogrammed control. [Link] CPU Utilization v. Hardwired Control Unit
✔ Efficient for Simple CPUs: Works well for RISC (Reduced Instruction Set --Efficient program control ensures that CPU cycles aren't wasted, Uses a hardwired control unit (faster than microprogrammed control).
Computing) architectures. improving system performance. Examples of RISC Processors: ARM, MIPS, SPARC, PowerPC
Disadvantages of Hardwired Control Unit --It prevents infinite loops or crashes due to execution errors.
✘ Difficult to Modify: Requires hardware changes for new instructions. [Link] Multi-tasking & Multi-threading CISC (Complex Instruction Set Computer) is a CPU design that uses a large
✘ Complex for CISC: Complex instruction sets require large control circuits, --In modern systems, program control enables multiple programs to run set of complex and variable-length instructions. It is designed to reduce
making the design hard to scale. simultaneously (context switching). the number of instructions per program by allowing a single instruction
--Example: Running a web browser while downloading a file. to perform multiple operations.
Key Mechanisms of Program Control Characteristics of CISC:
13. What is a microprogrammed control unit? How does it differ from a ✔ Instruction Sequencing → Ensures instructions are executed in the Complex and Variable-Length Instructions
hardwired control unit?. correct order. Supports many specialized instructions (e.g., string manipulation,
Ans- A Microprogrammed Control Unit is a type of control unit where control
signals are generated using a control memory (ROM) that stores ✔ Jump & Branch Control → Handles conditional and unconditional floating-point operations).
jumps. Instructions vary in length, making decoding more complex.
microinstructions. Instead of using fixed logic circuits (as in a hardwired control
unit), it uses microprograms to control the execution of instructions. ✔ Interrupt Handling → Manages external and internal interrupts. Memory-to-Memory Operations
Instructions can directly access memory, reducing the need for registers.
Working of a Microprogrammed Control Unit ✔ Pipeline Control → Ensures smooth execution in pipelined
[Link] Fetch & Decode:The CPU fetches the instruction and decodes the Reduces the number of instructions needed but slows execution.
architectures.
[Link] opcode determines the corresponding microprogram (sequence of Difficult Pipelining
✔ Exception Handling → Detects and responds to errors (e.g., divide by
microinstructions) stored in the Control Memory (CM). Variable-length instructions make pipelining less efficient.
zero).
[Link] Execution:The control unit fetches the first microinstruction May result in performance bottlenecks.
from the control [Link] microinstruction generates control signals to Fewer Registers
execute the instruction step by step.A Microprogram Counter (µPC) keeps track Uses fewer general-purpose registers since many operations work
of the next microinstruction. directly with memory.
[Link] & Completion:The CPU executes the microinstructions in sequence. Microprogrammed Control Unit
After execution, the next instruction cycle begins.
Uses a microprogrammed control unit (more flexible but slower than
Advantages of Microprogrammed Control Unit
hardwired).
✔ Easier to modify and update.
Examples of CISC Processors: Intel x86, AMD, VAX, IBM System/360
✔ Less complex than hardwired control.
✔ Useful for supporting complex instruction sets (CISC).
Disadvantages of Microprogrammed Control Unit
✘ Slower execution compared to hardwired control.
✘ Needs additional memory for storing microinstructions.