DEPARTMENT OF AVIONICS
ENGINEERING
COURSE : MICROWAVE ENGINEERING LAB
COURSE CODE : 308724
LAB NO. : 07
TITLE : Simulation of T-Junction Power Divider in Qucs
INSTRUCTOR : Mam Humail
SEMESTER : 07
SECTION : B
Member 1
NAME M Umar Aslam
REG NO 210701062
MARKS OBT.
PERFORMANCE
VIVA
DATE OF SUBMISSION :
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Abstract
This experiment models and simulates a three-port microstrip T-junction designed to split
input power in a 3:1 ratio (Port-2:Port-3). The divider was implemented on FR-4 with
quarter-wave transformer sections chosen to obtain an effective 1:3 power split while
preserving a 50 Ω input match. The simulation data from the provided project file were used
directly and analyzed to produce return-loss, transmission coefficients, and an energy
balance. Key results: at the design frequency 1.440 GHz the input return loss and
transmission magnitudes meet the intended asymmetrical split with small real-world losses.
Objective:
Design and simulate a lossless T-junction microstrip power divider that delivers 75% of
incident power to Port-2 and 25% to Port-3, with the input port well matched to 50 Ω at the
center frequency (1.44 GHz).
Background/Theory
A T-junction power divider is a three-port network where power division depends on the
characteristic impedances of the two output branches. For an asymmetrical split, the
characteristic impedances Z2 and Z3 are chosen so that:
⚫ The parallel combination of the branch impedances equals the source impedance (50 Ω),
ensuring input matching.
⚫ Quarter-wave transformer sections are often used to transform the branch impedances
to standard 50 Ω terminations while maintaining the power split ratio across the
operating frequency.
In practice, dielectric and conductor losses, fringing and connector effects cause small
deviations from ideal theoretical values. Quarter-wave transformers provide best
performance near the design frequency.
Equipment/Software
⚫ FR-4 substrate: thickness 1.6 mm, relative permittivity Er = 4.7, loss tangent = 0.02.
⚫ Microstrip dimensions and layout as summarized below.
⚫ Electromagnetic / circuit simulator.
Design Parameter:
The microstrip geometry used in the simulation:
⚫ Operating frequency : 1.4GHz
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⚫ Substrate: FR-4, h=1.6mm,Er=4.7, tan=0.02
⚫ Input line width: 2.80 mm
⚫ Port-2 (high-power branch): width = 2.44 mm, length = 29.6 mm
⚫ Port-3 (low-power branch): width = 0.72 mm, length = 30.8 mm
Design Schematic:
Simulated Results:
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Interpretation:
Input match: The input return loss of -23.624 dB implies an excellent match at 1.440 GHz (less
than 1% of input power reflected). This is far better than the conventional -10 dB criterion and
indicates the input sees a near-50 Ω termination at the design frequency.
Power split accuracy: The measured transmissions correspond to 67.8% to Port-2 and 23.8%
to [Link] is very close to the 75%/25% design target, especially when considering the
practical losses of FR-4. The theoretical ideal dB values for perfect 75% and 25% splits are -
1.25 dB and -6.02 dB respectively; the simulated values show small additional attenuation
(0.44 dB extra on the high-power arm and 0.21 dB extra on the low-power arm), attributable
to substrate and conductor losses.
Loss sources: The FR-4 substrate is relatively lossy at microwave frequencies; this and finite
conductor conductivity explain the 7.95% unaccounted power. Manufacturing tolerances and
microstrip discontinuities at the T-junction also introduce small mismatch and radiation
losses.
Design tradeoffs: Using FR-4 is economical but introduces measurable dissipation. For
improved efficiency, a low-loss substrate or optimized conductor thickness/grounding could
be used. Frequency sensitivity is also expected: quarter-wave transformers provide best
match near the center frequency only.
Conclusion:
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⚫ The T-junction microstrip divider, as modelled on FR-4, achieves the intended
asymmetrical division near 1.4 GHz with excellent input matching (S11= −23.624 dB).
⚫ Transmission levels (S21 = −1.687 dB --> 67.81% ; S31 = −6.234 dB --> 23.80%) closely
approximate the 3:1 split goal; small discrepancies are explained by dielectric and
conductor loss.
⚫ For applications that require minimal loss, redesigning on a lower-loss substrate (or
optimizing conductor geometry) is recommended.
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