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ARTS COLLEGE (AUTONOMOUS) TTDs TIRUPATI
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ARCHITECTURE OF INTEL 8085 MICROPROCESSOR
Features of 8085
Intel 8085 is an 8-bit, NMOS microprocessor.
It is a 40 pin I.C. package fabricated on a single LSI chip.
The Intel 8085 uses a single +5Vd.c. supply for its operation
Its clock speed is about 3 MHz
The clock cycle is of 320 ns.
It has 80 basic instructions and 256 opcodes.
Figure shows the functional block diagram of Intel 8085. It consists of three main
sections:
[1] Arithmetic and Logic Unit (ALU)
[2] Timing & Control Unit
[3] Set of registers.
Figure Architecture 8085 processor
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1. ALU (Arithmetic and Logic Unit):
As the name suggest, ALU i.e arithmetic and logic unit performs the following
arithmetic and logical operations:
iv. Logical OR
v. Logical EXCLUSIVE OR
vi. Complement (logical NOT)
vii. Increment (add 1)
viii. Decrement (Subtract 1)
ix. Left shift, Rotate left, Rorate Right
x. Clear, etc.
2. Timing & Control Unit:
It generates timing & control signals which are necessary for the execution of
instructions.
It controls data flow between CPU and peripherals including memory.
It provides status, control and timing signals which are required for the operation
of memory and I/O devices.
It controls entire operations of the microprocessor and peripherals connected to it.
Thus, it is seen that the control unit of the CPU acts as the brain of the computer
system.
3. Set of Registers:
Fig 1.2.1 shows the various registers of Intel 8085 which are used by the
microprocessor for temporary storage and manipulation of data and instructions.
Intel 8085 microprocessor has the following registers:
i. One 8-bit Accumulator (ACC) i.e register A
ii. Six 8-bit general purpose registers. These are B, C, D, E, H & L
iii. One 16-bit stack pointer, SP
iv. One 16-bit program Counter, PC
v. Instruction Register
vi. Temporary register
In addition to the above mentioned register the 8085 microprocessor contains a
set of five flipflops which serve as flag (or status flags). A flag is a flipflop which
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indicates some conditions which arises after execution of arithmetic and logical
instructions.
Accumulator:
The accumulator (register A) is an 8-bit register associated with ALU.
It is used to hold one of the operands of an arithmetic or logical operation.
It serves as one input to the ALU. The other operand for an arithmetic or logical
operation may be stored either in the memory or in one of the general-purpose
registers.
Final result of an arithmetic or logical operation is placed in the accumulator.
General Purpose Registers
The 8085 microprocessor contains six 8-bit general purpose registers. They are
B, C, D, E, H and L.
To hold 16-bit data a combination of two 8-bit registers can be employed which
known as register pairs.
The valid register pairs in 8051 are B-C, D-E and H-L. the programmer cannot
form the register pair by selecting any two registers of his choice.
The H-L pair is used to act as memory pointer and for this purpose it holds the
16- bit address of a memory location.
The general purpose registers and the accumulator are accessible to programmer.
He can store data in these registers during writing his program.
Program Counter (PC):
It is a 16-bit special purpose register used to hold the memory address of the next
instruction which is to be executed.
It keeps the track of memory addresses of the instructions in the program while
they are being executed.
The microprocessor increments the content of the program counter during the
execution of an instruction so that it points to the address of the next instruction
in the program at the end of the execution of an instruction.
Stack Pointer (SP):
It is a 16-bit special purpose register.
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“Stack is a sequence of memory location set aside by the programmer to
store/retrieve the content of accumulator, flags, program counter and general
purpose registers during the execution of a program.
Any portion of the memory can be used as stack. Since the stack works on LIFO
(last in first out) principle, its operation is faster compared normal store/ retrieve
of memory locations.
“The SP holds the address of the top element of data stored in the stack.
“The stack is defined and stack pointer is initialized by the programmer at the
beginning of a program which needs stack operation. Stack is also used by the
microprocessor. For example, it stores the contents of program counter when it
jumps to a subroutine using CALL instruction.
Instruction Register:
The instruction register holds the opcode (operation code or instruction code) of
the instruction which is being decoded and executed.
Temporary Register:
It is an 8-bit register associated with ALU. It holds data during an
arithmetic/logical operation.
It is used by microprocessor.
It is not accessible to programmer.
Flags (Program Status Word i.e. PSW):
The Intel 8085 microprocessor contains five flip-flops to serve as status flags.
The flip-flops are set or reset according to the conditions which arises during an
arithmetic or logical operation.
The five status flags of Intel 8085 are:
i. Carry flag (CS)
ii. Parity Flag (P)
iii. Auxiliary Carry Flag (AC)
iv. Zero Flag (Z)
v. Sign Flag (S)
In fig five bits indicates the five status flags and three bits are undefined. The
combination of these 8-bits is called Program Status Word (PSW). PSW and the
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accumulator are treated as a 16-bit unit for stack operation.
Figure Flag Register
Carry Flag (CS):
After execution of an arithmetic instruction if carry is produced, the carry flag CS
is set to 1. Otherwise it is 0.
The carry flag is set or reset in case of addition as well as subtraction.
After the addition of two 8-bit numbers, if the sum is larger than 8-bits, a carry is
produce; and the carry flag is set to 1.
In case of subtraction, if borrow occurs, the carry flag is set to 1.
The carry flag holds carry out of the most significant bit resulting from the
execution of an arithmetic operation.
Parity Flag (P):
The parity flag P is set to 1, if the result of an arithmetic or logical operation
contains even number of 1s.
It is reset i.e it is 0, if the result contains odd number of 1s.
Auxiliary Carry Flag (AC):
The auxiliary carry flag AC hold carry out of the bit number 3 to the bit number
4 resulting from the execution of an arithmetic operation.
The counting of bits starts from 0, and hence Bit No.3 is actually the fourth bit
from the least significant bit.
Zero Flag (Z):
The zero status flag Z is set to 1, if the result of an arithmetic or logical operation
is Zero otherwise it is set to 0.
Sign Flag (S):
The sign flag S is set to 1, if the result of an arithmetic or logical operation is
negative. If the result is positive, the sign flag is set to 0.
The sign flag has significance only when signed arithmetic operation is
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performed. To represent a signed numbed the most significant bit is reserved by
the programmer to represent the sign of a number.
In other words, the MSB is used as a sign bit.
If the number is negative, the sign bit is 1. For positive, sign bit is 0.
In case of 8-bit sign operation, the remaining 7 bits are used to represent the
magnitude of a number.
Data and Address bus:
The Intel 8085 is an 8-bit microprocessor. Its data bus is 8-bit wide and hence,
8bit of data can be transmitted in parallel from or to the microprocessor.
The Intel 8085 requires a 16-bit wide address bus as the memory addresses are of
16 bits.
The 8 most significant bits of the address are transmitted by the address bus, a-
bus (pins A8 to A15).
The least significant bits of address are transmitted by address/ data bus, AD-bus
(pins AD0 to AD7).
The address/ data bus transmits data and address at different moments. At a
particular moment it transmits either data or address. Thus AD-bus operates in
time shared mode.
This technique is known as multiplexing. First all 16-bit memory address is
transmitted by the microprocessor; the 8 MSBs of the address on A-bus and the 8
LSBs of the address on AD- bus. Thus effective width of address bus becomes
16
bit wide.
PIN OUT DIAGRAM OF 8085 MICROPROCESSOR:
The description of various pins is as follows
A8 – A15:
These are the output lines
These are the parallel address lines called as Address bus and are used for the
most significant bits of the memory address or 8 bits of I/O address.
AD0 – AD7:
Input / Output lines
These are time multiplexed address/data bus i.e. they serve dual purpose
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They are used for the least significant 8 bits of memory address or I/O address
during the first clock cycle of a machine cycle.
Again they are used for data during second and third clock cycles.
Figure Pinouts of 8085 processor
ALE:
It is an output pin.
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. is an address latch enable signal.
It
It goes high during first clock cycle of a machine cycle and enables the lower 8
bits of the address to be latched either in to the memory or external latch.
IO/M:
It is an output status signal which distinguishes whether the address is for
memory or I/O.
When it goes high the address on the address bus is for an I/O device.
When it goes low the address on the address bus is for a memory location.
S0, S1:
These are the output status signals sent by the microprocessor to distinguish the
various types of operations as given below.
Status codes for 8085,
S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
RD:
It is an output control signal.
It controls the READ operation.
When it goes low selected memory or I/O device is read
WR:
It is an output control signal.
It controls the WRITE operation.
When it goes low data on the data bus is written into the selected memory or I/O
location.
READY: (input)
It is used by the microprocessor to sense whether a peripheral is ready to transfer
data or not.
A slow peripheral may be connected to the microprocessor through READY line.
If READY is high peripheral is ready.
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. it is low microprocessor waits till it goes high.
If
HOLD (input):
It indicates that another device is requesting for the use of address and data bus.
After receiving the HOLD request microprocessor handover the controls of buses
to that devices as soon as current machine cycle is completed. Internal processing
may continue.
The processor regains the control over the buses after removal of HOLD signal.
When hold is acknowledged, address bus, data bus, RD, WR, and IO/M are tri-
stated.
HOLD is sampled in T2 Clock Cycle.
HLDA (output):
It is signal for HOLD acknowledgement.
It indicates that the HOLD request has been received.
After removal of a HOLD request the HLDA goes low.
The CPU takes over the buses half clock cycle after the HLDA goes low.
INTR (input):
It is an interrupt request signal.
Among interrupts it has lowest priority.
When it goes high the program counter does not increment its content.
The microprocessor suspends its normal sequence of instructions.
After completing the instruction at hand it attends the interrupting device.
The INTR line is sampled in the last state of the last machine cycle of an
instruction.
The INTR is enabled or disabled by software.
An interrupt is used by I/O device to transfer data to microprocessor without
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wasting time.
If CPU is in HOLD state or interrupt enable flip-flop is reset, an interrupt request
is not honored.
INTA: (output)
It is an interrupt acknowledgement sent by the microprocessor after INTR is
received.
RST 5.5, 6.5 and TRAP: (inputs)
These are the interrupts.
When an interrupt is recognized the next instruction is executed from a fixed
location in the memory as given below:
Interrupt Vectored location
TRAP 0024
RST5.5 002C
RST6.5 0034
RST7.5 003C
RST 7.5, RST6.5 and RST 5.5 are the restart interrupts. They cause an internal
restart to be automatically inserted, each them has programmable mask.
The TRAP has highest priority among the interrupts and it is non-maskable
interrupt.
The order of priority of interrupts is as follows: TRAP (Highest Priority)
o RST7.5
o RST6.5
o RST5.5
o INTR (Lowest Priority)
RESET IN: (input)
It resets the program counter to 0.
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It also resets interrupt enable and HLDA flip-flops.
It does not affect any other flag or register except the instruction register.
The CPU is held in reset condition as long as RESET is applied.
RESET OUT: (output)
It indicates that the CPU is being reset.
X1, X2: (input)
These are terminals connected to an external crystal oscillator which drives an
internal circuitry of the microprocessor to produce a suitable clock for the
operation of microprocessor.
CLK: (output)
It is a clock output for user, which can be used for other digital ICs. Its frequency
is same at which microprocessor operates.
SID: (input)
It is a data line for serial input.
The data on this line is loaded into the 7th nit of the accumulator when RIM
instruction is executed.
SOD: (output)
It is a data line for serial output. The 7th bit of the accumulator is output on SOD
line when SIM instruction is executed.
Vcc:
+5 volts supply.
Vss:
Ground reference.
INSTRUCTION FORMAT OF 8085
The 8085 have 74 basic instructions and 246 total instructions. The instruction set of 8085
is defined by the manufacturer Intel Corporation. Each instruction of 8085 has 1 byte
opcode. With 8-bit binary code, we can generate 256 different binary codes. In this, 246.
codes have been used for opcodes.
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Figure Instruction Format of 8085
[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-131]
The size of 8085 instructions can be 1 byte, 2 bytes or 3 bytes.
The 1-byte instruction has an opcode alone.
The 2 bytes instruction has an opcode followed by an eight-bit address or data.
The 3 bytes instruction has an opcode followed by 16 bit address or data. While
storing the 3 bytes instruction in memory, the sequence of storage is, opcode
first followed by low byte of address or data and then high byte of address or
data.
ADDRESSING MODES
Every instruction of a program has to operate on a data. The method of
specifying the data to be operated by the instruction is called Addressing. The 8085
has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
Immediate Addressing
In immediate addressing mode, the data is specified in the instruction itself. The
data will be apart of the program instruction. All instructions that have ‘I’ in their
mnemonics are of Immediate addressing type.
Eg. MVI B, 3EH - Move the data 3EH given in the instruction to B register.
Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction.
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The data will be in memory. In this addressing mode, the program instructions and data
can be stored in different memory blocks. This type of addressing can be identified by
16-bit address present in the instruction.
Eg. LDA 1050H - Load the data available in memory location 1050H in
accumulator.
Register Addressing
In register addressing mode, the instruction specifies the name of the register in
which the data is available. This type of addressing can be identified by register names
(such as ‘A’, ‘B’, … ) in the instruction.
Eg. MOV A, B -Move the content of B register to A register.
Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will be in memory and the
address will be in the register pair. This type of addressing can be identified by letter
‘M’ present in the instruction.
Eg. MOV A, M - The memory data addressed by HL pair is moved to A register.
Implied Addressing
In implied addressing mode, the instruction itself specifies the type of operation and
location of data to be operated. This type of instruction does not have any address,
register name, immediate data specified along with it.
Eg. CMA - Complement the content of accumulator.
STACK OPERATIONS
The stack is a group of memory location in the R/W memory (RAM) that is used for
temporary storage of data during the execution of a program.
Address of the stack is stored into the stack pointer register. The 8085 provide two
instructions PUSH & POP for storing information on the stack and reading it back.
Data in the register pairs stored on the stack by using the instruction PUSH.
Data is read from the stack by using the instruction POP.
PUSH & POP both instruction works with register pairs only.
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he storage and retrieval of the content of registers on the stack fallows
the LIFO (Last- In-First-Out) sequence.
Operation of the stack by PUSH and POP Instruction
2000LXI SP, 2099H ; this instruction define stack
2003LXI H, 42F2H ; this instruction store 42F2 in to the HL pair
2006PUSH H ; store HL pair on to the stack
2010POP H ; store data from top of the stack to HL pair
For PUSH H
The stack pointer is decremented by one to 2098H, and the contents of the h
register are copied to memory location [Link] stack pointer register is again
decremented by one to 2097H,and the contents of the L register are copied to memory
location [Link] contents of the register pair HL are not destroyed.
Figure PUSH H operation
For POP H
The contents of the top of the stack location shown by the stack pointer are
copied in the L register and the stack pointer register is incremented by one to 2098 H.
The contents of the top of the stack (now it is 2098H) are copied in the H register, and
the stack pointer is incremented by one. The contents of memory location 2097H and
2098 are not destroyed until some other data bytes are stored in these locations.
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Figure POP H operation
TIMING DIAGRAM:
A time diagram is a graphical representation. The 8085 instruction timing diagram
represents the execution time of each instruction in graphical format. Execution time is
given in T-states. The 8085 microprocessor has a set of control signals and data signals
that play an important role in the execution of instructions. In this article, I will explain
in detail what a timing diagram is and how to draw a timing diagram of different
instructions
Clock Signal: The time required to execute an instruction is called a clock cycle.
Machine Cycle: The time required to access memory or input/output devices is called a
machine cycle. The 8085 has 5 basic machine cycles i.e., load opcode, read from
memory, write to memory, read I/O, and write I/O.
T-State: A machine cycle and an instruction cycle take several clock periods. The
portion of an operation performed in one system clock period is called a T-state.
Control Signals: The control signal controls the operations. Common signals
are ALE (address block enable), RD (read), WR (write), and IO/M (input/output)
memory.
Machine Cycle of 8085
The 8085 microprocessor has 5 basic machine cycles. They are:
Opcode Fetch {4T- state}
Memory Read {3T- state}
Memory Write {3T- state}
I/O Read {3T- state}
I/O Write {3T- state}
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Opcode Fetch Machine Cycle of 8085
Each processor instruction has a one byte opcode.
Operation codes are stored in memory. Thus, the processor performs an opcode load
machine cycle to load the opcode from memory.
Thus, each instruction begins with a machine cycle of opcodes.
The time the processor takes to perform an opcode load cycle is 4T.
At this time, the first, 3T-states are used to load the opcode from memory, and the
remaining T-states are used for internal opcodes.
Opcode Fetch Cycle
Memory Read Machine Cycle of 8085
A memory read machine cycle is executed by the processor to read a data byte from
memory.
The processor takes 3T states to perform this cycle.
Instructions that have more than one byte word will use machine cycle after machine
cycle to load the opcode.
Memory Read Machine Cycle
Memory Write Machine Cycle of 8085
A write-to-memory machine cycle is executed by the processor to write a data byte to
memory.
The processor takes 3T states to perform this cycle.
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Instructions that have more than one byte word will use machine cycle after machine
cycle to load the opcode.
Memory Write Machine Cycle
I/O Read Machine Cycle
A reader I/O cycle is performed by the processor to read a data byte from an I/O port or peripheral that is I/O
mapped in the system.
The processor needs 3T states to execute this machine cycle.
I/O Read Machine Cycle
I/O Write Machine Cycle
A writer's I/O cycle is executed by the processor to write a data byte to an I/O port or peripheral that is I/O
mapped in the system.
The processor needs 3T states to execute this machine cycle.
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INTERRUPTS
Interrupt is a signal send by an external device to the processor, to the processor
to perform a particular task or work. Mainly in the microprocessor based system the
interrupts are used for data transfer between the peripheral and the microprocessor.
When a peripheral is ready for data transfer, it interrupts the processor by
sending an appropriate signal to the interrupt pin of the processor. If the processor
accepts the interrupt then the processor suspends its current activity and executes an
interrupt service subroutine to complete the data transfer between the peripheral and
processor. After executing the interrupt service routine the processor resumes its
current activity. This type of data transfer scheme is called interrupt driven data
transfer scheme.
Types of Interrupts
The interrupts are classified into software interrupts and hardware interrupts.
The software interrupts are program instructions. These instructions are inserted
at desired locations in a program. While running a program, lf a software
interrupt instruction is encountered, then the processor executes an interrupt
service routine (ISR).
The hardware interrupts are initiated by an external device by placing an
appropriate signal at the interrupt pin of the processor. If the interrupt is
accepted, then the processor executes an interrupt service routine (ISR).
Software Interrupts of 8085
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The software interrupts are program instructions. When the instruction is
executed, the processor executes an interrupt service routine stored in the vector
address of the software interrupt instruction. The software interrupts of 8085 are RST
0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.
Table Interrupt vector address
The software interrupt instructions are included at the appropriate (or required)
place in the main program. When the processor encounters the software instruction, it
pushes the content of PC (Program Counter) to stack. Then loads the Vector address in
PC and starts executing the Interrupt Service Routine (ISR) stored in this vector
address. At the end of ISR, a return instruction - RET will be placed. When the RET
instruction is executed, the processor POP the content of stack to PC. Hence the
processor control returns to the main program after servicing the interrupt. Execution
of ISR is referred to as servicing of interrupt. All software interrupts of 8085 are
vectored interrupts. The software interrupts cannot be masked and they cannot be
disabled.
Hardware Interrupts of 8085
An external device, initiates the hardware interrupts of 8O85 by placing an
appropriate signal at the interrupt pin of the processor. The processor keeps on
checking the interrupt pins at the second T -state of last machine cycle of every
instruction. If the processor finds a valid interrupt signal and if the interrupt is
unmasked and enabled, then the processor accepts the interrupt. The acceptance of the
interrupt is acknowledged by sending an INTA signal to the interrupted device.
The processor saves the content of PC (program Counter) in stack and then
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loads the vector address of the interrupt in PC. (If the interrupt is non-vectored, then
the interrupting device has to supply the address of ISR when it receives INTA signal).
It starts executing ISR in this address. At the end of ISR, a return instruction, RET will
be placed. When the processor executes the RET instruction, it POP the content of top
of stack to PC. Thus the processor control returns to main program after servicing
interrupt. The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and
INTR. Further the interrupts may be classified into vectored and non-vectored
interrupts.
Vectored Interrupt
In vectored interrupts, the processor automatically branches to the specific
address in response to an interrupt.
Non-Vectored Interrupt
But in non-vectored interrupts the interrupted device should give the address of
the interrupt service routine (ISR).
In vectored interrupts, the manufacturer fixes the address of the ISR to which
the program control is to be transferred.
The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085
are defined by INTEL.
The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the
interrupt signal has to make a low to high transition and then it has to remain
high until the interrupt is recognized.
The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5,
the interrupt signal has to make a low to high transition and it need not remain
high until it is recognized.
The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these
interrupts the interrupting signal should remain high, until it is recognized.
Maskable & Non-Maskable Interrupts:
The hardware vectored interrupts are classified into maskable and non-maskable
interrupts.
TRAP is non-maskable interrupt
RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.
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Masking is preventing the interrupt from disturbing the main program. When an interrupt
is masked the processor will not accept the interrupt signal. The interrupts can be
masked by moving an appropriate data (or code) to accumulator and then executing
SIM instruction. (SIM - Set Interrupt Mask). The status of maskable interrupts can be
read into accumulator by executing RIM instruction (RIM - Read Interrupt Mask).
All the hardware interrupts, except TRAP are disabled, when the processor is resetted.
They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
When an interrupt is disabled, it will not be accepted by the processor. (i.e.,
INTR, RST 5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and upon
hardware reset).
To enable (to allow) the disabled interrupt, the processor has to execute El
instruction (El-Enable Interrupt).
Interrupt Driven Data Transfer Scheme
The interrupt driven data transfer scheme is the best method of data transfer for
effectively utilizing the processor time. In this scheme, the processor first initiates the
I/O device for data transfer. After initiating the device, the processor will continue the
execution of instructions in the program. Also at the end of an instruction the
processor will check for a valid interrupt signal. If there is no interrupt, then the
processor will continue the execution.
When the I/O device is ready, it will interrupt the processor. On receiving an
interrupt signal, the processor will complete the current instruction execution and
saves the processor status in stack. Then the processor calls an interrupt service
routine (ISR) to service the interrupted device. At the end of ISR the processor status
is retrieved from stack and the processor starts executing its main program. The
sequence of operations for an interrupt driven data transfer scheme is shown in figure
below.
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Figure sequence of operations for an interrupt
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