PROGRAM
//Burglar alarm
module burglar_alarm (
input wire motion_sensor, // 1 = motion detected
input wire window_sensor, // 1 = window open
input wire reset, // 1 = reset alarm
output reg siren // 1 = alarm ON
);
always @(*) begin
if (reset)
siren = 0;
else if (motion_sensor || window_sensor)
siren = 1;
else
siren = 0;
end
endmodule
PROGRAM
//Image Process
module image_process(
input [1:0] mode,
output reg [7:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,
data_out6,data_out7,data_out8,data_out9,data_out10,data_out11,data_out12,dat
a_out13,data_out14,data_out15 );
reg [7:0] image_data_in [0:15];
reg [7:0] image_data_out [0:15];
initial begin
image_data_in [0]=8'b00000000;
image_data_in [1]=8'b11111111;
image_data_in [2]=8'b00010100;
image_data_in [3]=8'b11111111;
image_data_in [4]=8'b01111000;
image_data_in [5]=8'b11100011;
image_data_in [6]=8'b00101100;
image_data_in [7]=8'b11101011;
image_data_in [8]=8'b11110000;
image_data_in [9]=8'b110101101;
image_data_in [10]=8'b00000000;
image_data_in [11]=8'b11111111;
image_data_in [12]=8'b00000000;
image_data_in [13]=8'b11111111;
image_data_in [14]=8'b00000000;
image_data_in [15]=8'b11111111; end
integer i;
always @(*) begin
for (i = 0; i < 15; i = i + 1) begin
case (mode)
2'b00: image_data_out[i] = ~image_data_in[i]; // Invert
2'b01: image_data_out[i] = (image_data_in[i] > 128) ? 255 : 0; //
Threshold
2'b10: image_data_out[i] = image_data_in[i] + 50; // Brightness
default: image_data_out[i] = image_data_in[i];
endcase
end
data_out0=image_data_out[0];
data_out1=image_data_out[1];
data_out2=image_data_out[2];
data_out3=image_data_out[3];
data_out4=image_data_out[4];
data_out5=image_data_out[5];
data_out6=image_data_out[6];
data_out7=image_data_out[7];
data_out8=image_data_out[8];
data_out9=image_data_out[9];
data_out10=image_data_out[10];
data_out11=image_data_out[11];
data_out12=image_data_out[12];
data_out13=image_data_out[13];
data_out14=image_data_out[14];
data_out15=image_data_out[15];
end
endmodule
PROGRAM
//Tic Tac Toe
module gamecontroller(
input clk,
input rst,
input [3:0] cell_select,
input move,
output reg [1:0] current_player,
output reg [1:0] winner,
output reg game_over
);
reg [3:0] move_count;
reg [1:0] board [0:8];
initial begin
move_count = 0;
current_player = 2'b01;
game_over = 0;
winner = 2'b00;
board[0]=2'b00;
board[1]=2'b00;board[2]=2'b00;board[3]=2'b00;board[4]=2'b00;board[5]=2'b00
;board[6]=2'b00;board[7]=2'b00;board[8]=2'b00;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
move_count <= 0;
current_player <= 2'b01;
game_over <= 0;
winner <= 2'b00;
end
else if (move && !game_over) begin
if (board[cell_select] == 2'b00) begin
board[cell_select] <= current_player;
move_count <= move_count + 1;
if((board[0]==current_player &&
board[1]==current_player &&
board[2]==current_player)||(board[3]==current_player &&
board[4]==current_player &&
board[5]==current_player)||(board[6]==current_player &&
board[7]==current_player &&
board[8]==current_player)||(board[0]==current_player &&
board[3]==current_player &&
board[6]==current_player)||(board[1]==current_player &&
board[4]==current_player &&
board[7]==current_player)||(board[2]==current_player &&
board[5]==current_player &&
board[8]==current_player)||(board[0]==current_player &&
board[4]==current_player &&
board[8]==current_player)||(board[2]==current_player &&
board[4]==current_player && board[6]==current_player))
begin winner<=current_player; game_over<=1; end
if (!game_over)
current_player <= (current_player == 2'b01) ? 2'b10 : 2'b01;
end
end
end
endmodule
Test Bench Code
//Tic Tac Toe
module tictacgame;
// Inputs
reg clk;
reg rst;
reg [3:0] cell_select;
reg move;
// Outputs
wire [1:0] current_player;
wire [1:0] winner;
wire game_over;
// Instantiate the Unit Under Test (UUT)
gamecontroller uut (
.clk(clk),
.rst(rst),
.cell_select(cell_select),
.move(move),
.current_player(current_player),
.winner(winner),
.game_over(game_over)
);
initial begin
clk = 0; forever #5 clk = ~clk;
end
initial begin
rst = 1; move = 0; cell_select = 0;
#10 rst = 0;
#10 cell_select = 0; move = 1;
#10 move = 0;
#10 cell_select = 3; move = 1;
#10 move = 0;
#10 cell_select = 1; move = 1;
#10 move = 0;
#10 cell_select = 2; move = 1;
#10 move = 0;
#10 cell_select = 8; move = 1;
#10 move = 0;
#10 cell_select = 4; move = 1;
#10 move = 0;
#10 cell_select = 7; move = 1;
#10 move = 0;
#10 cell_select = 5; move = 1;
#10 move = 0;
end
endmodule
Test Bench Code
module testbench;
reg [1:0] mode;
wire [7:0] data_out0,data_out1,data_out2,data_out3,data_out4,
data_out5,data_out6,data_out7,data_out8,data_out9,data_out10,
data_out11,data_out12,data_out13,data_out14,data_out15;
image_process
IP(mode,data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,
data_out6,data_out7,data_out8,data_out9,data_out10,data_out11,data_out12,
data_out13,data_out14,data_out15);
initial begin
mode = 2'b00;
#10 ;
mode=2'b01;
#10;
mode=2'b10;
#10;
end
endmodule