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Program 1

The document contains two Verilog modules: a FIR filter and a traffic light controller. The FIR filter processes input data using predefined coefficients to produce an output, while the traffic light controller manages the states of traffic lights based on a timer. Both modules utilize a clock signal for operation and include reset functionality.

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bafel49471
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8 views3 pages

Program 1

The document contains two Verilog modules: a FIR filter and a traffic light controller. The FIR filter processes input data using predefined coefficients to produce an output, while the traffic light controller manages the states of traffic lights based on a timer. Both modules utilize a clock signal for operation and include reset functionality.

Uploaded by

bafel49471
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

PROGRAM

//FIR Filter
module fir_filter (
input clk,
input reset,
input [3:0] data_in,
output reg [7:0] data_out
);

parameter [7:0] h0 = 7'd1;


parameter [7:0] h1 = 7'd2;
parameter [7:0] h2 = 7'd3;
parameter [7:0] h3 = 7'd4;
reg [3:0] x0, x1, x2, x3;

always @(posedge clk or posedge reset) begin


if (reset) begin
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
data_out = 0;
end else begin

x3 = x2;
x2 = x1;
x1 = x0;
x0 = data_in;

data_out = (x0 * h0) + (x1 * h1) + (x2 * h2) + (x3 * h3);


end
end

endmodule
PROGRAM
//Traffic Light
module clkdiv(clk, clk1);
input clk;
output reg clk1;
reg [27:0]c;
initial c=28'b0;
always @(posedge clk)
begin
c=c+1;
clk1=c[27];
end
endmodule

module traffic(clk, east, west, north, south);


input clk;
output reg [4:0] east;
output reg [4:0] west;
output reg [4:0] north;
output reg [4:0] south;
integer timer;
always @(posedge clk)
begin
timer<=timer+1;
if(timer<2)begin
north<=5'b01011;
east<=5'b01001;
south<=5'b01001;
west<=5'b01001;end
else if(timer<10)begin
north<=5'b01100;end
else if(timer<12)begin
north<=5'b01001;
east<=5'b01011;end
else if(timer<20)begin
east<=5'b01100;end
else if(timer <22)begin
east<=5'b01001;
south<=5'b01011;end
else if (timer<30)begin
south<=5'b01101;end
else if(timer<32)begin
south<=5'b01001;
west<=5'b01011;end
else if(timer<40)begin
west<=5'b01100;end
else if(timer<45)begin
north<=5'b10001;
east<=5'b10001;
south<=5'b10001;
west<=5'b10001;end
else
begin
timer<=0;
end
end
endmodule

module traffic_light(clk,east,west,north,south);
input clk;
output [4:0] north;
output [4:0] south;
output [4:0] east;
output [4:0] west;
wire clk1;
clkdiv c1(clk,clk1);
traffic t1(clk1,east,west,north,south);
endmodule

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