ASYNCHRONOUS DRAMS
Information is stored in a dynamic memory cell in the form of a charge on a capacitor.
This charge can be maintained for only tens of milliseconds.
Since the cell is required to store information for a much longer time, its contents
must be periodically refreshed by restoring the capacitor charge to its full value.
This occurs when the contents of the cell are read or when new information is written
into it.
An example of a dynamic memory cell that consists of a capacitor, C, and a transistor,
T, is shown in below figure.
To store information in this cell, transistor T is turned on and an appropriate voltage is
applied to the bit line. This causes a known amount of charge to be stored in the
capacitor.
After the transistor is turned off, the capacitor begins to discharge.
The information stored in the cell can be retrieved correctly only if it is read before
the charge in the capacitor drops below some threshold value.
During a Read operation, the transistor in a selected cell is turned on.
A sense amplifier connected to the bit line detects whether the charge stored in the
capacitor is above or below the threshold value. If the charge is above the threshold,
the sense amplifier drives the bit line to the full voltage representing the logic value 1.
As a result, the capacitor is recharged to the full charge corresponding to the logic
value 1.
If the sense amplifier detects that the charge in the capacitor is below the threshold
value, it pulls the bit line to ground level to discharge the capacitor fully.
Thus, reading the contents of a cell automatically refreshes its contents.
Since the word line is common to all cells in a row, all cells in a selected row are read
and refreshed at the same time.
A 16 Megabit DRAM chip, configured as 2M × 8, is shown in Figure.
The cells are organized in the form of a 4K x 4K array. The 4096 cells in each row are
divided into 512 groups of 8.
A row can store 512 bytes of data. 12 address bits are needed to select a row.
Another 9 bits are needed to specify a group of 8 bits in the selected row.
Thus, a 21-bit address is needed to access a byte in this memory.
The high order 12 bits constitute the row address and the low order 9 bits of the address
constitute column address of a byte.
During a Read or a Write operation, the row address is applied first.
It is loaded into the row address latch in response to a signal pulse on the Row
Address Strobe (RAS) input of the chip.
Then a Read operation is initiated, in which all cells on the selected row are read and
refreshed.
Shortly after the row address is loaded, the column address is applied to the address
pins and loaded into the column address latch under control of the Column Address
Strobe (CAS) signal.
The information in this latch is decoded and the appropriate group of 8 Sense/Write
circuits are selected.
If the R/W’ control signal indicates a Read operation, the output values of the selected
circuits are transferred to the data lines, D7-0.
For a Write operation, the information on the D7-0 lines is transferred to the selected
circuits.
This information is then used to overwrite the contents of the selected cells in the
corresponding 8 columns.
During a Read or a Write operation, the row address is applied first.
It is loaded into the row address latch in response to a signal pulse on the Row
Address Strobe (RAS) input of the chip.
Then a Read operation is initiated, in which all cells on the selected row are read and
refreshed.
Shortly after the row address is loaded, the column address is applied to the address
pins and loaded into the column address latch under control of the Column Address
Strobe (CAS) signal.
The information in this latch is decoded and the appropriate group of 8 Sense/Write
circuits are selected.
If the R/W’ control signal indicates a Read operation, the output values of the selected
circuits are transferred to the data lines, D7-0.
For a Write operation, the information on the D7-0 lines is transferred to the selected
circuits.
This information is then used to overwrite the contents of the selected cells in the
corresponding 8 columns.