HCL Analog design training
Name: Roll no:
Instructions
1. The test is for 120 minutes and 60 is the maximum score
2. Allowed to use calculators, books or web
3. Write answers in the sheets and return them. Box all your final answers in your scripts
4. Feel free to make reasonable assumptions and state them
5. Approximations are acceptable within reasonable limits
Questions
1. In the circuit shown, the flop exhibits non-zero tcq , tsu and thold .
(a) Find the maximum frequency of operation in terms of the gate delays, clock skew and
flop parameters
3 marks
(b) Find the criteria to not have hold time failures
3 marks
B
D Q A D Q
Qb Qb
tskew
clk
Figure 1: Problem: 1
2. A PTAT bias is constructed as shown.
(a) Develop a table(as shown below) to define the function performed by each capacitor
(C1 to C8 ) shown. Explain briefly
10 marks
(b) What would be the benefit/bug if gate of M16 was connected to V1 instead of V2 ?
1
3 marks
Capacitor Useful/Nuisance Function
C1
C2
C8
Vdd
M3 M5 M10 M11
M4
C6
C5
M7
M8 M9 M12 M13 M14
V4
C4
V3
V5 M15
V7
V1 V6 I<N:0>
M6 M2 V2 M0 M18
M1
C3 VR M17 M21<N:0>
M16 C1 C8
C2 C7
R1
M19 M20<N:0>
Figure 2: Problem: 2
3. In the amplifier circuit shown, the W
L
ratio of the transistors are indicated. The character-
istic of NMOS and PMOS are respectively Id = 125µ W L
(Vgs − 0.5)2 and Id = 45µ W
L
(|Vgs | −
2
0.5) . Vdd = 2V
10uA Vdd
2 1
V3
M2
M3
1 1 Vin
M0 M1
Vo
M6
V1 V2
1uF
M4 M5 20f 1
1 1
Figure 3: Problem: 3
(a) For Vin = 1.2V , Find the quiescent voltages at V1 , V2 & V3
2
2 marks
(b) Find the input common-mode range
3 marks
(c) If only NMOS suffers from channel length modulation with λ = 0.1V −1 ,
Evaluate the DC gain
2 marks
Find the pole-splitting capacitor required to keep phase margin better than 60◦
3 marks
(d) For Vin = 1.2V , Find the systematic input referred offset (there will be offset due to
the channel length modulation in NMOS)
4 marks
(e) How does the systematic input referred offset(found in previous part) change for Vin =
0.3V
2 marks
4. For the LDO shown, Vref = 1V
(a) Find the total current consumption from Vdd when Vdd = 2.5V and IL = 1mA
2 marks
(b) Find the total current consumption from Vdd when Vdd = 2.0V and IL = 1mA
3 marks
(c) If you force Vo = 2.2V with an external voltage source when Vdd = 2.5V and IL = 1mA,
what will be the total current consumption from Vdd ?
4 marks
Vdd
5u 5u
Vb
1 10
Vo
Vref
500k
5u IL
500k
Figure 4: Problem: 4
3
5. Evaluate the correctness of the following statements. Provide explanation
INL of thermometric DAC is better compared to binary weighted DAC
2 marks
To get rid of hold-time failures in digital circuits, it is sufficient to design circuits with
flops that exhibit zero hold-time
2 marks
In a current steering DAC, the offset voltage of the output buffer results in DAC’s
offset error
1 mark
It is normal to have rail-to-rail input stage for the DAC output buffer. In these buffers,
the systematic input offset varies with the DAC output voltage due to the switch over
between the P and N input stages. This results in gain error
2 marks
Pass transistor does not contribute much to the LDO’s output noise due to its large
size
2 mark
6. In the cascode amplifier shown,
(a) Find the total input referred noise [Hint: Find N1 noise PSD contribution to output
and divide it by stage gain squared, Repeat this for N2 and R and sum all of them]
3 marks
(b) Plot the input referred noise components from N1 and N2 . Explian why they behave
this way.
2 marks
(c) What modification would an output capacitor (Co ) do to the previous part?
2 marks
Vo
N2
V1
N1
Vin
C1
Figure 5: Problem: 6