PIC 16F877 ARCHITECTURE

The PIC16FXX is a family of low-cost, high-performance, CMOS, fully-static, 8-

bitmicrocontrollers.

All PIC microcontrollers employ an advanced RISC architecture. The

PIC16FXXmicrocontroller family has enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The two-stage instruction pipeline allows all
instructions to execute in a single cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction set) are available. Also, a large register
set helps to achieve a very high performance. . The PIC 16FXX uses Harvard architecture, in
which, program and data are accessed from separate memories using separate buses.

This improves bandwidth over traditional Von Neumann architecture where program and
data may be fetched from the same memory using the same bus. Separating program and data
buses further allows instructions to be sized differently than 8-bit wide data words.
Instruction opcodes are 14-bits wide making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions
execute in a single cycle (200 ns@ 20MHz) except for program branches.4

Block diagram of PIC 16F87X Microcontroller

The PIC 16F87X devices have a 13-bit program counter capable of addressing an
8KX14program memory space. The PIC 16FF876/877 devices have 8Kx 14 words of Flash
program memory .The RESET vector is at 0000h and the Interrupt vector is at 0004h.

REGISTER FILE STRUCTURE

In PIC Microcontrollers the Register File consists of two parts namely

a) General Purpose Register File b) Special Purpose Register File

a) General Purpose Register File:

The general purpose register file is another name for the microcontroller’s RAM .
Data can be written to each 8-bit location updated and retrieved any number of times.

b) Special Purpose Register File:

The special function register file consists of input, output ports and control registers
used to configure each 8-bit port either as input or output. It contains registers that provide
the data input and data output to a chip resources like Timers, Serial Ports and Analog to
Digital converter and also the registers that contains control bits for selecting the mode of
operation and also enabling or disabling its operation.
CPU REGISTERS

The CPU registers are used in the execution of the instruction of the PIC microcontroller. The
PIC PIC16F877 Microcontroller has the following registers.

1. Working Register-W (Similar to Accumulator)

2. Status Register

3. FSR – File Select Register (Indirect Data memory address pointer)

4. INDF

5. Program Counter

1. Working Register: Working Register is used by many instructions as the source of an

operand. It also serves as the destination for the result of instruction execution and it is
similar to accumulator in other µcs and µps
2. Status Register: This is an 8-bit register which denotes the status of ALU after any
arithmetic operation and also RESET status and the bank select bits for the data memory.

C: Carry/borrow bit

DC: Digit carry/borrow bit

Z: Zero bit

NOT_PD : Reset Status bit (Power-down mode bit)

NOT_TO : Reset Status bit (tme- out bit)

RPO: Register bank Select The bits 7 and 6 of Status Register are unused by 16c6x/7x. The
‘C’ bit is set when two 8-bit operands are added together and a 9-bit result occurs. This 9-bit
is placed in the carry bit.

The DC or Digit carry bit indicates that a carry from the lower 4 bits occurred during an 8-bit
addition. Example: 0011 1000 0011 1000 0111 0000 Here DC=1 as a result of the carry from
the bit 3 to the bit 4 position.8

The Z or zero bits is affected by the execution of arithmetic or logic instructions. The reset
status bits NOT_TO and NOT_PD are used in conjunction with PIC’s sleep mode. The micro
controller can put itself to sleep mode to save power during intervals when it has nothing to
do. It can be reset by any of three kinds. Upon reset the CPU can check these two reset status
bits to determine which kind of event resettled it and then respond accordingly. The Register
bank select bit RPO is used to select either bank or bank. When RPO=0,select Bank 0,
RPO=1, select Bank 1.

Example: bcf STATUS, RPO ; Select bank 0

bsf STATUS, RPO ; Select bank 1.

3. FSR – (File Select Register):

It is the pointer used for indirect addressing. In the indirect addressing mode the 8-
bitregister file address is first written into FSR. It is a special purpose register that serves as
an address pointer to any address throughout the entire register file.

[Link] – (Indirect File): It is not a physical register addressing but this INDF will cause
indirect addressing. Any instructions using the INDF register actually access the register
pointed to by the FSR.

5 .PROGRAM COUNTER

PIC PIC16F877A has a 13 bit program counter in which PCL is the lower 8-bits of
the PC and PCLATH is the write buffer for the upper 5 bits of the PC.
PCLATH (program counter Latch can be read or from or written to without affecting the
Program Counter(PC).The upper 3 bits of PCLATH remain zero. It is only when PCL is
written to that PCLATH is automatically written into the PC at the same time.

I/O Ports

Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O ports They are
PORT A, PORT B, PORT C , PORT D and PORT E.

PORT A: Port A is a 6-bit wide bi-directional port. Its data direction register is TRISA setting
TRISA bit to 1 will make the corresponding PORT A Pin an input. Clearing a TRIS a bit will
make the corresponding pin as an output.

PORT B: Port B is an 8-bit wide, bi-directional port. Four of the PORT B pins RB 7 – RB4
have an interrupt-on- change feature. Only the pins configured as inputs can cause this
interrupt to occur.

PORT C: Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register determine the
function of its pins. Similar to other ports, a logic one 1 in the TRISC Register configures the
appropriate port pin as an input.

PORT D: Port D is an 8-bit wide bi-directional port. In addition to I/O port, Port D also
works as8-bit parallel slave port or microprocessor port. When control bit PSPMODE
(TRISE:4) is set.

PORT E: It is a 3-bit bi-directional port. Port E bits are multiplexed with analog inputs of
ADCand they serve as control signals (RD , WR, CS) for parallel slave port mode of
operation.

TIMER MODULES:

There are three completely independent Timers available in PIC 16F8XX Microcontrollers.

They are♦ Timer 0♦ Timer1 and♦ Timer2

CCP (Capture-Compare –PWM)

The CCP module(s) can operate in one of three modes 16-bit capture, 16-bit
compare,or up to 10-bit Pulse Width Modulation (PWM)

Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL register
pair. The capture event can be programmed for either the falling edge, rising edge, fourth
rising edge, or sixteenth rising edge of the CCPx pin.

Compare mode compares the TMR1H:TMR1L register pair to the CCPRxH:CCPRxL

register pair. When a match occurs, an interrupt can be generated and the output pin CCPx
can be forced to a given state (High or Low) and Timer1 can be reset. This depends on
control bitsCCPxM3:CCPxM0.
 PWM mode compares the TMR2 register to a 10-bit duty cycle register
(CCPRxH:CCPRxl<5:4>) as well as to an 8-bit period register (PR2).

INTERRUPTS:

The PIC16F8XX family has up to 11 sources of interrupt. The interrupt control

register (INTCON) records individual interrupt requests in flag bits. It also has individual and
global interrupt enable bits.

WATCH DOG TIMER:

• Watchdog Timer (WDT) can be helpful to automatically reset the system whenever a
timeout occurs.
• System reset is required for preventing failure of the system in a situation of a
hardware fault or program error.

INSTRUCTION REGISTER AND DECODER

To execute an instruction, the processor copies the instruction code from the program
memory into the instruction register (IR). It can then be decoded (interpreted) by
the instruction decoder, which is a combinational logic block which sets up the processor
control lines as required.
These control lines are not shown explicitly in the block diagram, as they go to all
parts of the chip, and would make it too complicated.
In the PIC, the instruction code includes the operand (working data), which may be a
literal value or register address. For example, if a literal (a number) given in the instruction is
to be loaded into the working register (W), it is placed on an internal data bus and the
W register latch enable lines are activated by the timing and control logic.

OSCILLATOR START UP TIMER:

An oscillator start-up timer (OST) is a module used by some microcontrollers to keep
the device reset until the crystal oscillator is stable. When a crystal oscillator starts up, its
frequency is not constant, which causes the clock frequency to be non-constant. This would
cause timing errors, leading to many problems. An oscillator start-up timer ensures that the
device only operates when the oscillator generates a stable clock frequency

POWER UP TIMER:
The Power-up Timer (PWRT) provides a nominal 72-millisecond delay after a Power
On Reset (POR), Brown Out Reset (BOR), or after the Master Clear Pin External Reset
(MCLR) pin reset is initiated. The PWRT operates on a dedicated internal RC oscillator. The
device is kept in reset as long as the PWRT has not timed out. The PWRT allows the Vdd
voltage of the PIC®MCU to rise to an acceptable level before operating.
POWER ON RESET:
When a PIC® MCU is first powered up, it will run through some defined hardware
functions internally to prepare the MCU for proper operation. This can include the oscillator
start-up and power stabilization. The Power On Reset will hold the device in reset while these
operations happen. It prevents the device from running any software until a minimum level
Vdd voltage threshold is met and the oscillator is stable.

BROWN OUT RESET (BOR)

BOR will hold a PIC® MCU in reset when the Vdd drops below a brown out
threshold voltage. Not all devices have BOR, but most do, and some have multiple voltage
thresholds to select from. Between a BOR and Power On Reset the whole range of startup
voltages can be covered to protect for proper operation after a power drop at the Vdd line. It
is also recommended that the Power-Up Timer (PWRT) be enabled to increase the delay in
returning from a BOR event.
 MEMORY ORGANIZATION OF PIC 16F877A
Memory of the PIC16F877 divided into 3 types of memories:

• Program Memory - A memory that contains the program (which we had written), after
we've burned it. As a reminder, Program Counter executes commands stored in the
program memory, one after the other.
• Data Memory – This is RAM memory type, which contains a special registers like SFR
(Special Faction Register) and GPR (General Purpose Register). The variables that we
store in the Data Memory during the program are deleted after we turn of the micro.

These two memories have separated data buses, which makes the access to each one of
them very easy.

• Data EEPROM (Electrically Erasable Programmable Read-Only Memory) - A

memory that allows storing the variables as a result of burning the written program.

Each one of them has a different role. Program Memory and Data Memory two memories
that are needed to build a program, and Data EEPROM is used to save data after the
microcontroller is turn off.

Program Memory and Data EEPROM they are non-volatile memories, which store the
information even after the power is turn off. These memories called Flash Or EEPROM. In
contrast, Data Memory does not save the information because it needs power in order to
maintain the information stored in the chip.

PIC16F87XA Program Memory

The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x
14 bit program memory space. This memory is used to store the program after we burn it to
the microcontroller. The PIC16F876A/877A devices have 8K words x 14 bits of Flash
program memory that can be electrically erased and reprogrammed. Each time we burn
program into the micro, we erase an old program and write a new one.

PIC16F876A/877A program memory map and stack

Program Counter (PC) keeps track of the program execution by holding the address of the
current instruction. It is automatically incremented to the next instruction during the current
instruction execution.

The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space
is not part of either program or data space and the stack pointer is not readable or writable. In
the PIC microcontrollers, this is a special block of RAM memory used only for this purpose.

The CALL instruction is used to jump to a subroutine, which must be terminated with the
RETURN instruction. CALL has the address of the first instruction in the subroutine as its
operand. When the CALL instruction is executed, the destination address is copied to the PC.
The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’ed in the event of a RETURN, RETLW or a RETFIE
instruction execution.
The stack operates as a circular buffer. This means that after the stack has been PUSHed
eight times, the ninth push overwrites the value that was stored from the first push. The tenth
push overwrites the second push (and so on).

Each time the main program execution starts at address 0000 - Reset Vector. The address
0004 is “reserved” for the “interrupt service routine” (ISR).

If we plan to use an interrupt, our program will begin after the Interrupt Vector; and if not we
can start to write from the beginning of the Reset Vector.

Here is a code where we use interrupt:

ORG 0x000 ; processor reset vector

goto main ; go to beginning of main program
ORG 0x004 ; interrupt vector location
movwf w_temp ; save off current W register contents
movf STATUS,w ; move status register into W register
movwf status_temp ; save off contents of STATUS register
.
.
RETFIE

main
Some of the memory is divided into the pages that are designed for write/burn the program
into them; the remaining memory (Stack, Interrupt Vector, and Reset Vector) is hardware
registers.

Attention!
Program Memory is divided into the pages, where the program is stored. Data Memory is
divided into the banks. The banks are located inside the RAM, where the special registers and
the data located.

PIC16F87XA Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose
Registers and the Special Function Registers. Number of banks may vary depending on the
microcontroller; for example, micro PIC16F84 has only two banks.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for
the Special Function Registers. Above the Special Function Registers are General Purpose
Registers, implemented as static RAM. While program is being executed, it is working with
the particular bank. The default bank is BANK0.

To access a register that is located in another bank, one should access it inside the program.
There are special registers which can be accessed from any bank, such as STATUS register.
 ADDRESSING MODES
Direct and Indirect addressing

Direct Addressing: Using this method we are accessing the registers directly by detecting
location inside Data Memory from Opcode and by selecting the bank using bits RP1 and RP0
of the STATUS register.

Indirect Addressing: To implement indirect addressing, a File Select Register (FSR) and
indirect register (INDF) are used. In addition, when using this method we choose bank using
bit IRP of the STATUS register. Indirect addressing treated like a stack pointer, allowing
much more efficient work with a number of variables. INDF register is not an actual register
(it is a virtual register that is not found in any bank).

There is SFR (Special Function Register) - special registers of RAM, and there is FSR (File
Select Register).The following figure shows the two addressing methods:

Pin diagram of PIC16F877A

To the left you can see the direct addressing method, where the bank selection is made by RP
bits and the referencing is made directly from memory Opcode by using the variable name.

To the right you can see the indirect addressing method, where the bank selection is made by
IRP bit and accessing the variable by pointer FSR.

Let’s explore the differences between the 2 methods:

We want to assign number 5 to the variable TEMP located at address 0X030. In the first row
of each example, we will define the variable TEMP at the address 0X030.

Example of direct addressing:

1. TEMP Equ 0x030

2. Movlw 5
3. Movwf TEMP

It's easy to understand, that direct addressing method means working directly with the
variables. In the second line we put the number 5 into the working register W, and in the line
3, the content of the W passes to the TEMP variable .

Example of indirect addressing:

1. TEMP Equ 0x030
2. Movlw 0x030
3. Movwf FSR
4. Movlw 5
5. Movwf INDF

In the second line, we put a value into the W register. In the third line, the value passes to the
FSR register, and from this moment FSR points to the address of the TEMP variable. In the
fourth line, the number 5 passes to the W register, and in the fifth line, we move the contents
of W register (which is 5) to the INDF. In fact INDF performs the following: it takes the
number 5 and puts it in the address indicated by FSR register.

PIC16F87XA Data EEPROM

The data EEPROM and Flash program memory is readable and writable during normal
operation (over the full VDD range). This memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the Special Function Registers.

There are six SFRs used to read and write to this memory:

1. EECON1
2. EECON2
3. EEDATA
4. EEDATH
5. EEADR
6. EEADRH

When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and
EEADR holds the address of the EEPROM location being accessed. These devices have 128
or 256 bytes of data EEPROM (depending on the device), with an address range from 00h to
FFh. On devices with 128 bytes, addresses from 80h to FFh are unimplemented.

A few important points about Data EEPROM memory:

• It lets you save data DURING programming

• The data is saved during the “burning” process
• You can read the data memory during the programming and use it
• The use is made possible with the help of SFR

At this point there is no need to learn how to use this memory with special registers, because
there are functions (writing and reading) that are ready.

Instruction Set
It has been already mentioned that microcontrollers differs from other integrated circuits.
Most of them are ready for installation into the target device just as they are, this is not the
case with the microcontrollers. In order that the microcontroller may operate, it needs precise
instructions on what to do. In other words, a program that the microcontroller should execute
must be written and loaded into the microcontroller. This chapter covers the commands
which the microcontroller "understands". The instruction set for the 16FXX includes 35
instructions in total. Such a small number of instructions is specific to the RISC
microcontroller because they are well-optimized from the aspect of operating speed,
simplicity in architecture and code compactness. The only disadvantage of RISC architecture
is that the programmer is expected to cope with these instructions.

INSTRUCTION DESCRIPTION OPERATION FLAG CLK *

Data Transfer Instructions

Move constant to
MOVLW k k -> w 1
W

MOVWF f Move W to f W -> f 1

MOVF f,d Move f to d f -> d Z 1 1, 2

CLRW Clear W 0 -> W Z 1

CLRF f Clear f 0 -> f Z 1 2

f(7:4),(3:0) ->
SWAPF f,d Swap nibbles in f 1 1, 2
f(3:0),(7:4)

Arithmetic-logic Instructions

Add W and
ADDLW k W+k -> W C, DC, Z 1
constant

ADDWF f,d Add W and f W+f -> d C, DC ,Z 1 1, 2

Subtract W from
SUBLW k k-W -> W C, DC, Z 1
constant

SUBWF f,d Subtract W from f f-W -> d C, DC, Z 1 1, 2

Logical AND with

ANDLW k W AND k -> W Z 1
W with constant

Logical AND with

ANDWF f,d W AND f -> d Z 1 1, 2
W with f

Logical AND with

ANDWF f,d W AND f -> d Z 1 1, 2
W with f

Logical OR with
IORLW k W OR k -> W Z 1
W with constant

Logical OR with
IORWF f,d W OR f -> d Z 1 1, 2
W with f
 Logical exclusive
XORLW k OR with W with W XOR k -> W Z 1 1, 2
constant

Logical exclusive
XORWF f,d W XOR f -> d Z 1
OR with W with f

INCF f,d Increment f by 1 f+1 -> f Z 1 1, 2

DECF f,d Decrement f by 1 f-1 -> f Z 1 1, 2

Rotate left f
RLF f,d through CARRY C 1 1, 2
bit

Rotate right f
RRF f,d through CARRY C 1 1, 2
bit

COMF f,d Complement f f -> d Z 1 1, 2

Bit-oriented Instructions

BCF f,b Clear bit b in f 0 -> f(b) 1 1,2

BSF f,b Set bit b in f 1 -> f(b) 1 1,2

Program Control Instructions

Test bit b of f.
Skip the
Skip if f(b)
BTFSC f,b following 1 (2) 3
=0
instruction if
clear.

Test bit b of f.
Skip the
Skip if f(b)
BTFSS f,b following 1 (2) 3
=1
instruction if
set.

DECFSZ f,d Decrement f. 1 (2) 1, 2, 3

f-1 -> d skip
Skip the
 following if Z = 1
instruction if
clear.

Increment f.
Skip the
f+1 -> d skip
INCFSZ f,d following 1 (2) 1, 2, 3
if Z = 0
instruction if
set.

GOTO k Go to address k -> PC 2

PC -> TOS,
CALL k Call subroutine 2
k -> PC

Return from
RETURN TOS -> PC 2
subroutine

Return with k -> W, TOS

RETLW k 2
constant in W -> PC

Return from TOS -> PC,

RETFIE 2
interrupt 1 -> GIE

Other instructions

TOS -> PC,

NOP No operation 1
1 -> GIE

0 -> WDT, 1
Clear watchdog
CLRWDT -> TO, 1 -> TO, PD 1
timer
PD

0 -> WDT, 1
Go into sleep
SLEEP -> TO, 0 -> TO, PD 1
mode
PD

Table 9-1 16Fxx Instruction Set

*1 When an I/O register is modified as a function of itself, the value used will be that value
present on the pins themselves. *2 If the instruction is executed on the TMR register and if
d=1, the prescaler will be cleared. *3 If the PC is modified or test result is logic one (1), the
instruction requires two cycles.

Data Transfer Instructions

Data Transfer within the microcontroller takes place between working register W (called
accumulator) and a register which represents any location of internal RAM regardless of
whether it is about special function or general purpose registers. First three instructions move
literal to W register (MOVLW stands for move Literal to W), move data from W register to
RAM and from RAM to W register (or to the same RAM location with change on flag Z
only). Instruction CLRF clears f register, whereas CLRW clears W register. SWAPF
instruction swaps nibbles within f register (one nibble contains four bits).

Arithmetic-logic Instructions
Similar to most microcontrollers, PIC supports only two arithmetic instructions- addition and
subtraction. Flags C, DC, Z are automatically set depending on the results of addition or
subtraction. The only exception is the flag C. Since subtraction is performed as addition with
negative value, the flag C is inverted after subtraction. It means that the flag C is set if it is
possible to perform operation and cleared if the larger number is subtracted from smaller one.
Logic one (1) of the PIC is able to perform operations AND, OR, EX-OR, inverting (COMF)
and rotation (RLF and RRF). Instructions which rotate a register actually rotate its bits
through the flag C by one bit left (toward bit 7) or right (toward bit 0). The bit shifted from
the register is moved to the flag C which is automatically moved to the bit on the opposite
side of the register.

Bit-oriented Instructions
Instructions BCF and BSF clear or set any bit in memory. Although it seems to be a simple
operation, it is not like that. CPU first reads the entire byte, changes one its bit and rewrites
the whole byte to the same location.

Program Control Instructions

The PIC16F887 executes instructions GOTO, CALL, RETURN in the same way as all other
microcontrollers do. A difference is that stack is independent from internal RAM and has 8
levels. The ‘RETLW k’ instruction is identical to RETURN instruction, with exception that a
constant defined by instruction operand is written to the W register prior to return from
subroutine. This instruction enables Lookup tables to be easily created by creating a table as
a subroutine consisting of ‘RETLWk‘ instructions, where the literals ‘k’ belong to the table.
The next step is to write the position of the literals k (0, 1, 2, 3...n) to W register and call the
subroutine (table) using the CALL instruction. Table below consists of the following literals:
k0, k1, k2...kn.

Main movlw 2 ;write number 2 to accumulator

call Lookup ;jump to the lookup table
Lookup addwf PCL,f ;add accumulator and program current address (PCL)
retlw k0 ;return from subroutine (accumulator contains k0)
retlw k1 ;...
retlw k2 ;...
... ;...
... ;...
retlw kn ;return from subroutine (accumulator contains kn)

Legend

f - Any memory location (register);

W - Working register (accumulator);

b - Bit address within an 8-bit register;

d - Destination bit; [label] - Set of 8 characters indicating start of particular address in the
program;

C - Carry/Borrow bit of the STATUS register;

DC - Digit Carry bit of the STATUS register; and

Z - Zero bit of the STATUS register.

ADDLW - Add literal and W

Syntax: ADDLW k

Description: The content of the register W is added to the 8-bit literal k. The result is stored
in the W register.

Operation: (W) + k -> W

Operand: 0 ≤ k ≤ 255

Status affected: C, DC, Z

Number of cycles: 1

EXAMPLE:

ADDLW 0x15
Before instruction execution: W=0x10
After instruction: W=0x25
C=0 (the result is not greater than 0xFF, which means that Carry has not occurred).

ADDWF - Add W and f

Syntax: ADDWF f, d

Description: Add the contents of the W and f registers. If d = w or d = 0 the result is stored
in the W register.
If d = f or d = 1 the result is stored in register f.

Operation: (W) + (f) -> d

Operand: 0 ≤ f ≤ 127, d [0,1]

Status affected: C, DC, Z

Number of cycles: 1

EXAMPLE 1:

ADDWF REG,w
Before instruction execution: W = 0x17
REG = 0xC2
After instruction: W = 0xD9
REG = 0xC2
C=0 (No carry occurs, i.e. the result is maximum 8-bit long).

EXAMPLE 2:

ADDWF INDF,f
Before instruction execution: W=0x17
FSR = 0xC2 Register at address 0xC2 contains the value 0x20
After instruction: W = 0x17
FSR=0xC2, Register at address 0xC2 contains the value 0x37

ANDLW - AND literal with W

Syntax: [label] ANDLW k

Description: The content of the register W is AND’ed with the 8-bit literal k. It means that
the result will contain one (1) only if both corresponding bits of operand are ones (1). The
result is stored in the W register.

Operation:(W) AND k -> W

Operand: 0 ≤ k ≤ 255

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] ANDLW 0x5F
Before instruction execution: W = 0xA3 ; 1010 0011 (0xA3)
; 0101 1111 (0x5F)
------------------
After instruction: W = 0x03 ; 0000 0011 (0x03)
Z = 0 (result is not 0)

EXAMPLE 2:

....
[label] ANDLW 0x55
Before instruction execution: W = 0xAA ; 1010 1010 (0xAA)
; 0101 0101 (0x55)
------------------
After instruction: W = 0x00 ; 0000 0000 (0x00)
Z = 1( result is 0)

ANDWF - AND W with f

Syntax: [label] ANDWF f,d

Description: AND the W register with register f.

If d = w or d = 0, the result is stored in the W register.

If d = f or d = 1, the result is stored in register f.

Operation: (W) AND (f) -> d Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] ANDWF REG,f
Before instruction execution: W = 0x17, REG = 0xC2 ; 0001 0111 (0x17)
; 1100 0010 (0xC2)
------------------
After instruction: W = 0x17, REG = 0x02 ; 0000 0010 (0x02)

EXAMPLE 2:

....
[label] ANDWF FSR,w
Before instruction execution: W = 0x17, FSR = 0xC2 ; 0001 0111 (0x17)
; 1100 0010 (0xC2)
------------------
After instruction: W = 0x02, FSR = 0xC2 ; 0000 0010 (0x02)

BCF - Bit Clear f

Syntax: [label] BCF f, b
Description: Bit b of register f is cleared.

Operation: (0) -> f(b)

Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7

Status affected: -

Number of cycles: 1

EXAMPLE 1:

....
[label] BCF REG,7
Before instruction execution: REG = 0xC7 ; 1100 0111 (0xC7)
After instruction: REG = 0x47 ; 0100 0111 (0x47)

EXAMPLE 2:

....
[label] BCF INDF,3
Before instruction execution: W = 0x17
FSR = 0xC2
Register at address (FSR)contains the value 0x2F
After instruction: W = 0x17
FSR = 0xC2
Register at address (FSR)contains the value 0x27

BSF - Bit set f

Syntax: [label] BSF f,b

Description: Bit b of register f is set.

Operation: 1 -> f (b)

Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7

Status affected: -

Number of cycles: 1

EXAMPLE 1:

....
[label] BSF REG,7
Before instruction execution: REG = 0x07 ; 0000 0111 (0x07)
After instruction: REG = 0x87 ; 1000 0111 (0x87)

EXAMPLE 2:

....
[label] BSF INDF,3
Before instruction execution: W = 0x17
FSR = 0xC2
Register at address (FSR)contains the value 0x20
After instruction: W = 0x17
FSR = 0xC2
Register at address (FSR)contains the value 0x28

BTFSC - Bit test f, Skip if Clear

Syntax: [label] BTFSC f, b

Description: If bit b of register f is 0, the next instruction is discarded and a NOP is executed
instead, making this a two-cycle instruction.

Operation: Discard the next instruction if f(b) = 0

Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7

Status affected: -

Number of cycles: 1 or 2 depending on bit b

EXAMPLE:

....
LAB_01 BTFSC REG,1 ; Test bit 1 of REG
LAB_02 .... ; Skip this line if bit = 1
LAB_03 .... ; Jump here if bit = 0
Before instruction execution: The program counter was at address LAB_01.
After instruction:
- if bit 1 of REG is cleared, program counter points to address LAB_03.
- if bit 1 of REG is set, program counter points to address LAB_02.

BTFSS - Bit test f, Skip if Set

Syntax: [label] BTFSS f, b

Description: If bit b of register f is 1, the next instruction is discarded and a NOP is

executed instead, making this a two-cycle instruction.

Operation: Discard the next instruction if f(b) = 1

Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7

Status affected: -

Number of cycles: 1 or 2 depending on bit b

EXAMPLE:

....
LAB_01 BTFSS REG,3 ; Test bit 3 of REG
LAB_02 .... ; Skip this line if bit = 0
LAB_03 .... ; Jump here if bit = 1
Before instruction execution: The program counter was at address LAB_01
After instruction:
- if bit 3 of REG is cleared, program counter points to address LAB_03.
- if bit 3 of REG is cleared, program counter points to address LAB_02.

CALL - Calls Subroutine

Syntax: [label] CALL k

Description: Calls subroutine. First the address of the next instruction to execute is pushed
onto the stack. It is the PC+1 address. Afterwards, the subroutine address is written to the
program counter.

Operation: (PC) + 1 -> (Top Of Stack - TOS) k -> PC (10 : 0), (PCLATH (4 : 3)) -> PC (12
: 11)

Operand: 0 ≤ k ≤ 2047

EXAMPLE:

....
LAB_01 CALL LAB_02 ; Call subroutine LAB_02
 ....
....
LAB_02 ....
Before instruction execution: PC = address LAB_01
TOS (top of stack) = x
After instruction: PC = address LAB_02
TOS (top of stack) = LAB_01

CLRF - Clear f
Syntax: [label] CLRF f

Description: The content of register f is cleared and the Z flag of the STATUS register is
set.

Operation: 0 -> f

Operand: 0 ≤ f ≤ 127

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] CLRF TRISB
Before instruction execution: TRISB=0xFF
After instruction: TRISB=0x00
Z=1

EXAMPLE 2:

Before instruction execution: FSR=0xC2

Register at address 0xC2 contains the value 0x33
After instruction: FSR=0xC2
Register at address 0xC2 contains the value 0x00
Z=1

CLRW - Clear W
Syntax: [label] CLRW

Description: Register W is cleared and the Z flag of the STATUS register is set.

Operation: 0 -> W

Operand: -
Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] CLRW
Before instruction: W=0x55
After instruction: W=0x00
Z=1

CLRWDT - Clear Watchdog Timer

Syntax: [label] CLRWDT

Description: Resets the watchdog timer and the WDT prescaler. Status bits TO and PD are
set.

Operation: 0 -> WDT 0 -> WDT prescaler 1 -> TO 1 -> PD

Operand: -

Status affected: TO, PD

Number of cycles: 1

EXAMPLE :

....
[label] CLRWDT
Before instruction execution: WDT counter = x
WDT prescaler = 1:128
After instruction: WDT counter = 0x00
WDT prescaler = 0
TO = 1
PD = 1
WDT prescaler = 1: 128

COMF - Complement f
Syntax: [label] COMF f, d
Description: The content of register f is complemented (logic zeros (0) are replaced by ones
(1) and vice versa).

If d = w or d = 0 the result is stored in W. If d = f or d = 1 the result is stored in register f.

Operation: (f) -> d

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] COMF REG,w
Before instruction execution: REG = 0x13 ; 0001 0011 (0x13)
; complementing
------------------
After instruction: REG = 0x13 ; 1110 1100 (0xEC)
W = 0xEC

EXAMPLE 2:

....
[label] COMF INDF, f
Before instruction execution: FSR = 0xC2
Register at address (FSR)contains the value 0xAA
After instruction: FSR = 0xC2
Register at address (FSR)contains the value 0x55

DECF - Decrement f
Syntax: [label] DECF f, d

Description: Decrement register f by one. If d = w or d = 0, the result is stored in

the W register.

If d = f or d = 1, the result is stored in registerf.

Operation: (f) - 1 -> d

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] DECF REG,f
Before instruction execution: REG = 0x01
Z=0
After instruction: REG = 0x00
Z=1

EXAMPLE 2:

....
[label] DECF REG,w
Before instruction execution: REG = 0x13
W = x, Z = 0
After instruction: REG = 0x13
W = 0x12, Z = 0

DECFSZ - Decrement f, Skip if 0

Syntax: [label] DECFSZ f, d

Description: Decrement register f by one. If d = w or d = 0, the result is stored in

the W register.

If d = f or d = 1, the result is stored in register f. If the result is 0, then a NOP is executed

instead, making this a two-cycle instruction.

Operation: (f) - 1 -> d

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: -

Number of cycles: 1 or 2 depending on the result.

EXAMPLE 1:

....
MOVLW .10
MOVWF CNT ;10 -> CNT
Loop ......
 ...... ;Instruction block
......
DECFSZ CNT,f ; decrement REG by one
GOTO Loop ; Skip this line if = 0
LAB_03 ....... ; Jump here if = 0

In this example, instruction block is executed as many times as the initial value of the
variable CNT is, which in this example is 10.

GOTO - Unconditional Branch

Syntax: GOTO k

Description: Unconditional jump to the address k.

Operation: (k) -> PC(10:0), (PCLATH(4:3)) -> PC(12:11)

Operand: 0 ≤ k ≤ 2047

Status affected: -

Number of cycles: 2

EXAMPLE :

....
LAB_00 GOTO LAB_01 ; Jump to LAB_01
.....
.....
LAB_01 ..... ; Program continues from here
Before instruction execution: PC = LAB_00 address
After instruction: PC = LAB_01 address

INCF - Increment f
Syntax: INCF f, d

Description: Increment register f by one.

If d = w or d = 0, the result is stored in register W. If d = f or d = 1, the result is stored in

register f.

Operation: (f) + 1 -> d Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:
....
[label] INCF REG,w
Before instruction execution: REG = 0x10
W = x, Z = 0
After instruction: REG = 0x10
W = 0x11, Z = 0

EXAMPLE 2:

....
[label] INCF REG,f
Before instruction execution: REG = 0xFF
Z=0
After instruction: REG = 0x00
Z=1

INCFSZ - Increment f, Skip if 0

Syntax: [label] INCFSZ f, d

Description: Register f is incremented by one. If d = w or d = 0, the result is stored in

register W. If d = f or d = 1, the result is stored in register f. If the result is 0, then a NOP is
executed instead, making this a two-cycle instruction.

Operation: (f) + 1 -> d

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: -

Number of cycles: 1 or 2 depending on the result.

EXAMPLE :

....
LAB_01 INCFSZ REG,f ; Increment REG by one
LAB_02 ....... ; Skip this line if result is 0
LAB_03 ....... ; Jump here if result is 0

The content of program counter Before instruction execution, PC= LAB_01address. The
content of REG after instruction, REG = REG+1. If REG=0, the program counter points to
the address of label LAB_03. Otherwise, the program counter points to address of the next
instruction, i.e. to LAB_02 address.

IORLW - Inclusive OR literal with W

Syntax:IORLW k
Description: The content of the W register is OR’ed with the 8-bit literal k. The result is
stored in register W.

Operation: (W) OR (k) -> W

Operand: 0 ≤ k ≤ 255

Status affected: -

Number of cycles: 1

EXAMPLE :

....
[label] IORLW 0x35
Before instruction execution: W = 0x9A
After instruction: W = 0xBF
Z=0

IORWF - Inclusive OR W with f

Syntax: [label] IORWF f, d

Description: The content of register f is OR’ed with the content of W register.

If d = w or d = 0, the result is stored in the W register. If d = f or d = 1, the result is stored in
register f.

Operation: (W) OR (f) -> d

Operand: 0 ≤ f ≤ 127, d -> [0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] IORWF REG,w
Before instruction execution: REG = 0x13,
W = 0x91
After instruction: REG = 0x13,
W = 0x93 Z = 0

EXAMPLE 2:

....
[label] IORWF REG,f
Before instruction execution: REG = 0x13,
 W = 0x91
After instruction: REG = 0x93,
W = 0x91 Z = 0

MOVF - Move f
Syntax: MOVF f, d

Description: The content of register f is moved to a destination determined by the operand d.

If d = w or d = 0, the content is moved to register W. If d = f or d = 1, the content remains in
register f. Option d = 1 is used to test the content of register f because this instruction affects
the Z flag of the STATUS register.

Operation: (f) -> d

Operand: 0 ≤ f ≤ 127, d -> [0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] MOVF FSR,w
Before instruction execution: FSR=0xC2
W=0x00
After instruction: W=0xC2
Z=0

EXAMPLE 2:

....
[label] MOVF INDF,f
Before instruction execution: W=0x17
FSR=0xC2, register at address 0xC2 contains the value 0x00
After instruction: W=0x17
FSR=0xC2, register at address 0xC2 contains the value 0x00,
Z=1

MOVLW - Move literal to W

Syntax: MOVLW k

Description: 8-bit literal k is moved to register W.

Operation: k -> (W)

 Operand: 0 ≤ k≤ 255

Status affected: -

Number of cycles: 1

EXAMPLE 1:

....
[label] MOVLW 0x5A
After instruction: W=0x5A

EXAMPLE 2:

Const equ 0x40

[label] MOVLW Const
Before instruction execution: W=0x10
After instruction: W=0x40

MOVWF - Move W to f
Syntax: MOVWF f

Description: The content of register W is moved to register f. Operation: (W) -> f

Operand: 0 ≤ f ≤ 127

Status affected: -

Number of cycles: 1

EXAMPLE 1:

....
[label] MOVWF OPTION_REG
Before instruction execution: OPTION_REG=0x20
W=0x40
After instruction: OPTION_REG=0x40
W=0x40

EXAMPLE 2:

....
[label] MOVWF INDF
Before instruction execution: W=0x17
FSR=0xC2, register at address 0xC2 contains the value 0x00
After instruction: W=0x17
FSR=0xC2, register at address 0xC2 contains the value 0x17

NOP - No Operation
Syntax: NOP

Description: No operation.

Operation: -

Operand: -

Status affected: -

Number of cycles: 1

EXAMPLE :

....
[label] NOP ; 1us delay (oscillator 4MHz)
Before instruction execution: PC = x
After instruction: PC = x + 1

RETFIE - Return from Interrupt

Syntax: RETFIE

Description: Return from subroutine. The value is popped from the stack and loaded to the
program counter. Interrupts are enabled by setting the bit GIE of the INTCON register.

Operation: TOS -> PC, 1 -> GIE

Operand: -

Status affected: -

Number of cycles: 2

EXAMPLE :

....
[label] RETFIE
Before instruction execution: PC = x
GIE (interrupt enable bit of the SATUS register) = 0
After instruction: PC = TOS (top of stack)
GIE = 1

RETLW - Return with literal in W

Syntax: RETLW k

Description: 8-bit literal k is loaded into register W. The value from the top of stack is
loaded to the program counter.

Operation: (k) -> W; top of stack (TOP) -> PC

Operand: -

Status affected: -

Number of cycles: 2

EXAMPLE :

....
[label] RETLW 0x43
Before instruction execution: W = x
PC = x
TOS (top of stack) = x
After instruction: W = 0x43
PC = TOS (top of stack)
TOS (top of stack) = TOS - 1

RETURN - Return from Subroutine

Syntax: RETURN

Description: Return from subroutine. The value from the top of stack is loaded to the
program counter. This is a two-cycle instruction.

Operation: TOS -> program counter PC.

Operand: -

Status affected: -

Number of cycles: 2

EXAMPLE :

....
[label] RETURN
Before instruction execution: PC = x
TOS (top of stack) = x
After instruction: PC = TOS (top of stack)
TOS (top of stack) = TOS - 1

RLF - Rotate Left f through Carry

Syntax: RLF f, d

Description: The content of register f is rotated one bit to the left through the Carry flag.
If d = w or d = 0, the result is stored in register W. If d= f or d = 1, the result is stored in
register f.

Operation: (f(n)) -> d(n+1), f(7) -> C, C -> d(0);

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: C

Number of cycles: 1

EXAMPLE 1:

....
[label] RLF REG,w
Before instruction execution: REG = 1110 0110
C=0
After instruction: REG = 1110 0110
W = 1100 1100
C=1

EXAMPLE 2:

....
[label] RLF REG,f
Before instruction execution: REG = 1110 0110
C=0
After instruction: REG = 1100 1100
C=1

RRF - Rotate Right f through Carry

Syntax: RRF f, d

Description: The content of register f is rotated one bit right through the Carry flag.
If d = w or d = 0, the result is stored in register W. If d = for d = 1, the result is stored in
register f.
Operation: (f(n)) -> d(n-1), f(0) -> C, C -> d(7);

Operand: 0 ≤ f ≤ 127, d -> [0,1]

Status affected: C

Number of cycles: 1

EXAMPLE 1:

....
[label] RRF REG,w
Before instruction execution: REG = 1110 0110
W=x
C=0
After instruction: REG = 1110 0110
W = 0111 0011
C=0

EXAMPLE 2:

....
[label] RRF REG,f
Before instruction execution: REG = 1110 0110, C = 0
After instruction: REG = 0111 0011, C = 0

SLEEP - Enter Sleep mode

Syntax: SLEEP

Description: The processor enters sleep mode. The oscillator is stopped. PD bit (Power
Down) of the STATUS register is cleared. TO bit of the same register is set. The WDT and
its prescaler are cleared.

Operation: 0 -> WDT, 0 -> WDT prescaler, 1 -> TO, 0 -> PD

Operand: -
Status affected: TO, PD

Number of cycles: 1

EXAMPLE :

....
[label] SLEEP
Before instruction execution: WDT counter = x
WDT prescaler = x
After instruction: WDT counter = 0x00
WDT prescaler = 0
TO = 1
PD = 0

SUBLW - Subtract W from literal

Syntax: SUBLW k

Description: The content of register W is subtracted from the literal k. The result is stored in
register W.

Operation: k - (W) -> W

Operand: 0 ≤ k ≤ 255

Status affected: C, DC, Z

Number of cycles: 1

EXAMPLE :

....
[label] SUBLW 0x03
Before instruction execution: W = 0x01, C = x, Z = x
After instruction: W = 0x02, C = 1, Z = 0 result is positive

Before instruction execution: W = 0x03, C = x, Z = x

After instruction: W = 0x00, C = 1, Z = 1 result is 0

Before instruction execution: W = 0x04, C = x, Z = x

After instruction: W = 0xFF, C = 0, Z = 0 result is negative

SUBWF - Subtract W from f

Syntax: SUBWF f, d
Description: The content of register W is subtracted from register f. If d = w or d = 0, the
result is stored in register W. If d = f or d = 1, the result is stored in register f. Operation: (f)
- (W) -> d

Operand: 0 ≤ f ≤ 127, d [0,1]

Status affected: C, DC, Z

Number of cycles: 1

EXAMPLE :

....
[label] SUBWF REG,f
Before instruction execution: REG = 3, W = 2, C = x, Z = x
After instruction: REG = 1, W = 2, C = 1, Z = 0 result is positive

Before instruction execution: REG = 2, W = 2, C = x, Z = x

After instruction: REG = 0, W = 2, C = 1, Z = 1 result is 0

Before instruction execution: REG = 1, W = 2, C = x, Z = x

After instruction: REG = 0xFF, W = 2, C = 0, Z = 0 result is negative

SWAPF - Swap Nibbles in f

Syntax: SWAPF f, d

Description: The upper and lower nibbles of register f are swapped. If d = w or d = 0, the
result is stored in register W. If d = f or d = 1, the result is stored in register f.

Operation: f(0:3) -> d(4:7), f(4:7) -> d(0:3);

Operand: 0 ≤ f ≤ 127, d [0,1]

Status affected: -

Number of cycles: 1

EXAMPLE 1:

....
[label] SWAPF REG,w
Before instruction execution: REG=0xF3
After instruction: REG=0xF3
W = 0x3F
EXAMPLE 2:

....
[label] SWAPF REG,f
Before instruction execution: REG=0xF3
After instruction: REG=0x3F

XORLW - Exclusive OR literal with W

Syntax: XORLW k

Description: The content of register W is XOR’ed with the 8-bit literal k . The result is
stored in register W.

Operation: (W) .XOR. k -> W

Operand: 0 ≤ k ≤ 255

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] XORLW 0xAF
Before instruction execution: W = 0xB5 ; 1011 0101 (0xB5)
; 1010 1111 (0xAF)
------------------
After instruction: W = 0x1A ; 0001 1010 (0x1A)
Z=0

EXAMPLE 2:

Const equ 0x37

[label] XORLW Const
Before instruction execution: W=0xAF ; 1010 1111 (0xAF)
Const = 0x37 ; 0011 0111 (0x37)
-------------------------------
After instruction: W = 0x98 ; 1001 1000 (0x98)
Z=0

XORWF - Exclusive OR W with f

Syntax: XORWF f, d
Description: The content of register f is XOR’ed with the content of register W. A bit of
result is set only if the corresponding bits of operands are different. If d = w or d = 0, the
result is stored in register W. If d = f or d = 1, the result is stored in register f.

Operation: (W) .XOR. k -> d

Operand: 0 ≤ f ≤ 127, d[0,1]

Status affected: Z

Number of cycles: 1

EXAMPLE 1:

....
[label] XORWF REG,f
Before instruction execution: REG = 0xAF, W = 0xB5 ; 1010 1111 (0xAF)
; 1011 0101 (0xB5)
------------------
After instruction: REG = 0x1A, W = 0xB5 ; 0001 1010 (0x1A)

EXAMPLE 2:

....
[label] XORWF REG,w
Before instruction execution: REG = 0xAF, W = 0xB5 ; 1010 1111 (0xAF)
; 1011 0101 (0xB5)
------------------
After instruction: REG = 0xAF, W = 0x1A ; 0001 1010 (0x1A)

In addition to the preceding instructions, Microchip has also introduced some other
instructions. To be more precise, they are not instructions as such, but macros supported by
MPLAB. Microchip calls them "Special Instructions" since all of them are in fact obtained by
combining already existing instructions.

EQUIVALENT STATUS
INSTRUCTION DESCRIPTION
INSTRUCTION AFFECTED

ADDCF f,d Add with carry BTFSC INCF STATUS,C

Add with Digit

ADDDCF f,d BTFSC INCF STATUS,DC
Carry

B k Branch GOTO
BC k Branch on Carry BTFSC GOTO STATUS,C

Branch on Digit
BDC k BTFSC GOTO STATUS,DC
Carry

Branch on No
BNC k BTFSS GOTO STATUS,C
Carry

Branch on No
BNDC k BTFSS GOTO STATUS,DC
Digit Carry

BNZ k Branch on No Zero BTFSS GOTO STATUS,Z

BZ k Branch on Zero BTFSC GOTO STATUS,Z

CLRC Clear Carry BCF STATUS,C

CLRDC Clear Digit Carry BCF STATUS,DC

CLRZ Clear Zero BCF STATUS,Z

MOVFW f Move File to W MOVF

SETC f Set Carry BSF STATUS,C

SETDC Set Digit Carry BSF STATUS,DC

SETZ Set Zero BSF STATUS,Z

SKPC Skip on Carry BTFSS STATUS,C

Skip on Digit
SKPDC BTFSS STATUS,DC
Carry

SKPNC Skip on No Carry BTFSC STATUS,Z

 Skip on No Digit
SKPNDC BTFSC STATUS,DC
Carry

SKPNZ Skip on Non Zero BTFSC STATUS,Z

SKPZ Skip on Zero BTFSS STATUS,Z

Subtract Carry
SUBCF f, d BTFSC DECF STATUS,C
from File

Subtract Digit
SUBDCF f, d BTFSC DECF STATUS,DC
Carry from File

TSTF f Test File MOVF

CPU REGISTERS
1. Status register
2. PORT register
3. TRIS register
4. INTCON register
5. OPTION register
6. PIE1
7. PIR1
8. PIE2
9. PIR2
[Link] Register

The INTCON Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

GIE EEIE T0IE INTE RBIE T0IF INTF RBIF

Introduction: The PIC16F84 has four interrupt sources:
1. Termination of writing data to EEPROM
2. TMR0 interrupt caused by timer overflow
3. Interrupt during alteration on RB4, RB5, RB6 and RB7 pins of port B.
4. External interrupt from RB0/INT pin of microcontroller

Generally speaking, each interrupt source has two bits associated with it. One enables
interrupts, and the other detects when interrupts occur. There is one common bit called GIE
which can be used to disable or enable all interrupts simultaneously. This bit is very useful
when writing a programme because it allows for all interrupts to be disabled for a period of
time, so that execution of some important part of a programme would not be interrupted.
When the instruction which resets GIE bit is executed (GIE=0, all interrupts disallowed), any
interrupt that remained unsolved would be ignored. Interrupts which remained unsolved and
were ignored, are processed when GIE bit (GIE=1, all interrupts allowed) would be cleared.
When interrupt was answered, GIE bit was cleared so that any additional interrupts would be
disabled, return address was pushed onto stack and address 0004h was written in programme
counter - only after this does replying to an interrupt begin! After interrupt is processed, the
bit which caused an interrupt must be cleared, or the interrupt routine would automatically be
processed over again during a return to the main programme.

Interrupt Request Mechanism

The INTCON Register:

The INTCON register is a readable and writable register which contains the various enable
bits for all interrupt sources.

The meaning of INTCON might be (though this is only me thinking) INTurrpt CONtrol
register. I have serached the net for the source of this acronym with no avail; if you find it
please e-mail me.

Anyway, interrupt flag bits get set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

This register is used to configure the interrupt control logic circuitry. Bits 0 to 6 are used to
configure the interrupt enable/disable statuses and the interrupt flags for the four interrupt
sources. No interrupt to the CPU will result unless the GIE bit is set. The GIE bit is the bit
INTCON<7> and when set, enables all un-masked interrupts.
 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
R = Readable bit
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF W= Writable bit
U = Unimplemented bit, read as ‘0’
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -n= Value at POR reset

bit 7:
GIE: The Global Interrupt Enable bit is like the master switch for all the different interrupts.
SETTING this bit will enable all the interrupts to function, CLEARING this bit will
disable ALL interrupts.
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6
EEIE: EE Write Complete Interrupt Enable bitEE Write Complete Interrupt Enable bit
allows an interrupt to occur when a write operation to the EEPROM has completed. This
interrupt may be required in your programs because it takes time for a write operation to
EEPROM to complete. This interrupt capability allows the program to do other things instead
of halting while the write operation is accomplished. SETTING the EEIE bit allows an
interrupt when the write to EEPROM operation is complete; CLEARING the bit disables the
interrupt.
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt

bit 5
T0IE: The TMR0 Overflow Interrupt Enable bit allows an interrupt when the TMR0 counter
overflows from 255 (0xff) to 0 (0x00). Setting this bit allows the TMR0 interrupt,
CLEARING this bit will disable the interrupt.
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4:
INTE: The RB0/INT External interrupt Enable bit allows an interrupt from a clocking signal
applied to pin RB0. Whether the interrupt occurs on the rising or falling edge of this clocking
signal is determined by the state of the INTEDG bit in the OPTION_REG. SETTING the
INTE bit allows an interrupt from the signal on RB0, CLEARING this bit disables the
interrupt.
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt

bit 3:
RBIE: The Port Change Interrupt Enable bit allows an interrupt when there is a change of
state on pins RB7, RB6, RB5 and RB4 on PORTB. SETTING the RBIE bit will allow the
PORTB change interrupts; CLEARING this bit disables the interrupts.
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2:
T0IF: The TMR0 Overflow Interrupt Flag bit is used by the device to indicate if the interrupt
was the result of a TMR0 overflow. As you may have noticed, an interrupt code will be
triggered by any of the different resources available on the MCU. It is up to you, the
programmer, to determine through your software code which of the resources generates the
interrupt. Flag bits allow you to make that determination. In this case, when a TMR0
overflow interrupt occurs, the TOIF flag bit is SET. Early in the interrupt service routine (the
subroutine program that you will write to deal with an interrupt) , a check of the various flags
is accomplished - in this case, the TOIF flag, and if it is SET, a TMR0 interrupt occurred and
the program will take the desired action. You reset the TMR0 interrupt by CLEARING the
TOIF bit. If you fail to reset the TOIF bit, additional TMR0 interrupts will occur immediately
once the interrupt service routine has completed.
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow

bit 1:
INTF: The RB0/INT External Interrupt Flag bit is used by the device to indicate if the
interrupt was the result of a clocking signal on the RB0 pin. You will need to check the state
of INTF in the interrupt service routine to determine if the interrupt occurred because of a
clock signal on RB0. At completion of the interrupt service routine, the INTF pin must be
CLEARED to prevent unintended interrupts.
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur

BIT 0:
RBIF: The Port Change Interrupt Flag bit is used likewise by the device to indicate if the
interrupt was the result
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state.
 Fig. The PIC 16F84’s interrupt logic.
PIE1 Register
The PIE1 register contains the individual enable bits for the peripheral
interrupts. The structure of this register is shown below.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
• Bit 7 (PSPIE): this bit is the Parallel Slave Port Read/Write Interrupt Enable bit
(1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt)

• Bit 6 (ADIE): A/D Converter Interrupt Enable bit which control the analog to
digital converter interrupt.
(1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt)

• Bit 5 (RCIE): USART Receive Interrupt Enable bit which control the USART
data reception interrupt.
(1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt)

• Bit 4 (TXIE): USART Transmit Interrupt Enable bit that control USART data
transmission.
(1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt)

• Bit 3 (SSPIE): Synchronous Serial Port Interrupt Enable bit that control SSP data
interrupt.
(1 = Enables the SSP interrupt

0 = Disables the SSP interrupt)

• Bit 2 (CCP1IE): CCP1 Interrupt Enable bit which control the capture-compare-
pulse width modulation interrupt.
(1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt)

• Bit 1 (TMR2IE): TMR2 to PR2 Match Interrupt Enable bit.

(1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt)

 • Bit 0 (TMR1IE): TMR1 Overflow Interrupt Enable bit that control the overflow
interrupt of timer 1 module.
(1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt)

PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral interrupt.
The structure of PIR1 register is given below.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

• Bit 7 (PSPIF): Parallel Slave Port Read/Write Interrupt Flag bit.
(1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred)

• Bit 6 (ADIF): A/D Converter Interrupt Flag bit that control the interrupt flag for
that analog to digital converter.
(1 = An A/D conversion completed

0 = The A/D conversion is not complete)

• Bit 5 (RCIF): USART Receive Interrupt Flag bit.

(1 = The USART receive buffer is full

0 = The USART receive buffer is empty)

• Bit 4 (TXIF): USART Transmit Interrupt Flag bit.

(1 = The USART transmit buffer is empty

0 = The USART transmit buffer is full)

• Bit 3 (SSPIF): Synchronous Serial Port (SSP) Interrupt Flag bit that control the
SSP interrupt flag in a PIC.
(1 = The SSP interrupt condition has occurred and must be cleared in software
before returning from the Interrupt Service Routine. The conditions that will
set this bit are:

• SPI – A transmission/reception has taken place.

• I2C Slave – A transmission/reception has taken place.

• I2C Master

– A transmission/reception has taken place.

– The initiated Start condition was completed by the SSP module.

– The initiated Stop condition was completed by the SSP module.

– The initiated Restart condition was completed by the SSP module.

– The initiated Acknowledge condition was completed by the SSP module.

– A Start condition occurred while the SSP module was Idle (multi-master
system).

– A Stop condition occurred while the SSP module was Idle (multi-master
system).

0 = No SSP interrupt condition has occurred)

• Bit 2 (CCP1IF): CCP1 Interrupt Flag bit that control capture-compare-pulse

width modulation interrupt flag. It works in three modes. They are given below.
1. Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

2. Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

3. PWM mode:

• Bit 1 (TMR2IF): TMR2 to PR2 Match Interrupt Flag bit

(1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred)

• Bit 0 (TMR1IF): TMR1 Overflow Interrupt Flag bit.

(1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow)

PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral
interrupt, the SSP bus collision

Interrupt, EEPROM write operation interrupt and the comparator interrupt. The
structure of this register is given below.

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

——
——
————— CMIE ————— EEIE BCLIE —- ————— CCP2IE
• Bit 7 Unimplemented: Read as ‘0’
• Bit 6 (CMIE): Comparator Interrupt Enable bit
(1 = Enables the comparator interrupt

0 = Disable the comparator interrupt)

• Bit 5 Unimplemented: Read as ‘0’

Bit 4 (EEIE): EEPROM Write Operation Interrupt Enable bit

(1 = Enable EEPROM write interrupt

0 = Disable EEPROM write interrupt)

• Bit 3 (BCLIE): Bus Collision Interrupt Enable bit.

(1 = Enable bus collision interrupt

0 = Disable bus collision interrupt)

• Bit 2-1 Unimplemented: Read as ‘0’

• Bit 0 (CCP2IE): CCP2 Interrupt Enable bit.
(1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt)

PIR2 Register
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus
collision interrupt, EEPROM write operation interrupt and the comparator
interrupt. The structure of this register is given below.

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

——
——
————— CMIF ————— EEIF BCLIF - ————— CCP2IF
• Bit 7 Unimplemented: Read as ‘0’
• Bit 6 (CMIF): Comparator Interrupt Flag bit
(1 = the comparator input has changed (must be cleared in software)

0 = the comparator input has not changed)

• Bit 5 Unimplemented: Read as ‘0’

• Bit 4 (EEIF): EEPROM Write Operation Interrupt Flag bit.
(1 = the write operation completed (must be cleared in software)

0 = the write operation is not complete or has not been started)

• Bit 3 (BCLIF): Bus Collision Interrupt Flag bit.

(1 = A bus collision has occurred in the SSP when configured for I2C Master
Mode

0 = No bus collision has occurred)

• Bit 2-1 Unimplemented: Read as ‘0’

• Bit 0 (CCP2IF): CCP2 Interrupt Flag bit. This also works in three modes. They
ere
1. Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

2. PWM mode:

This mode is not used.

PCON Register
The Power Control (PCON) register contains flag bits to allow differentiation
between a Power-on Reset

(POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external

MCLR Reset. The structure of this register is given below.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1

—— ——- ——- ——- ——- ——— POR(inverting) BOR(inverting)

• Bit 7-2 Unimplemented: Read as ‘0’
• Bit 1 (POR): Power-on Reset Status bit
(1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on

Reset occurs)

• Bit 0(BOR): Brown-out Reset Status bit

(1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out

Reset occurs)

STATUS register

In most cases, this register is used to switch between the banks (Register Bank Select), but
also has other capabilities.

PIC STATUS register

 With the help of three left bits (IRP, RP1, and RP0) one can control the transition between
the banks:

• IRP - Register Bank Select bit, used for indirect addressing method.
• RP1:RP0: - Register Bank Select bits, used for direct addressing method.

To distinguish between the two methods, at this point, the will use the definition of
fundamental concepts. Later on, the two methods will be studied in detail.
When the IRP Equal to 0, the program will work with banks 0, 1.
When the IRP Equal to 1, the program will work with banks 2, 3.

The following table demonstrates, which of the Banks the program is working with, based on
the selection of the RP0 and RP1 bits:

RP1:RP0 BANK
00 0
01 1
10 2
11 3

An example of using STATUS register and Register Bank Select bit:

1. bsf STATUS, 5 ; Change to Bank 1

2. clrf TRISB ; Set PORTB as output
3. bcf STATUS, 5 ; Change to Bank 0

In the first line, we are in changing/setting the 5th bit, RP0, in the STATUS register to 1, and
thus, base on the table we are switching/selecting Bank 1. After PortB was set as output in the
second line, we switched back to Bank 0 by in changing/setting the 5th bit, RP0, in the
STATUS register to 0, in the third line.

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

An example of using STATUS register and Carry/borrow bit:

1. Movlw 200
2. Addwf 100, 0

In this example, we are assigning value of 200 to the W (working) register. Then, we are
adding the value of 100 and the W register together. The result is stored in W register and
should be 300 (200+100).
However, the maximum value is 256, resulting in carry out. The C (bit 0) of the STATUS
register becomes 1 (C = 1). Register W will contain the reminder: 44.

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for

borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

The bits 3 and 4 are used with WDT - Watchdog Timer.

PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

PORT register

The role of the PORT register is to receive the information from an external source (e.g.
sensor) or to send information to the external elements (e.g. LCD). The 28-pin devices have 3
I/O ports, while the 40/44-pin devices, like PIC16F877, have 5 I/O ports located in the
BANK 0.

1. PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is
TRISA.
Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input. Clearing a
TRISA bit (= 0) will make the corresponding PORTA pin an output.
2. PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is
TRISB.
Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input. Clearing a
TRISB bit (= 0) will make the corresponding PORTB pin an output.
3. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is
TRISC.
Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input. Clearing a
TRISC bit (= 0) will make the corresponding PORTC pin an output.
4. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually
configurable as an input or output.
5. PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are
individually configurable as inputs or outputs. These pins have Schmitt Trigger input
buffers.

For

example:
# define SWITCH PORTA, 0

We define a variable named SWITCH, which received a value of bit number 0 of the
PORTA. Usually we define the ports at the beginning of the program, and then we use only
the given names.

TRIS register

The TRIS register is data direction register which defines if the specific bit or whole port will
be an input or an output. Each PORT has its own TRIS register. Here's a map of the
locations:
BANK0 BANK1
PORTA TRISA
PORTB TRISB
PORTC TRISC
PORTD TRISD
PORTE TRISE

The default mode of each TRIS is input. If you want to set a specific port as exit you must
change the state of the TRIS to 0.

Keep in mind: to change a specific port to an output, one should first move to the BANK1,
make the change, and then return to BANK0. The default state of the banks is BANK0.

The running program is working only with one bank at all time. If not set otherwise, then as
stated, the default bank is BANK0. Part of the registers located inside BANK0, and some are
not. When we need to access a register that is not located inside BANK0, we are required to
switch between the banks.

For example, the access to PORT registers is done inside BANK0. However, to change port
from an input to an output and vice versa, we need to access TRIS register that is located
inside BANK1. From the moment we moved to the BANK1, the program will always work
with BANK1; at this time, to access registers inside BANK0, we will have to return to the
situation in which our program will work with BANK0.
 OSCILLATOR AND RESET CIRCUIT
Most of the modern PIC CPU’s like PIC16F87XA devices are built with many types of advanced
features that are capable of performing additional special tasks and operations. These features
increases the stability of the PIC and increases its functional reliability. It is also helpful for
designers to decrease the entire cost of the designed circuit by the integration and replacement of
external components and also by providing a lot of power saving protections. The general special
features of a modern PIC chip are given below (basis of PIC6F877A).
• Oscillator Selection
• Reset
o Power-on Reset (POR)
o Power-up Timer (PWRT)
o Oscillator Start-up Timer (OST)
o Brown-out Reset (BOR)

Oscillator Selection Function

The PIC16F8xx series basically supports different types of oscillators and also PIC16F87XA devices. It also has a
Watchdog Timer which can be shut-off only through configuration bits. It runs off its own RC oscillator for added
reliability (Configurations as compared to normal microcontrollers/processors). The different oscillator modes can
be easily selected by the user. The user can program two configuration bits (foscillator1 and foscillator0) to selection
of the basic four modes. The basic oscillator modes and the typical values used for these oscillators are given in the
picture below.
✓ LP Low-Power Crystal.
✓ XT Crystal/Resonator
✓ HS High-Speed Crystal/Resonator
✓ RC Resistor/Capacitor
Reset Function
Reset function is one of the most advanced features that is available on all modern microcontrollers. The PIC16F8xx
series have various kinds of resets. The various kinds of reset options that are available on PIC 16F877 series are
given below.

Power-on Reset (POR).

• MCLR Reset during normal operation.

• MCLR Reset during Sleep.
• WDT Reset (during normal operation).
• WDT Wake-up (during Sleep).
• Brown-out Reset (BOR).
A simplified block diagram of the on-chip Reset circuit is shown in the figure below.

MCLR
MCLR is an advanced reset path that helps to filter the unwanted noise. This filter helps to detect unwanted clock
pulses and other noise signals and filter such pulses. It should be noted that a WDT Reset does not drive MCLR pin
low. The behaviour of the ESD protection on the MCLR pin differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can result in both Resets and current consumption outside of device
specification during the Reset event. For this reason, Microchip recommends that the MCLR pin no longer be tied
directly to VDD.
Power-on Reset (POR)
The power –on-reset signals are generated by on-chip when VDD rise is detected. In the normal conditions, the VDD
rise is in the range of 1.2v to1.7v. To take the advantage of POR, connect the MCLR pin to VDD by the resistor
capacitor (RC) network. Before the device is set to start for its normal operation, the different operating parameters
such as frequency, voltage, temperature, and so on must be checked to see if they are normal or proper. If not, the
chip/circuit must be held in reset until the operating conditions are proper or normal. Brown-out-reset function
provides support for these operations.
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Power-up Timer
operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT’s time
delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable or disable the PWRT. The
power-up time delay will vary from chip to chip due to VDD, temperature and process variation
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT
delay is over (if PWRT is enabled). This helps to ensure that the crystal oscillator or resonator has started and
stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up
from Sleep.
Brown-out Reset (BOR)
Brown-out-reset is a special resetting function in modern controllers. Once the brown-out occurs, the device will
remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in Reset for
TPWRT. If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD
rises above VBOR with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out
Reset circuit is enabled, regardless of the state of the PWRT configuration bit.
Time-out Sequence
On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR Reset occurs.
Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, and HS). When the OST ends, the
device comes out of Reset. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will
begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F87XA
device operating in parallel. Table shows the Reset conditions for the Status, PCON and PC registers, while Table
shows the Reset conditions for all the registers.