Module I: Mastering in Digital Design
Module Outcome :
By the end of this course, learners will be able to analyze, design, and troubleshoot basic digital electronic circuits.
They will understand the principles of binary systems, Boolean algebra, logic gates, combinational and sequential circuits, and
be able to apply this knowledge to real-world applications and simulations.
Eligibility :
No prior experience in digital electronics is required. The course begins with fundamental concepts and builds
progressively. all you need is a learning mindset and a genuine interest in electronics and digital systems.
Mode of Training :
Online or Offline
Duration :
20 hours (2hr per session)
Batch Size :
Max 5 people
Course Syllabus
➢ Digital Systems and Binary Numbers ➢ Gate‐Level Minimization ➢ Synchronous Sequential Logic
• Digital Systems • Introduction • Introduction
• Binary Numbers • The Map Method • Sequential Circuits
• Number‐Base Conversions • Four‐Variable K-Map • Storage Elements: Latches
• Octal and Hexadecimal Numbers • Product‐of‐Sums Simplification • Storage Elements: Flip‐Flops
• Complements of Numbers • Don’t‐Care Conditions • Analysis of Clocked Sequential Circuits
• Signed Binary Numbers • NAND and NOR Implementation • Synthesizable HDL Models of Sequential Circuits
• Binary Codes • Other Two‐Level Implementations • State Reduction and Assignment
• Binary Storage and Registers • Exclusive‐OR Function • Design Procedure
• Binary Logic • Hardware Description Language
➢ Registers and Counters
➢ Boolean Algebra and Logic Gates ➢ Combinational Logic • Registers
• Introduction • Introduction • Shift Registers
• Basic Definitions • Combinational Circuits • Ripple Counters
• Axiomatic Definition of Boolean Algebra • Analysis Procedure • Synchronous Counters
• Basic Theorems and Properties of Boolean • Design Procedure • Other Counters
Algebra • Binary Adder–Subtractor
• Boolean Functions • Decimal Adder ➢ Memory and Programmable Logic
• Canonical and Standard Forms • Binary Multiplier • Introduction
• Other Logic Operations • Magnitude Comparator • Random‐Access Memory
• Digital Logic Gates • Decoders • Memory Decoding
• Integrated Circuits • Encoders • Error Detection and Correction
• Multiplexers • Read‐Only Memory
• Programmable Logic Array
• Programmable Array Logic
• Sequential Programmable Devices
Module II: Verilog HDL - Fast-Track to Hardware Development
Module Outcome :
By the end of this course, participants will be able to understand the purpose of Verilog HDL in digital system
design by developing synthesizable, and reusable RTL code. Work through complete design cycles from specification to
simulation, troubleshoot and debug HDL code effectively through testbench implementation.
Eligibility :
No prior experience in learning HDL’s is required. The course begins with fundamental concepts and builds
progressively. all you need is a learning mindset and a genuine interest in electronics and digital systems building through
Verilog HDL
Mode of Training :
Online or Offline
Duration :
18 hours (2hr per session)
Batch Size :
Max 5 people
Course Syllabus
➢ Introduction to Verilog HDL
➢ Assignment ➢ Synthesis Coding Style
• Applications of Verilog HDL
• Types of assignments • Registers in verilog
• Verilog HDL language concepts
• Verilog language basics and constructs • Continuous assignments • Unwanted latches
• Abstraction levels • Timing references • Operator synthesis
• Procedures
• RTL coding style
• Blocking and non blocking
➢ Data Types assignment
• Execution branching
• Type concepts • Task and functions
• Nets and registers
• Non hardware equivalent variables ➢ Finite State Machine
• Arrays • Basic FSM structure
➢ Verilog Operators • Moore Vs Mealy
• Common FSM coding styles
• Logical operators • Registered outputs
• Bitwise and reduction operators ➢ Advance Verilog for Verification
• Concatenation and conditional
• Relational and arithmetic • System tasks
• Shift and equality operators • Internal variable monitoring
• Operators precedence • Compiler directives
• File input and output
Module III :System Verilog HVL: Fast-Track to Verification Mastery
Module Outcome :
By the end of this course, participants will be able to understand the role of System Verilog in functional
verification by developing testbenches using classes, constraints, and randomization. Implementing reusable, scalable
verification components and analyse coverage data to identify verification gaps.
Eligibility :
No prior experience in learning HVL’s is required. The course begins with fundamental concepts and builds
progressively. all you need is a learning mindset and a genuine interest in electronics and digital systems verifying through
System Verilog HVL
Mode of Training :
Online or Offline
Duration :
20 hours (2hr per session)
Batch Size :
Max 5 people
• Null ➢ Assertions
➢ Verification Introduction • Program blocks • External deceleration
• Verification history ▪ Procedural blocks • Event simulation
• Classes and structers • Assertions type
• Usage of verification ▪ Fork join • Typedef class
• Verification plan and environment ▪ Fork control • Assertions system tasks
• Pure • Concurrent assertion layer
• Types of verification (direct and ▪ Subroutines
random verification) • Other oops features • Sequences
• Semaphore ➢ Randomization
• Bus function module (BFM’s) • Mailbox • Properties
• Constrained random verification • Verification directive
➢ Basic Constructs • Fine grain process control • Verilog CRV
➢ Interface ➢ Coverage’s
• Data types • System verilog CRV
• Ports • Code coverage
• Literals • Randomization objects ▪ Statement coverage
• Strings • Interface methods • Random variables
• Clocking blocks ▪ Block coverage
• User define data type • Randomization methods ▪ Conditional coverage
▪ Class • Virtual interface • Checkers ▪ Branch coverage
▪ Union • SVTB Verilog DUT • Constraint blocks ▪ Path coverage
▪ Struct ➢ OOPs ▪ Inline constraint ▪ Toggle coverage
▪ Enumeration • Class ▪ Global constraint ▪ FSM coverage
▪ Typedef • Objects ▪ Constraint mode • Functional coverage
• Arrays • Methods ▪ External constraint ▪ Cover groups
▪ Static array • Inheritance
▪ Fixed arrays ▪ Randomization ▪ Sample
▪ Dynamic arrays • Encapsulation controllability ▪ Cover points
▪ Associative arrays • Polymorphism ▪ Static constraint ▪ Cover point expressions
• Queues • Abstract classes ▪ Generic coverage group
▪ Constraint expression
• Linked list • Parameterized classes ▪ Coverage bin
▪ Variable ordering ▪ Explicit bin creation
• Casting • Nested classes ▪ Constrain solver speed
• Data declaration • Constant ▪ Transition bins
▪ Randcase ▪ Wild card bins
• Reg and logic • Statics
• Operators ▪ Rand sequence ▪ Ignore bins
• Casting ▪ Random stability
• Events ▪ Illegal bin
• Copy ▪ Array randomization ▪ Cross coverage
• Control statements
• Scope resolution operator ▪ Constraint guards ▪ System tasks
▪ Cover property