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Short Course 1

The 2025 Symposium on VLSI Technology features two short courses focused on key VLSI technologies and circuits for AI and computing. The first course covers topics such as CMOS scaling, memory technologies, and integration landscapes, while the second course discusses hardware accelerator design, AI architecture trends, and advancements in power architectures. The event includes presentations from industry leaders and academics, providing insights into current challenges and future directions in VLSI technology.

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24 views5 pages

Short Course 1

The 2025 Symposium on VLSI Technology features two short courses focused on key VLSI technologies and circuits for AI and computing. The first course covers topics such as CMOS scaling, memory technologies, and integration landscapes, while the second course discusses hardware accelerator design, AI architecture trends, and advancements in power architectures. The event includes presentations from industry leaders and academics, providing insights into current challenges and future directions in VLSI technology.

Uploaded by

jei248267
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Program 2025 Symposium on

VLSI Technology
Short Course 1 and Circuits
Key VLSI Technologies in the AI Era
Monday, June 9, 8:25-16:35

Chairpersons: S. Fujii, KIOXIA Corp.


A. Veloso, Imec

8:25
Opening

8:30
CMOS Scaling Exploration: Technology Trends and System-Level
Perspectives
L. Yang, TSMC Main Menu

9:20 Tech. Sessions


2D Materials and Their Application Space - Recent Insights Gained -
J. Appenzeller, Purdue Univ. Circ. Sessions
10:10
Author Index
Break

10:25
Heterogenous System Partitioning, the 2.5D and 3D Integration Landscape
and Roadmap
E. Beyne, imec
Program 2025 Symposium on
VLSI Technology
11:15 and Circuits
Etch and Materials Innovations for Advanced Logic and Memory Applications
T. Lill, Lam Research

12:05
Lunch

12:55
DRAM History and Challenges
Y. Matsumoto, Micron

13:45
Current Landscape and Future Outlook of Emerging Memory Technologies
S. G. Kim, SK hynix Main Menu
14:35
Tech. Sessions
Break

14:50 Circ. Sessions


DTCO/STCO for Multi-Objective Optimization from Device to System
H.-O. Kim, Samsung Author Index

15:40
Heterogeneous Integration Technologies for 3D Integrated CMOS Image
Sensors
Y. Kagawa, Sony
Program 2025 Symposium on
VLSI Technology
16:30 and Circuits
Closing

Short Course 2
Circuits and Systems for AI and Computing
Monday, June 9, 8:25-17:25

Chairpersons: T. Nezuka, MIRISE Technologies Corp.


V. Chen, Carnegie Mellon Univ.

Organizers: K. Nii, TSMC Design Technology Japan, Inc


Y. Li, Western Digital Corp.
Main Menu

8:25 Tech. Sessions


Opening
Circ. Sessions
8:30
Hardware Accelerator Design for AI: Enabling Efficient Generative Models
L. Chang, IBM
Author Index

9:20
Architecture Trends for AI Hardware Platforms
N. James, AMD
Program 2025 Symposium on
VLSI Technology
10:10 and Circuits
Break

10:25
Modular Chiplet Approaches for Scalable and Efficient Machine Learning
Z. Zhang, Univ. of Michigan

11:25
AI for EDA: Challenges and Opportunities
I. Markov, Synopsys

12:05
Lunch
Main Menu
12:55
Connectivity Technologies to Accelerate AI
Tech. Sessions
T. C. Carusone, Univ. of Toronto Alphawave Semi

13:45 Circ. Sessions


3D Optical Interconnect Design
F. Lee, TSMC Author Index

14:35
Break
Program 2025 Symposium on
VLSI Technology
14:50 and Circuits
HBM for AI Computing
J. Lee, SK hynix

15:40
Semiconductor Storage for Further Evolution of Generative AI
J. Deguchi, KIOXIA Corp.

16:30
Advancements in Power Architectures for AI Computing: The Role of
Intermediate Bus Converters and Hybrid Power Systems
K.-H. Chen, National Yang Ming Chiao Tung Univ.

Main Menu

Tech. Sessions

Circ. Sessions

Author Index

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