ELE3124 - Electroni Devices
and Applications
CREDITS:3
ANASWARA VISWANATH
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Programmable Logic
•Simple Programmable Logic Devices (SPLDs)
•Complex Programmable Logic Devices
TOPICS (CPLDs)
COVERED •Macrocell Modes
•Field-Programmable Gate Arrays (FPGAs)
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•The distinction between hardware and software is hazy.
•Today, new digital circuits are programmed into hardware using languages like VHDL.
•The density (number of equivalent gates on a single chip) has increased dramatically over the past few
years.
•The maximum number of gates in an FPGA (a type of PLD known as a field-programmable gate array) is
doubling every 18 months.
•At the same time, the price for a PLD is decreasing.
•PLDs, such as the FPGA, can be used in conjunction with processors and software in an embedded
system,or the FPGA can be the sole component with all the logic functions programmed in.
•An embedded system is one that is dedicated to a single task or a very limited number of tasks unlike the
computer, which is multipurpose and can be programmed to perform just about any task.
•With PLDs, logic is described with software and then implemented with the internal gates of the PLD.
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Simple Programmable Logic Devices
(SPLDs)
•Two major types of simple programmable logic devices (SPLDs) are the PAL and the GAL.
•PAL stands for programmable array logic, and GAL stands for generic array logic.
•Generally, a PAL is one-time programmable (OTP), and a GAL is a type of PAL that is
reprogrammable.
•The basic structure of both PALs and GALs is a programmable AND array and a fixed OR array,
which is a basic sum-of-products architecture.
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The PAL
•A PAL (programmable array logic) consists of a programmable array of AND gates that connects to a fixed
array of OR gates.
•PALs are implemented with fuse process technology and are, therefore, one-time programmable (OTP).
•The PAL structure allows any sum-of-products (SOP) logic expression with a defined number of variables
to be implemented.
•Programmable array is essentially a grid or matrix of conductors that form rows and columns with a
programmable link at each cross point.
•Each programmable link, which is a fuse in the case of a PAL, is called a cell.
• Each row is connected to the input of an AND gate, and each column is connected to an input variable or
its complement.
•By programming the presence or absence of a fuse connection, any combination of input variables or
complements can be applied to an AND gate to form any desired product term.
•The AND gates are connected to an OR gate, creating a sum-of-products (SOP) output.
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The PAL
Implementing a Sum-of-Products Expression
•Fuses are left intact to connect the desired variables or their complements to the appropriate
AND gate inputs.
•The fuses are opened where a variable or its complement is not used in a given product term.
•The final output from the OR gate is the SOP expression,
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SPLD: The GAL
•The GAL is essentially a PAL that can be reprogrammed.
• It has the same type of AND/OR organization that the PAL does.
•The basic difference is that a GAL uses a reprogrammable process technology, such as EEPROM,
instead of fuses, as shown in.
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Simplified Notation for PAL/GAL
•Actual PAL and GAL devices have many AND and OR gates in addition to other elements and are
capable of handling many variables and their complements.
•Most PAL and GAL diagrams that you may see on a data sheet use simplified notation, to keep the
schematic from being too complicated
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Simplified Notation for PAL/GAL
•The input variables to a PAL or GAL are usually buffered to prevent loading by a large number of
AND gate inputs to which they are connected.
•The triangle symbol represents a buffer that produces both the variable and its complement.
•The fixed connections of the input variables and buffers are shown using standard dot notation.
•PALs and GALs have a large number of programmable interconnection lines, and each AND gate
has multiple inputs.
•Typical PAL and GAL logic diagrams represent a multiple input AND gate with an AND gate symbol
having a single input line with a slash and a digit representing the actual number of inputs.
•Programmable links in an array are indicated in a diagram by a red X at the cross point for an
intact fuse or other type of link and the absence of an X for an open fuse.
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Show how a PAL is programmed for the following 3-variable logic function:
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PAL/GAL General Block Diagram
•A block diagram of a PAL or GAL is shown in Figure.
•Remember, the basic difference is that a GAL has a reprogrammable array and the PAL is one-
time programmable.
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Macrocells
•The programmable AND array outputs go to fixed OR gates that are connected to additional
output logic.
•A macrocell generally consists of one OR gate and some associated output logic.
•The macrocells vary in complexity, depending on the particular type of PAL or GAL.
•A macrocell can be configured for combinational logic, registered logic, or a combination of
both.
•Registered logic means that there is a flip-flop in the macrocell to provide for sequential logic
functions.
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•(a) shows a simple macrocell with the OR gate and an inverter with a tristate control that can
make the inverter like an open circuit to completely disconnect the output.
•The output of the tristate inverter can be either LOW, HIGH, or disconnected.
•Part (b) is a macrocell that can be either an input or an output. When it is used as an input, the
tristate inverter is disconnected, and the input goes to the buffer that is connected to the AND
array.
• Part (c) is a macrocell that can be programmed to have either an active-HIGH or an active- LOW
output, or it can be used as an input. One input to the exclusive-OR (XOR) gate can be
programmed to be either HIGH or LOW.
•When the programmable XOR input is HIGH, the OR gate output is inverted, Similarly, when the
programmable XOR input is LOW, the OR gate output is not inverted.
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Complex Programmable Logic Devices (CPLDs)
•The CPLD is basically a single device containing multiple SPLDs and providing more capacity for
larger logic designs.
•A CPLD (complex programmable logic device) consists basically of multiple SPLD arrays with
programmable interconnections.
•Although the way CPLDs are internally organized varies with the manufacturer,. illustrates a
generic CPLD
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Complex Programmable Logic Devices (CPLDs)
•SPLD array in a CPLD as a LAB (logic array block). Other designations are sometimes used, such
as function block, logic block, or generic block.
•The programmable interconnections are generally called the PIA (programmable interconnect
array) although some manufacturers, such as Xilinx, use the term AIM (advanced interconnect
matrix)
•The LABs and the interconnections between LABs are programmed using software.
•A CPLD can be programmed for complex logic functions based on the SOP structure of the
individual LABs (actually SPLDs).
•Inputs can be connected to any of the LABs, and their outputs can be interconnected to any
other LABs via the PIA.
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Classic CPLD Architecture
•The architecture of a CPLD is the way in which the internal elements are organized and arranged. The
architecture of specific CPLDs is similar to the block diagram of a generic CPLD (shown in Figure 10–
8).
•It has the classic PAL/GAL structure that produces SOP functions.
•The density ranges from 2 LABs to 16 LABs, depending on the particular device in the series, package
sizes for
CPLDs vary from 44 pins to 208 pins.
Typically, a series of CPLDs uses the EEPROM-based process technology. In-system programmable (ISP)
versions use the JTAG standard interface.
•Four LABs are shown, but there can be up to sixteen, depending on the particular device in a series.
•Each of the four LABs consists of sixteen macrocells, and multiple LABs are linked together via the PIA,
which is a programmable global (goes to all LABs) bus structure to which the general-purpose inputs,
the I/Os, and the macrocells are connected.
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Classic CPLD Architecture
The Macrocell
•The macrocell contains a small programmable AND array with five AND gates, an OR gate, a
product-term selection matrix for connecting the AND gate outputs to the OR gate, and
associated logic that can be programmed for input, combinational logic output, or registered
output.
•As shown in Figure, Five AND gates feed product terms from the PIA into the product-term
selection matrix.
•The product term from the bottom AND gate can be fedback inverted into the programmable
array as a shared expander for use by other macrocells.
•The parallel expander inputs allow borrowing of unused product terms from other macrocells to
expand an SOP expression.
•The product-term selection matrix is an array of programmable connections that is used to
connect selected outputs from the AND array and from the expander inputs to the OR gate.
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Classic CPLD Architecture
Shared Expanders
•A complemented product term that can be used to increase the number of product terms in an SOP expression is
available from each macrocell in a LAB.
•Figure illustrates how a shared expander term from another macrocell can be used to create additional product terms.
• In this case, each of the five AND gates in a macrocell array is limited to four inputs, shows the expansion to two
product terms.
•Each macrocell can produce up to five product terms generated from its AND array.
•If a macrocell needs more than five product terms for its SOP output, it can use an expander term from another
macrocell.
•Suppose that a design requires an SOP expression that contains six product terms.
•Figure shows how a product term from another macrocell can be used to increase an SOP output.
•Macrocell 2, which is underutilized, generates a shared expander term (E + F) that connects to the fifth AND gate in
macrocell 1 to produce an SOP expression with six product terms
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Classic CPLD Architecture
Parallel Expanders
•Another way to increase the number of product terms for a macrocell is by using parallel
expanders in which additional product terms are ORed with the terms generated by a macrocell
instead of being combined in the AND array, as in the shared expander.
•A given macrocell can borrow unused product terms from neighboring macrocells.
•The basic concept is illustrated, where a simplified circuit that can produce two product terms
borrows three additional product terms.
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Classic CPLD Architecture
•Figure shows how one macrocell can borrow parallel expander terms from another macrocell to
increase the SOP output.
• Macrocell 2 uses three product terms from macrocell 1 to produce an eight-term SOP expression.
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LUT CPLD Architecture
•This architecture differs from the classic CPLD previously discussed.
•This device contains logic array blocks (LABs) each with multiple logic elements (LEs).
•An LE is the basic logic design unit and is analogous to the macrocell.
•The programmable interconnects are arranged in a row and column arrangement running
between the LABs, and input/output elements (IOEs) are oriented around the perimeter.
•A main difference between this type of CPLD and the classic AND/OR array CPLD is the way in
which a logic function is developed.
•Look-up tables (LUTs) are used instead of AND/OR arrays.
•An LUT is basically a type of memory that can be programmed to produce SOP functions.
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•LUT CPLD has a row/column arrangement of interconnects instead of the channel-type
interconnects found in most classic CPLDs
•Most CPLDs use a nonvolatile process technology for the programmable links.
•The LUT CPLD, however, uses a SRAM-based process technology that is volatile—all
programmed logic is lost when power is turned off.
•The memory embedded on the chip stores the program data using nonvolatile memory
technology and reconfigures the CPLD on power up.
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PLA (Programmable Logic Array)
•Architecture of a CPLD is the way in which the internal elements are organized and arranged.
•The architecture of some PLDs is based on a PLA (programmable logic array) structure rather
than on a PAL (programmable array logic) structure,
•The PAL has a programmable AND array followed by a fixed OR array and produces an SOP
expression
•The PLA has a programmable AND array followed by a programmable OR array.
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THANK YOU
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