IS.1/ MULTIPLE PROCESSOR ORGANIZATIONS 639, af / gh oF - KEY POINTS of 7% Atraditional way to increase system performance is to use rultiplé proces- sors that can execute in parallel to support a given workload. The two most common multiple-processor organizations are symmetric multiprocessors (SMPs) and clusters. More recently, nonuniform memory access (NUMA) systems have been introduced commercially. An SMP consists of multiple similar processors within the same computer, imterconnected by a bus or some sort of switching arrangement. The most critical problem to address in an SMP is that of cache coherence. Each Processor has its own cache and so it is possible for a given line of data to be present in more than one cache. If such a line is altered in one cache, then both main memory and the other cache have an invalid version of that line. Cache coherence protocols are designed to cope with this problem. @ When more than one processor are implemented on a single chip, the con- figuration is referred to as chip multiprocessing. A related design scheme “is to replicate some of the components of a single processor so that the processor can execute multiple threads concurrently: this is known as a multithreaded processor A cluster isa group of interconnected, whole computers working together as a unified computing resource that can create the illusion of being one machine. The term whole computer means a system that can run on its own, apart from the cluster ¢ A NUMA system is a shared-memory multiprocessor in which the access time from a given processor to a word in memory varies with the location of the memory word * A special-purpose type of parallel organization is the vector facility, which is tailored to the processing of vectors or arrays of data Traditionally, the computer has been viewed as a sequential machine. Most computer Programming languages require the programmer to specify algorithms as sequences of instructions. Processors execute programs by executing machine instructions in sequence and one at a time, Each instruction is executed in a sequence of operations (fetch instruction, fetch operands, perform operation, store results) This view of the computer has never been entirely true. At the micro-operation level. multiple control signals are generated at the same time. Instruction pipelining. at Ieast to the extent of overlapping fetch and execute operations, has been around for a long time. Both of these are examples of performing functions in parallel. This approach is taken further with superscalar organization, which exploits instruction Jevel parallelism. With a superscalar machine, there are multiple execution units le processor. and these may execute multiple instructions from the same within a sin program in parallelne 640 CHATTER 18 PARALLTI PROCESSING [As computer technology has evolved, and as the cost of computer hardware has dropped, computer designers have sought more and more opportunities for paral Ielsm, usually to enhance performance and, in sone cases @ icresse aval ‘Ate an everview tis chapter looks at some of the most prominent approaches 10 parallel orzanization. isl, we examine ssmmettie multiprocessors (SMP), one of the kl organization. In an SMP organi ‘earliest and stil the most common example of pe “ation, multiple proeeseors shares common momen: Thisarganization raises the issue Of cache eaherence.o which a separate section is devoted. Then we describe clusters ‘which consist of multiple independent computers organized ina cooperative fashion Next. the chapter examines molithreaded processors and chip mulliprocessors e hevond the Cosers have become increasingly common to support worklees chat SMP Another approuet to the use of multiple processes hat examine is that of nanuniformy memory aceess (NUMA) machines The NUMA, approach is selatively new snl not et proven in the marketplace, but is often consi HL as an alternative to the SMP oz cluster approach. Final this chapter Zooks roa approaches to vector computation, These approaches opt hardware orsani mize the ALU for processing vectors of arrays wf flaring: point numbers They ar EGS Tee goo Soe aes Iypes of Parallel Processor Systems Led by Ehsan [FLYN72] Stil che mos common a J processing capabilits Flynn proposed the folloy A toxonomy first inte categorizing sostents with paral is catepories of computer ssteme Jn, single data (SISD) stream: single processur ever nt to operate on dita stosed ita singh! menors single instruct Unipracessoes fll iio this exo tas single machine instr liple data (SIMD) st controls the simuharcuts execution of a number of processing Tockstep basis, Fach processing element has an assieiated data memory. that each instruction is exceuted oa diferent set of dat hy the ale “a! aay prosessiors all inte this catego processors Vecto “Multiple instruetion, single data (MSD) sir mitted to a set of provessore each of which executes a different instruction A sequence ol data is trans sequence This stiueture is nor commercially implemented A set of processors sent “Multiple instruetion, multiple data (MIMD) Tumeousty exectte diferent instruction sequences on diferent data sey SMI chastorsand NUMA systems i int this Catepor With the MIMD organization, the processors are general purpose: evel ble (o process all of the instructions necessary Io) perform the appropriate eit iranstormation: MIMDs can be further subulivided by che means in which the re [8.1 [Fhe processors shave a common memes processors communicate— 642 CHAPTER 18 PARALLEL PROCESSING faye c Faure 162 Allematie Computer Organizations YY 4 shared memory. Final. ith the MIMD, there are multiple evn units ah fy ing a separate instruction staan to its wn PUL The MIMD qray be a sharedememory inultipiowessor (Fisure 18 2ep or 4 dstibuted-merory multicomputer ¢Figure 18.20) “The design issues celating 1g SMPs, clusters and NUMASs are comple. nvols ing isues relating t physical organization, inlereonnection structures, interproses sor cornmunication, operating system design, ad application software teetinques. Our concern here is primarily with organization altbough we touch briefly on oper ating ystom dosign issues, PP n use Until fairy coven, viewaly al single-user personal computers snd most workstations contained @ single goneral-purpese microprocessor. As demands for petformanee Increase and as the cost of mkroprosessors continues to drop. venulors have introduces systems with an SMP organization. The term SMP refers (0 a computer hardware architecture and alsoto the operating system behavior tat eflets that architecture. AD SMP can be defined asa standalone computer system With the folowing characteristics: 1, There are two of more similae processors af comparable capability: 2. These provessors share the same main memory and 10 facilites and are inter connested by a bus oF other internal connection scheme, such that memory focess time is approximately the same for each processorIEEE SS=CSP'S'S; Fr PCL OMICUHPLE PROCESSOR ORGARIZAHONS. 641 Ste nanuction, Single etn, sis “ai Drocemor — procssue ‘tights enue Te apie Somme entlirm imation ‘mers wy, Howe ISLA Taxonuny of Patel Pruwessor Ar chiestures shen each provessor accesses program and data stored in the shared! meres ane processors communicate with cach other vi that memory The most commen lan Sf such ostem s known as asymmetric multiprocessor (SMP) which ne occa inpection 182. tan SME? multiple processors shane sinsle memory oy memory by means of a shared bus of other interconnection mechanien a den, Feature is that the memory access time to any region uf meme n Wely the same for each processor. A more recent development ith, Terunitorm memory access (NUMA) organization. which I described iy Secten ne suggests the memory access time to diferent rey ‘may diller for a NUMA processor A collection of independent unipracessors or SMPS may he interconneete to {ou luster: Communication among the computers is ether via fixed pathece some network facility tons of memory Parallel Orga TeOE Sa lastrates the genera oganizaton of he taxonomy of Figue Fg pra gets the structure of an SISD. There is some sort of control unit (CUj ie senate an Jsruction tears (1S) ta processing unit (PU), The proceing uni oe, wehon a single data stream (DS) from a memory unit (MU).With an SIMD there g pay ingle control unit. now feeding a single instruction steam to multiple Plc Each PU may have sown dedicated memory illustrated in Figure IX2b}ar there may he8.2) SYMMETRIC MULEIROCESSORS 643 3. All processors share nveess to MO devices either through the same ebunne® oF through different channels that provide paths tothe same device. 4 All processors can perform the same functions (hence the term ssmmncric) The system i controlled by an integrated operating system that provides interaction between processors aad their programs at the job, task file, snc data clement loves Points 110.4 should be self-explanatory. Point 5 illustrates one of the contrasts with a loosely coupled multiprocessing system. such as a cluster. Inthe latter. th nan SMP. indivi hal data elements ean constitute the level of interaction, and there can be a high ilepree of cooperation between processes, The operati physi unit of inceraction is usually-a message or complete fi system of an SMP schedules processes or threads seHuss all « the processors. An SMP organization has a number of potential advantages over i uniprocessor organization. including the following + Performance: It the wotk to be done by’ a computer can be organized 90 tha ‘ome portions of the work ean be done in parallel, thei system with multiple processors will yield greater performance than one with a single p the same type (Figure 18.3) | LLL LLLLLLL LL LLL 2 LL LLL EL LL LLL LLLLLELLILE LLL LL 1 | SS —} 77777 ZZA Woke! — MNBL Rossing we IK. Multiprogramming and Multiprocessingout + Availability: In a symmetric multiprocessor, because all processors €an per. form the same functions the failure of 2 single processor does not halt the ‘machine Instead, the system can continue to fumetion af reduced performance, + Incremental growths A user can en adding an additional processor the performance of a sysiem by: + Sealing: Vendors can offer a range of produets with different price and per. formance characteristics hased on the mumber of processoes configured in the system Tis important to note that these are potential rather than guaranteed, benefits The operating system must provide tools and functions 10 exploit the parallelism in an SMP system ‘An attractive feature of a SMP is that the existenee of multiple processors transparent to the user-The operating system Lakes care ufscteduline of threads or processes on individual processors ad of syncliranization among processors Organization Figure 18.4 depicts in general teens the organization of a multiprocessor ss Tere ars two or more processors, Each processor is self-contained, inci control unit, ALL [Link] oF more evels cache Fach processor Interconnection network ity Coupled MultiprocessorCoc °° 0(}°}°}jCT OO EE EEE SSE SYMMIETIC MULTIPROCESSOR 645 Jnas acces (a shares main memory and the HO devices through some form of inter ‘connection mechanism. The processors cin coninmunicate with each ather thraugh memory (messes a satus information left comitnon data areas). He may aba be possible for processors to exchange signals lrecty The memary ioften organized so ‘hae multiple simultaneanss accesses to separate blacks of meinory ae pombe. hn ‘oe configurations. each processor may also have its own private min atenvory and HO channels in addition tthe shared resources univation for personal computers. workstations and sig the simplest mechanisi for The mest common 0 servers is the time-shared bus, The tested bus is jorstiucting a multiprocessor systems (Figure [5-3 The structure and inter taces ae Dusically the same as fora singe-processor system thal uses a bus interconnection The bus camsists of control. addres. and dat Hines Tis fiitate DMA transters tom HO processors the follawing featuresare provid + Addressing: It must he possible to distinguish modules am the bus to deter mine the source and slestination of dat, + Arbitration: Any EO module van temporarily function as master” A mecha ism is provid! co arbitrate competing reguasts for bus cantiol wine soite Df priority scheme “ron fas mn Shared bus vw | Wo adapter subsystem _ 10 [aida vo adapter ame INS Synmeteie Muldiprocesior Organizationno 646 CHAPTER 18 / PARALLEL PROCESSING «Time sharing: When one module is controling the us. other modules are Jocked out and must, necessary. suspend operation until bus access achieved. These unipracessor features are directly usable nan SMP organization. tn this latter case, there are now multiple processors as well as multiple VO processors al sitempting 10 gain access fo one oF more memory modules via the bus The bus organization has several attract ve features: + Simplicity: Ths is the simplest approach to multiprocessor organization The physical interface and the addressing, achiteation, and time-sharing logic of {ach processor remain te same asin as + Flexibility tis generally easy to expand the ssstem by attaching more proces sors tothe bus Reliability: The bus is essentially a passive medium. and the failure of any attached device should nor cause failure of the whole system, x The main drawback to the bus organization is performance, All enor nes pass through the common bus. Thus. the hus eyele tiene Tims the speed Sistem, To improve performance, it iedesirable wo equip each processor ith tremors. This should reduce the aumber of bus accesses dramatically. Typically ‘workstation and PC SMPS have to Fevele of cache, with the LI & (Game chip as the processor) and the L2 cache eiter imternal or ¢ processors now employ 4 LScache a8 wel. “The use ol caches introduces some new design considerations. Because e3eh local cache eantains un image of a portion of memory if a ward is altered in one che. it could conceivably invalidate a word in another cache. To prevent this the Sher processors must be alerted that an update has taken place. This problem is known asthe euche cofterence problem ands typically alressed in hardware rather than by the operating system. We address this issue in Section 1S, Multiprocessor Operating Systen: Design Considerations An SMP operating system manages processor and other computer resources so that ‘the user perceives a single operating system controling system resources. In fact suet 2 configuration should appear 2s a single-processor multiprogramming sistem. It hath the SMP and uniprocessor cases. muliple jas or processes may be active at one time,gn its the responsiblity of the operating system to seedule their exewution and to allocate resources. A user may construct applications that use multiple processes ‘or multiple threads within processes without regard to whether a single processor oF Iultiple processore will be available. Thus a multiprocessor operating systems mast provide all the functionality of « multiprogeamming system plus zuitional features 10 Eecommodate multiple processors. Aniong the key design issues are the folowing + Simultaneous concurrent processes: OS routines nec to be reentrant 19 allow several processors 10 execute the same IS code simultaneously With multiple processors executing the same or different paris ofthe [Link] tables and mas gement structures must be managed properly to avoid deadlock or invalid ‘operations.SYARIETRIG MULTIEROCESSOHS 647 form scheduling, so conflicts must be .woided. The scheduler must assign ready prosesses to available processors + Synctroniations With mulile active processes having potest sees to shared addres spaces of shared HO resouree care must be tkea to provide trestie synchronization. Syoshroicaton is 9 fly tat enforces Mtl Memory management Meiory management ona mulprossor must dal wth | sof the fetes found on sipecesce machines dncuced in Chapce§ tn aalitin, the operating stem needs to expt the valle Reroware [U7 pave such ot muliportd memoris 10 tence the bot performance, | The pigng mechani on dierent preston mst De coondnated to nse Dag OF spent and fo dee on consistency when several procesors share a gradation i the fage of processor failure. The scheduler and other portion ‘operating system must recognize the loss of a processor and restrict meat tables aevordine!s Heamse SMP XC and workstation SMPs use a hus interconnection strategy as Jepicted in fe ISS. Its instructive to look at an alternative approuch, which © used event implementation of the IBS rSer ame tamily [SHEGOS. MAK}, 2930, This family 0f systems spans a range from w uniprocessor sith one main memory card to-a high-end system with 48 processors and S memory care The key components ofthe configuration are shown in Figuce 18.6 + Dual-core processor chip: Each processor chip inl wes two lentil processors (CPs). The CP is a CISC superscalar microprocessor. in wh wired and the rest ae executed hy vertica most of the instructions are hi ‘microcode. Each CP includes a 256-KB 11 instruction exche and a 255-KB LT data eache. + L2 cache: Pach L2 cache contains 52 MB The L2 eaehes are arranged in clus ters of five. with each cluster supposting eight processor chips and providing ccess to the entice main memory space W control clement (SCE): The SCE arbitrates system communication snk! has central rae in maintaining cache coherence. ain store control (MSC): The MSCs interzonneet the L2 caches wid the + Memory cards ach card holds 32 GB of memory. The maximum cont memory consists of 8 memory cards for a total of 256 GB, Memory cards interconnect to the MSC via syncheonous memory intertaces (SMls) Memory bus adapter (MBA): The MBA provides an interface to varios types ‘of HO channels Trai taieom the ehanncks goes directly tothe L2 cacheW547 CLUSTERS 663, separate threads Two program counters are wed, The processor alternates fetching ads AU the instructions ane instructions, up 1 eight ata tie, between the 199 thn Stored in a common instruction cache and share an instruction translation felt ‘she docs a partal instruction deceit. When a conditional branch is encountered Ie branch prediction facility prelets the ditestion of Uke branch at if possible eaewlates the target address For prodieting the target of a subroutine return. the Processor uses a retuen stack, one for each thread Instructions thea move into two separate instruction buffers, Then, om the basis of thread priority. group of insteuctions is selected and decoded in paral lel Next instructions flow throbgh a register renaming lacilty in peagiam ordet sal registers are mapped to physical registers, The Powers hs 120) physical point registers The insteie general-purpose registers and 120 physical float lions are then mowed inte issue queues Fron) the iste quickies, stration are 'ssued using symmetric multithreading. That is. the processor has a superscalar irelieeture and ean issue iastructions fram one or hoth threads in parallel At Inswagi, MPCIS erate head fers ate alle “es wa f An important and relatively recent development computer system design is clus tering. Clustering isan alternative wo symmetric multiprocessing as an approach to Fgh availahils anc! is particularly ateractive for proneing high porformanos ae server applications, We_cim define a cluster as 4 group, ‘somputers working fenether ay 9 untied semnpum reste thal ean create the Tons OT appare Tem TRE Tustin the iterate. each compater in haters pically referred to as. co [GREW7| tists tour benefits that eum be achieved with eustering, These can aso be thought of as objectives oF design requirentents 2 [is possible terete large clusters that fi pass the power o! even the fargest standalone machines. A cluster ean have dozens of ‘muchines cach of which i a multiprocessor + Incremental scalability: cluster is configured in sich a way that iis possible lord new systems tothe cluster in saya increments Thus, user can stact oxi With a modest system and expand it as necds giow, without having to po ticough a niajor upgrade in which an existing smal system is eephaeed with 2 larger system, + High availabilty: Because each node in cluster is standalone computer the Tailure of one node does not mea loss of serve. fn many products fal to ceraice i handle! sutomatiealy in software + Superior prie/pertormance: By using commodity buildin locks its posse tw put together a cluster with equal ar greater computing power than a single large machine, a much lower east | RRR a ae a ARR a GRC NORE ORI AARNE BA A OS664 cu Cluster Cont In the literature, ch Simplest clasifieation tase on whet the compute in a ser sha ase are classified in 4 qumber of different ways, Perhaps the exchange h other com lent systems. Note that in sesso. This is Not Res but does enhance both performance and jo a | Higare 110 Cluster Configurations163 CLUSTERS 665 Methods: ents a Liniations Deserption Bonet “Lislations ‘Aseconiyserver | Eagytoimploment | High ow beeaue the tatesoverin cate of secondary servers roma server fa, ‘tava for oer pomaioptaske ‘Acne Siconirgs | Tnsooontanysarer | Relies a TScaas | Tnerssed corp niy isalenued forpancese | sseanagy serves can _ ington betse fr pees ‘Sejuin Sanam | Separate sens kave Travail, | Traci and ene thei owa dks Date foveread de oping Iseontintoaly oped petatione fram pinay to secon serve. Sewers Comecied” | Sewer are aed | Rated networe aad Ua ees dak wDis thesamedsisea” | sonerowereaddue. | roger RAID tehsererowmits | tachninaon {Usher tocompenste sce irone scree | apsingopertions | foresee di talons Ist deme aton Sere Siow DRS | Mine sere Tac aetearc and] aqua ek manger sinlfapeoey sare | server overhead softreset ssc tok Reduedrak ofdowae | dk mircing oe RAID timeeauseaty ask | tecnotoge ~ use of RAID or some smitar thot the high availatibity achiesed by the presence of multiple compaitersis not com promised by a shared disk that is «single point of faire ‘A clearer picture of the range of clustce options ean he gained by laoking at Functional alternatives. Table 182 provides a useful classification along. funetional lundant disk technology is eommn i clusters $0 lines which we now discuss & common oller method, know 3 passive andi inp thane one em pur Teli of te presving Toad wile the olfer ompatsr fais tse Strats by tothe ori iste ‘ines. the aR a pinay sem pes Sendra "heater. mesage to the standby machine Should these mesages op arriving. the stanly assumes that the pinay server Is ile and pts tel inte operation. Ths approach increases snilbiity bat ces net imran performance Further ifthe only information tate Saetianel between the two syste sa antbeat messages and ie oo sper > rt sae common sk then the stony provide a functional backup But has ho acess othe databassa managed by the pra. The pase stay s generally na relent aa ctr The erm taster reserved for multiple interconseted computers tha areal actively doing proces ing while maining the image of» sing system tothe outside Worl. Te team ive secoiary olen snes serrng to thisconfiguation. Thre classieatons “ielstoins cin hehlemied- separate servers honed nothing a shared enor666 « a HAPTEIC IS UNIALLEL PROCESSING In one approach to castrng. each computer i separate sever wth ig oon di ad tere ae no dn shared beeen tems aurea teragenent pris hgh perormance ay wells hah vata bse oe some typeof management or schol sieve I ceded to gs ioe ion feguest to servers so thatthe Toa blanca and igh seas achive ts desable to have aoe supa hich meats at Pa puter fais wie eacesng so aplication, another computer he cao pick upand smpst the splicton ortho happendats mst oikersptems-The overhead of eds exchange cues Mish anes Re To ec the commanteons overhead. most ostes no const of snes connect common dts ute th lisa bm ths spose aed Shared nothing te comnon disse portioned ita volumes snd cack sone § owed bya ge compte that compute as ecstr mas econ Hivaho posite ohare mpc computes he sate deka eee line ate ee sed sak aprons ha each computer sarees ote fumes cna the dak ae ape egies ne ae soe peo ekg FY facility ro ensure tht da Operating Sestem Design Issues Full exploitation ofa cluster hardware configuration requires some enhancements toa single-spstem operating systen Failure Management How tulures ate managed by a cluster depends on the tering method used (Table 1S2)- In general. 1 approaches can be taken te dealing with failures: highly available clusters and faulltolerant clasters A highly wailable cluster affers a high probability Unat all resources will he in service If 3 failure daes occur. such as a system goes down oa disk vulume is Tost then the {queries in progress are last. Ans lost query. if retried, will he serviced by a different ompuicr in the cluster. However. the luster operating system makes no euarantee shout the state of partially executed transactions This would need tobe handled at the application level ‘A fault-tolerant cluster ens achieved by the use of redundant sh Uncommitted transactions and committing completed transactions The function of switching applications and data resources uver froma failed system to an alternative system in the cluster # referred to as failover. A related ‘unction isthe restoration of applications and data resounces to the original system donve i has been fixed: this s referred 10 as flack, Falck ean be automated ut thisis desirable only ifthe problea) is truly fixed und unlikely to recur. I pot ‘atic failback can eause subsequently failed resources to bounce back and forth between computers sulting in performance and recovery prableme re that all resources are abways available. This is 1d disks and. mechanisms for backing out Load Balineing A cluster requires an effective eapability for balancing the load among available computers. This includes the requirement that the elust /SSCLUNTERS 667 be incrementally sealable. When a new computer is added to the cluster. the joad-halaneing facility shoutd automaticaly include this compute’ in scheduling soplications, Middleware mechanisms need to cecagnire that services con "ppeat on different members ofthe eluster and may migrate from one member to another Paralletizing Computation In some cases, effective use of a cls ines *xecuting software froma single application in pasllel [KAPPON] lists thice neneral «pproaches tothe problen + Paraltelizing compiter: A parallelizing compiler determines at compte tn which parts of am application can be executed in parallel These ate then ph otf to be assigned ta dilferent computers in the cluster. Pettormance denends fon the nature ofthe problem and how wel the compiler is designed * Parallelized application: n this approach. the programmer writes the app éation from the outset to run on a cluster. and uses message p data. a8 required, hetween cluster nodes. This places a high hurde Programmer hut may be the hest approach for exploiting clusters for» * Parametric computing: This approach can be use i the essence of the appl sation is am algorithen or program that must he exseuted » lara mes, each time with a different set of starting conditions or pavanne good example isa simblation moa erent scenarkvs and then develop sta [Link] will run a large ‘ouch to be effective, parametric processing tools are needed to arzunr Cuvier Computer Architecture Figure 18.11 shows a ispicl euster architecture. The individual computers are com: nected by some high-speed LAN or switch hardware, Each computer is capsble. ‘operating independently. In addition, a middleware layer af oltware is installed wach computer to enable cluster operation. The elustet middleware prov ides-a Fed system image to the user. known as a singlesystem image. The middleware 1s also responsible for providing high availability. by means of load halancing an ‘sponding to failures in individual components. [HWANSI] lists the follow ny os desirable cluster middleware servi and funetions + Single entey poi computer. * Single file hierarchy: The user sees a single hierarchy of file directories wader the same rat directory A user logs onto the cluster rather then to an indivigva * Single control point: There is a default workstation used for cluster ment and control * Single vietwal networking: Any nous can access any other point in the cluster, «en though the actual cluster configuration may consist if miliple intercon nected networks. There isa single virtual network operatir899 Cluster middleware POmarkstation | Fomeristatn — [Leomm 30) | eames [Sen [Ne inertace ‘Speed NetworkiSitel Figure IRI Chater Counputer Arehitetune [ALYY WA]Sf NONUNHEOIRAL MEMORY ACCESS 669 ingle memory space: Distributed shared memory enables program to shate variables. + Single job-management system: Under cluster job scheduler, user can sub mitt job without specifying the host computer to execute the job, ingle user interface: A common praphic interface supportsall users, ‘of the workstation from which they enter the chister gardless + Single WO space: Any rile can remotely access any WO peripheral or disk device without knowledge of its physical location, Single process space: A uniform prewesei ‘on any node can ere + Checkpo alate eneapti lemification scheme is used. A press g: This function pevinically saves the process state and interme results toallow rollback recovery after a alone + Process t This function enables fad balancing. Te Last four itemson the preceding list enhance the availability ofthe clus Te romain Revurni tem are concerned with providing a single system image 3 Figure [8 11-a cluster sill also melds software took tr eral ihe efficient execution of prirams ths ae capable af parallel execution, Clusters Compared to SMP Both clusters and symmetric multiprocessors provide processors 10 support high-demand applications. Both solu ‘vailable although SMP schemes has ut The main strength of the SMP approach is that an SMP is easier to mara and configure than a cluster. The SMP is much closer to the original single-proesw inode for which nearly all applications ae written. The principal change require i thing from a uniprocessor 1 an SMP isto the scheduler function. Another Renetit Sf the SMP és that it usually takes up ess pysical space and draws less power tha {comparable cluster. A final important Benefit is That the SMP products ate wel established and stable ‘Over the long run, however, the advantages ofthe luster approach ae ike t result in clusters dominating the high-performance server market, Custers ae far Superior to SMPs in terms of inevemental and absolute scalability. Chiste Superior in terms of availabilty, because all components ofthe sytem can readily be mide highly redundant heen a MRR eee in terms of commercial prosuets, the (#0 common approaches to providing a multiple processor system to support applications sre SMPS and clusters Por some years. nother approach, known as nonuniform memory aecess (NUMA), has Been the subject of research and commercial NUMA products are now available TRefore proceeding, we shoul! define some terms often found in the NUMA