DIGITAL ELECTRONICS

DAY TOPIC NAME Assignments

1 Number Systems and conversions Examples for number systems convertions

2 Number System complements (Binary Arithematics - Addition and Subtraction) Examples to subtract numbers using complements

Boolean algebra, Boolean theorems and laws, Sum of products and product of sums,
3 Examples for conversions into canonicol forms
Minterms and Maxterms
4 Karnaugh map Minimization K-Map Examples
realization of logic gates with Universal gates, Alternative logic
5 Logic gates, Enable & disable concept of gates, Tristate logic gates
gates, De-generate & Non-degenerate
6 Binary Codes – Binary, BCD, Excess 3, Gray
7 Error detection & correction - Parity method Hamming code , CRC
8 Hazards in combinational circuits
9 Half Adder, Full Adder, RCA Subtractors (Half-subtractor, Full-subtractor), CLA
10 Multiplexer, Demultiplexer Design logic gates and other circuits using Mux
11 Encoders, Priority Encoders
12 Decoder (Active high & low outputs), Magnitude Comparator Design logic gates and other circuits using Decoder
TEST - 1
13 Sequential circuits: Latches (SR Latch, S'R' latch), gated latch (SR, D latch) NOR latches
14 Clock - Triggering types, clock duty cycle, clock jitter, glitches & skew
15 Sequential circuits: Flipflops & types (characteristic and excitation tables) FF convertions (other FF to T-FF convertion)
16 Master/Slave FF – Operation, timing diagrams
17 Shift registers - SISO, SIPO, PISO, PIPO Timing diagrams for shift registers
18 Shift registers - Universal Shift Register, Bidirectional Timing diagrams for shift registers
19 Design of Counters- Asynchronous Counters - Up, Down, Up-Down counters Mod counters
20 Synchronous Counters - Up, Down, Up-Down counters Ring Counter, Jhonson counter
Clock generation, Setup time, Hold time, Metastability and frequency calculations,
21
frequency division using counters
22 State Machines Design – Moore models (Overlapping & Non Overlapping) LFSR, Sequence detector
23 Mealy models (Overlapping & Non Overlapping)
24 Memory structure - ROM/ RAM
25 Synchronous FIFO
26 Asynchronous FIFO FIFO depth calculations
GRAND TEST
MOCK
Syllabus revised on - 26-03-2025
 ANALOG
[Link]. TOPIC
1 Basics of N-Type & P-Type semiconductor.
2 PN Junction Operation.
3 Basics of MOSFET (PMOS/NMOS) ,CMOS & FinFet.
4 Realization of Gates using MOSFET.
5 Understanding of basics CMOS operation.
6 CMOS Short Channel Effect , CMOS Leakage Current, DIBL effect.
7 MOSFET Power consumption & Drain Current equation.
8 Transistor Skewing & its effect.
9 CMOS Fabrication Steps.
10 Realization of D-Flip Flop using Transmission Gate.

Verilog
[Link]. TOPIC
1 Introduction - Why verilog, Language Concepts, and abstraction levels, what is DUT and TB
2 How to use questa and see the waveform and netlist Verilog Module and Dataflow
3 DataTypes - whitespaces, comments, Strings, Numbers, Net, Reg, Vectors, Integer, Real, Time, Arrays
4 Operators(Intro and Concatenation, Shift, Relational, Equality, Conditional, Arithmatic)
5 Operators (Logical, Bitwise, Reduction), System Tasks and Compiler directives
6 Gate Level Modeling(ALL gates and one circuit) AND Switch level(NAND)
7 Structural Modeling (FA and MUX and mux from decoder and tristate buffers)
8 Behavioural Modeling - Blocking vs Non-Blocking, if-else and Case and Loops
9 Behavioural Modeling - All Flipflops
10 Behavioural Modeling - Registers
11 Behavioural Modeling - Counters
12 FSM Design
GRAND TEST
MOCK
Syllabus Revised on 07-10-2025
 STATIC TIMING ANALYSIS
[Link]. Topic Sub-Topic
1 Introduction to STA What is Timing Analysis?
Types of Timing Analysis (Static vs Dynamic)
Why Timing Analysis is Important

2 STA Flow & Integration Static Timing Analysis Flow

STA in RTL to GDSII Flow
Inputs and Outputs of STA Tools
PrimeTime STA Tool Components

3 STA Concepts & Terminologies Timing Paths (Input-to-Reg, Reg-to-Output, etc.)

Timing Path Terminology
Setup Time & Hold Time
Timing Checks (Setup & Hold)
Sequential Cells & Timing Arcs
Schematic View of Timing Path

4 Timing Parameters Arrival Time

Required Time
Slack
Critical Path

5 Slack Calculations Setup Slack Calculation (with and without skew)

Hold Slack Calculation (with and without skew)
Positive vs Negative Skew Impact

6 Clock Skew
Definition
Launch & Capture Latency
Skew Impact on Slack

7 Constraints in STA Introduction to SDC (Synopsys Design Constraints)

Application of Constraints
Types of Constraints:
Clock Signal Constraints
Environment Constraints
Functionality Constraints
Design Rules & Optimization Constraints

8 Timing Exceptions False Paths

Multicycle Paths
Commands for Constraints (TCL Examples)

9 Design Rule Violations (DRV) Max Transition Violation

Max Capacitance Violation
Setting DRV Constraints in SDC

10 External Timing Concepts External Setup and Hold Time

Input signals go through pad drivers and logic before reaching synchronous inputs.

11 Clock Behavior Clock Jitter

Variation in clock edge timing due to noise and temperature.
Clock Uncertainty
Margin added to timing analysis due to unpredictable clock behavior.

12 Special Timing Paths Half Cycle Path

Timing paths evaluated within half of a clock cycle.

13 Timing Reports Setup Timing Path Report

Hold Timing Path Report

14 Reset Timing Checks Recovery Time

Removal Time

15 Timing Arc Types Unateness

Positive Unate
Negative Unate
Non-Unate

16 Analysis Techniques Graph-Based Analysis (GBA)

Used in tools like ICC2, Innovus, Fusion Compiler
Faster, more pessimistic, lower accuracy
Path-Based Analysis (PBA)
Used in PrimeTime, Tempus
More accurate, higher memory and runtime usage

17 Slack Equations with Clock Uncertainty Setup Slack Equation (with Uncertainty)
Hold Slack Equation (with Uncertainty)
Conditions for Setup/Hold to be MET or VIOLATED under clock uncertainty
GRAND TEST
MOCK
Syllabus Revised on 07-10-2025
 PHYSICAL DESIGN
[Link]. Topic Sub-Topic
1 Synthesis 1. Understanding Industrial VLSI Design Flow.
2. Inputs of Synthesis
3. Steps of Logical Synthesis, Physical aware Synthesis.
4. Synthesis Flow [Translation, Mapping, Optimization]
5. Synthesis Optimization Technique to achieve best PPA. [Retiming, Multi-Registers, Mux-opt]
6. Advantage & Disadvantage of Logical & Physical Synthesis.
7. Outputs of Synthesis [Gate level netlist, SDC, QOR]
8. Inputs of Physical Design [.V, .sdc, .lib, .lef, .tf, .tlu+]
9. Sanity checks [Checks all the Inputs]
MODULE TEST
2 Floorplan 1. Introduction of Floorplan
2. Inputs of Floorplan
3. Creating Core and Die area
4. Shape and Size of the block [Aspect Ratio]
5. Macro Placement and Guidelines
6. Ports and Pads placement
7. Blockages and types [Hard, Soft, Partial]
8. Keepout margin [Halo]
9. Physical only cells [Boundary, Well tap, Tie, Decap, Filler]
10. Checks after Floorplan
11. Goals of Floorplan
MODULE TEST
3 Powerplan 1. Introduction of Powerplan
[Link] of Power Consumption [Static, Dynamic]
[Link] [Pads, Trunks, Stripes, Rails, Rings]
4. Inputs of Powerplan
5. Methods of Powerplan [Wire band, Bump ]
6. IR drop Types and Fixes [Static and Dynamic]
7. Electro migration Causes and Fixes
8. Contents in UPF [Power domain, Special cells]
9. Isolation cells function and Types
10. Retention cells Function and Types
11. Level shifter cells Function and types
12. Always on cells Function
13. Power Optimization techniques
14. Power Gating and its Types
15. Clock Gating and its Types
16. Adaptive voltage and Frequency scaling
17. Check After Powerplan
18, Goals of Powerplan
MODULE TEST
4 Placement 1. Introduction of Placement
2. Inputs of Placement
3. Check before placement
4. Timing Driven Placement
[Link] driven Placement
6. Power driven placement
7. Area driven placement
[Link] tool perform placement stage [Global, Detail placement, HFNS, Scanchain, Iterations]
9. Congestion and reasons
10. Fixes of congestion
11. Fixes of timing [Setup]
12. Fixes of DRV [Max tran, Max cap]
13. Bounds and Types [Hard, Soft, Exclusive]
14. Path Grouping [R2R, I2R, I2O, R2O]
15. Magnet placement
16. Commands used in placement stage
17. Outputs of placement [Reports]
18. Check after placement
19. Goals of placement
MODULE TEST
5 Clock Tree Synthesis (CTS) 1. Introduction to CTS
2. Inputs of CTS
3. CTS flow [How tool perform]
4. CTS Exception [Stop pin, Through pin, Float pin, Exclude pin, ]
5. Don’t Touch Subtree Pin
6. Various Clock Tree Methodology like Conventional Tree ,H-Tree , MultiPoint Tree, Spine Tree etc.
7. Min/Max/Avg Latency & Global/Local Skew Understanding.
8. Latency & Skew Optimization.
9. CTS optimization techniques [Buffer and Gate sizing]
10 Clock Routing Methodology
11. Outputs of CTS
12. Checks after CTS
13. Goals and Targets of CTS
MODULE TEST
5 Routing 1. Introduction to Routing
2. Prerequisites of Routing
3. Routing Flow [Route_auto to Route_opt]
4. Global Route [Using industrial algorithms]
5. Track Assignment
6. Detail Route
7. Search and repair
8. Routing optimization [VT swapping, Buffer insertion, Cell sizing]
[Link] switches
10. Outputs of Routing [SPEF]
11. Checks after Routing [Opens and shorts]
12. Goals of Routing [Routing DRC Checks & understanding]
MODULE TEST
6 Signoff Data Export & PD pre signoff QC – 1. Introduction to Sign-off
2. Signal integrity and Cross talk [Delay and Noise]
3, Fixes of Crosstalk
4. Antenna voilation [Antenna ratio, Yeild, ]
5. Fixes of Antenna Voilation [Hoping]
6. Introduction to PV
7. Inputs and check of PV
8. LVS
9. ERC
10. DRC
11. DFM
12. Formality [RTL and .V]
13. Low Power Check
14. ECO [Timing, Functional, Metal]
15. Outputs of PV [GDS2]
16. Goals of PV
GRAND TEST
MOCK
Syllabus Revised on 07-10-2025
 Scripting and Projects
[Link]. Topic Sub-Topic
1 Scripting 1. Introduction of TCL
2. TCL Operators
3. TCL Statements
4. TCL Strings
5. TCL List
6. TCL Arrays
7. LINUX Commands

2 Projects 1. Chiptop 14nm

2. ORCA Top 14nm