DIGITAL ELECTRONICS

DAY TOPIC NAME Assignments

1 Number Systems and conversions Examples for number systems convertions
2 Number System complements (Binary Arithematics - Addition and Subtraction) Examples to subtract numbers using complements
Boolean algebra, Boolean theorems and laws, Sum of products and product of
3 Examples for conversions into canonicol forms
sums, Minterms and Maxterms
4 Karnaugh map Minimization K-Map Examples
realization of logic gates with Universal gates, Alternative logic
5 Logic gates, Enable & disable concept of gates, Tristate logic gates
gates, De-generate & Non-degenerate
6 Binary Codes – Binary, BCD, Excess 3, Gray
7 Error detection & correction - Parity method Hamming code , CRC
8 Hazards in combinational circuits
9 Half Adder, Full Adder, RCA Subtractors (Half-subtractor, Full-subtractor), CLA
10 Multiplexer, Demultiplexer Design logic gates and other circuits using Mux
11 Encoders, Priority Encoders
12 Decoder (Active high & low outputs), Magnitude Comparator Design logic gates and other circuits using Decoder
TEST - 1
13 Sequential circuits: Latches (SR Latch, S'R' latch), gated latch (SR, D latch) NOR latches
14 Clock - Triggering types, clock duty cycle, clock jitter, glitches & skew
15 Sequential circuits: Flipflops & types (characteristic and excitation tables) FF convertions (other FF to T-FF convertion)
16 Master/Slave FF – Operation, timing diagrams
17 Shift registers - SISO, SIPO, PISO, PIPO Timing diagrams for shift registers
18 Shift registers - Universal Shift Register, Bidirectional Timing diagrams for shift registers
19 Design of Counters- Asynchronous Counters - Up, Down, Up-Down counters Mod counters
20 Synchronous Counters - Up, Down, Up-Down counters Ring Counter, Jhonson counter
Clock generation, Setup time, Hold time, Metastability and frequency calculations,
21
frequency division using counters
22 State Machines Design – Moore models (Overlapping & Non Overlapping) LFSR, Sequence detector
23 Mealy models (Overlapping & Non Overlapping)
24 Memory structure - ROM/ RAM
25 Synchronous FIFO
26 Asynchronous FIFO FIFO depth calculations
GRAND TEST
MOCK
Updated On - 26-03-2025
 Verilog HDL
Day Topics
Introduction- Why HDL? Differences b/w high level language (C Programming) and HDL, VHDL vs Verilog HDL, VLSI Design Flow cycle.
1
Introducing RTL Design (DUT) and Testbench
Defining RTL Design (DUT) and Verilog Testbench, Structure of DUT and Verilog Testbench, What are Ports and types?, What is
2
Instantiation?, Compilation vs Simulation vs Synthesis
Modelling Styles-Levels of Abstraction, Data Flow Modelling- Implicit Continuous Assignments - Tool Introduction with basic gates or MUX
3
example in Dataflow modelling along with TB
4 Basic Concepts- Lexical Conventions (White Spaces, Comments, Operators, Number Specifications, Strings, Keywords, Identifiers)
5 Basic Concepts- Data Types (Net Data Types, Register Data Types), System Tasks, Defines, Parameters, timescale
6 Basic Concepts- Operators (Concatenation, Replication, Negation, Unary Reduction, Arithmetic, Shift, Relational)

7 Basic Concepts- Operators (Equality (Logical, Case), Bit-wise, Logical-wise, Conditional) - Close on DataFlow modelling

8 Modelling Styles- Gate Level Modelling- Gate Level Primitives (and, or, nand, nor, xor, xnor, not)
10 Modelling Styles- Structural Modelling-Instantiation- Naming, Positioning, Example-Ripple Carry Adder
TEST - 1
11 Modelling Styles- Behavioural Modelling- Procedural Blocks- initial and always, Sensitivity list, Blocking assignments/statements
12 Modelling Styles- Behavioural Modelling- Non-blocking assignments/statements, Inter and Intra Delays
13 Verilog Stratified Queues (Verilog Regions)- Active, Inactive, NBA, Monitor/Postponed Regions
14 Modelling Styles- Behavioural Modelling- If-else (2x1 and 4x1 Mux), case, casex, casez (4x1 Mux, Priority Encoder)

15 Modelling Styles- Behavioural Modelling- Looping Statements- for, repeat, while, forever, begin-end, fork-join, naming of blocks, disable

16 Verilog Functions- Introduction, formal arguments, actual arguments, function call, example- Ripple Carry Adder
17 Verilog Tasks- Introduction, example- Ripple Carry Adder, Task based Testbench
18 Verilog Coding- Arrays, Memories (ROM)
19 Verilog Coding- Memories (RAM)
20 Verilog Coding- Finite State Machines (Moore, Mealy -- Overlap, Non-overlap)
21 Verilog Coding- Synchronous FIFO
22 Testbench approaches - Self checking testbench, Linear TB, Random TB
23 Compiler Directives ('ifdef, 'ifndef, 'endif, 'else)
24 $value$plusargs, Force-Release, ceil, log
25 Clock generation and frequency calculations, frequency division using counters, clock duty cycle
26 File Handling's in verilog, PLI (optional)
27 Generate block - Genvar Keyword, Specify block and UDP (optional)
28 Modelling Styles- Switch Level Modelling- PMOS, NMOS, CMOS- NOT, NAND, NOR, AND, OR Gates (optional)
GRAND TEST
MOCK
Syllabus revised on - 30-08-2025
 System Verilog Syllabus
[Link]. Topic Day Subtopics [Link]. Topic Day Subtopics
• Introduction of System Verilog
• Necessity to migrate from Verilog --> SV --> UVM
• Limitations of Verilog HDL • Inheritance,
1 SV Introduction 1 19
• Role of Verification • Constraint Inheritance
• Types of Verification (Functional/Formal/AMS)
• Architecture of SV Environment
15 OOP Part -1
• New Data types introduced in SV
• Enum & methods
• Typedef
2 Datatypes 2 20 • Casting (static & Dynamic)
• Structure
• Union
• Class
• Fixed Array (Packed and Unpacked)
• Data hiding and Encapsulation
3 • Dynamic Array 21
• Abstract Class
• Associative Array
3 Arrays & Queues 16 OOP Part -2
• Polymorphism
• Queues
4 22 • Pure Virtual Methods
• Queue methods
• Parameterized class & typedef class
• Array ordering methods • Interface
Array Manupulation • Array reduction methods Interface & Program • Modports
4 5 17 23
Methods • Array locator methods block • Clocking Block
•Array index querying methods • Program Block
• Enhanced for loop
• foreach loop
• while loop
5 Loops 6 18 SV Regions 24 • Brief explanation about SV regions
• dowhile loop
• repeat
• forever
• Conditional statements (unique if, priority if, unique
case, priority case)
• jump statements • SV Environment - Monitors (input & output),
Procedural Statements
6 7 • statement labels 19 SV Environment 25 Scoreboard, program block, test, top
and Flow Control
• disable statements • MUX/RAM complete envinronment
• new procedural blocks
(always_comb,always_latch,always_ff,final)
• fork_join • Introduction to Coverage Driven Constraint Random
• fork_join_any Verification (CDCRV)
7 Process Control 8 20 Coverages Part -1 26
• fork_join_none • Types of Coverages (Code & Functional)
• wait fork and disable fork • Covergroups

• Introduction to class • Brief about Functional Coverages

8 Class Introduction 9 • Nested/Aggregated class 21 Coverages Part -2 27 • Coverage Bins (Implicit & Explicit)
• SV Environment - Introducing Transaction class • Different types of bins (Transition, Binsoff, intercept)

• SV methods Introduction - Function & Task • Conditional Coverage

10 • How they differ from Verilog methods 22 Coverages Part -3 28 • coverage options
SV Subroutines • Argument types and Argument Passing Types • Practice Coverages
9
(Function & Task)
• Introduction to Assertion Based Verification (ABV)
11 23 Assertions Part -1 29 • Need and Types of Assertions
• Static and Automatic Methods - Function & Task
• Immediate Assertion
• Why Randomization?
• rand and randc keywords , Randomization methods
• Randomization of scope variables
10 Randomization 12 24 Assertions Part -2 30 • SVA Building Blocks
• How to disable Randomization
• Introduction to Concurrent Assertions
• How we can control Randomization
• SV Environment - Generator class

• Introduction • Assertions Built-in methods

11 Constraints Part -1 13 25 Assertions Part -3 31
• Constraints : Inline, inside, unique and soft •SVA Binding
• Practice Assertions

14 • Constraints: Implication, weighted, static and iterative 32 • FIFO TB Development

SV TestBench
12 Constraints Part -2 26
• Constraints: function inside constraint, bi-directional Development -2 • Practice FIFO TB Development
15 33
and solve before • How to develop testcases in SV
• Work folder and path accessing
Parameters, Macros, • User defined macros
13 Copy methods 16 Shallow copy & Deep Copy 27 34
Packages & DPI • SV Packages
• Introducing DPI
• VPD
• Feature Extraction
17 • Semaphore 28 Introduction to Vplan 35 • Test plan
Inter Process
14 • Mailbox • Coverage Plan
Communication (IPC)
• Assertion Plan
• Events and wait_order GRAND TEST
18
• SV Environment - Driver class
TEST - 1 MOCK
Syllabus revised on 30-08-2025
 UVM
[Link] TOPICS SUBTOPICS COMMENTS
Differences b/w Verilog, SV, UVM TB.
Summary on UVM Methodology.
Limitations to SV Testbench.
1 Introduction to UVM Adavntages of UVM.
Difference b/w HVL (SV) and Methodology (UVM).
Features of UVM.
What is Universal Verification Methodology?

UVM Architecture & Difference between Objects and Components.

Summary on UVM Testbench Architecture with UVM flow.
2 UVM Architecture Exploring UVM Base Libraries.
Difference between Objects and Components.
UVM Architecture Flow Explanation.

UVM class hierarchy.

UVM Class Hierarchy
UVM objects - Sequence item - uvm object methods. Sequence item examples - create, print,copy, clone,
3 UVM Sequence item
UVM utility macros, field macros, Flags. compare.
UVM Object Methods
Print, copy, clone and compare methods usage.

Handshaking Mechanism b/w Sequence, Sequencer, Driver. Summary on Hand Shaking Mechanism.
UVM Handshaking Mechanism
4 UVM Sequence. Sequences with methods and macros.
UVM Sequences
Sequence methods - macros Create 7 sequences using various methods/do macros.

Explanation of UVM Phases.

Build Phases, Run Phases, Cleanup Phases. Summary of UVM Phases.
5 UVM Phases
UVM Infrastructure development (without reference model/ scoreboard / Build UVM infrastructure.
assertions & coverage class).

UVM Reporting and Verbosity Severity, Verbosity.

Development of SRAM Testbench, MUX Testbench.
UVM Driver Simulation Handling Behaviour and Methods: get_type, get_full_name, get_name.
Implementing Reporting Concepts in Testbench - need to
UVM Monitor Difference between reporting macros and Methods and how to control them from
check prints from each and every phase of the every
6 UVM Agent the command line switches.
component.
UVM Environment Develop UVM Driver (without interface) - check transactions in the Run phase of
UVM Basetest driver.
Develop SRAM/MUX DUT and interface.
UVM Testcases Develop UVM components - monitor, agent, environment, basetest, testcases.

Introduction to Database.
Difference between resource_db and config_db.
UVM Config_db Config_db set, get methods and Passing variables/Interface through config_db.
Assignment for uvm_config_db (other data type scenarios).
UVM Driver (ctd..) Passing object class in config_db Set and Get Methods.
7 Updation of Interface and DUT in SRAM and MUX
UVM Monitor (ctd..) Config_db scenarios (passing to only specific components) and passing values
Testbenches
DUT instantiation from command line switches.
Update UVM Driver and Monitor with interface and check transactions.
DUT instantiation and connections.

TEST - 1

Explanation of Factory Overriding. Assignment of Factory Overriding for objects and

9 UVM Factory
Methods - Factory Override by Type, Factory Override by Instance Components

Develop a environment with multiple agents which can drive transactions from
Environment with multiple agents setup Debug any issues
each agent one after the other

Overview and its need Standalone virtual sequence.

Virtual sequence with virtual sequencer. Assignment of Virtual sequence and sequencer. Integrating
Virtual Sequence & Virtual Sequencer
10 What is m_sequencer & p_sequencer. for Multiple IP's.
Sequencer Arbitration Methods
Integrating multiple IP’s into the testbench environment. Assignments for Multiple Arbitration Methods.
Various Arbitration Algorithms methods Using

Different ways of developing testcases in UVM. Developing Testcases by Factory Assignment in Testbench developing Multiple testcases
11 Testcase Development in UVM
Overriding Testcase Running using Config_db. using factory Overriding.

Blocking_put & Blocking_put_imp Blocking_get & Blocking_get_imp

Non-Blocking_put & Non-Blocking_put_imp Non-Blocking_get & Non-
TLM Assignments on Various TLM Ports.
12 Blocking_get_imp Analysis_port & Analysis_imp_port
UVM Subscriber Implementing TLM Ports in SRAM and MUX Testbenches.
TLM_Fifo, Analysis_TLM_fifo,`uvm_decl_macros Example of Subscriber
Connection in Testbench

UVM Scoreboard Develop scoreboard with comparison method.

13 Coverage class Develop coverage class. Debug any issues
Assertion module Write assertions in a module and bind.

14 Configuration object Develop configuration object and try to enable/disable scoreboard. Debug any issues
$value$plusargs - Control from Command Line Control of Verbosity from Command line Control of
15 Command Line Processors
$test$plusargs - Control from Command Line Testcases from Command line

16 VIP & UVC difference Differences b/w VIP and UVC. Revision

17 Mini Project - APB Verification Developing Verification Testbench Implementing Coverages and Assertions. Assignment of Complete testbench Bringup from Scratch.

GRAND TEST
MOCK
Syllabus Revised on 21-08-2025