BECE407P ASIC DESIGN

Module - 6: Physical Design

Dr. PRITAM BHATTACHARJEE

Assistant Professor (Senior Grade 2)
School of Electronics Engineering (SENSE)
Vellore Institute of Technology – Chennai
[Link]@[Link], +91 8132863424
Contents
❖Detailed steps in Physical Design Flow
❖Guidelines for Floorplan
❖Guidelines for Placement
❖Guidelines for Clock Tree Synthesis (CTS)
❖Guidelines for Routing
❖ECO flow
❖Signal Integrity Issues
Detailed steps in Physical Design Flow
▪ Physical design translates netlist to a
manufacturable layout.
▪ Main steps include:
❑ Partitioning & Floorplanning
❑ Placement
❑ Power Planning
❑ Clock Tree Synthesis (CTS)
❑ Routing
❑ Parasitic Extraction
❑ Physical Verification (DRC/LVS)
❑ ECO/Tapeout
Partitioning & Floorplanning
Partitioning: It involves the decomposition of a complex circuit into smaller subsystems (sub-blocks) so
that each subsystem will be of a manageable size and the no. of interconnections between these sub-
blocks will be minimum.
Floor planning: In this step, the rough position of each block on the silicon chip and the shape of each
block will be decided. And also, the pin locations of each block will be decided so that the
interconnections between these blocks can be routed easily in the future as shown in the below picture.
Partitioning & Floorplanning
▪ Purpose: Define chip architecture and spatial layout for macros and standard cells.
▪ Inputs: Netlist, .lef files, utilization target, aspect ratio.
Key Activities:
▪ Define die/core boundary and aspect ratio.
▪ Place I/O pads, macros, hard IPs.
▪ Define keep-out zones, placement blockages.
▪ Create power rings and block-level channels.
▪ Evaluate congestion map and area utilization.
Output: Floorplan DEF file with macro locations, IO pin placements, and power ring
locations.
Power Planning & Placement
Power planning sets up robust power distribution to all logic cells.
Types:
Core cell power management: Core ring (VDD/VSS) and vertical/horizontal straps.
IO cell power management: Power path from IO pads to core rings.
Considerations:
▪ IR drop and electromigration control.
▪ Width/spacing of power strips as per current density.
▪ Separate supplies for analog, digital, and IO domains.
Tools: Innovus, ICC2, or Voltus PowerGrid Analysis.
Placement
Objective: Position standard cells optimally for timing and routability.
Steps:
1. Pre-placement setup (define regions, cell density targets).
2. Initial placement (timing-driven or congestion-driven).
3. Legalization (remove overlaps, satisfy cell site alignment).
4. Optimization (insert buffers, resize gates for timing).
Outputs: Placed DEF file, timing/congestion reports.
Goals:
▪ Minimize total wirelength.
▪ Balance path delays.
▪ Reduce congestion and DRCs.
Clock Tree Synthesis (CTS)

After the completion of floor planning and placement, millions of flip-flops in the
complex circuit will be scattered at multiple places on the silicon chip, so that the
transmission delays of the clock signal for all the flip-flops will not be the same. The
clock will not arrive/reach all the flip-flops at the same time as shown in the figure
below. The difference in the arrival times of the clock signal to these flip-flops is
referred to as clock skew.
Clock Tree Synthesis (CTS)
It is mandatory to make sure that the clock signal reaches multiple flip-flops with no or
minimum skew difference. CTS will ensure that the clock reaches various flip-flops
almost at the same time. In the clock tree synthesis process, any one of the standard
Tree topology structures (shown in the below picture) will be implemented in the
design with an intention of making the length of all the wires in the clock distribution
network equal.
Clock Tree Synthesis (CTS)
Purpose: Distribute clock with controlled skew and latency.
Inputs: Post-placement netlist and parasitic.
CTS Stages:
1. Clock Net Identification
2. Clock Buffer Insertion
3. Clock Balancing and Optimization
4. Post-CTS Hold Fixing
Common Topologies: H-Tree, X-Tree, Fishbone (I-Tree).
Outputs:
▪ Balanced clock network.
▪ Skew, latency, insertion delay reports.
CTS Checks: Ensure no hold/setup violations, no unnecessary transition degradation.
Routing
In this step, interconnecting wires between various blocks will be routed in such a way
that, the length of the interconnecting wires will be minimum for meeting the timing
requirements and for ensuring that, the chip area will not be increased as shown in the
below picture. Proper routing will also ensure that there are no congestion hotspots in
the chip so that, the probability of having faults during the fabrication will be less.
Routing
Objective: Establish physical connections between pins and cells following metal rules.
Stages:
1. Global Routing: Estimate routes at a coarse level; guides detailed router.
2. Track Assignment: Assign routing tracks and layers.
3. Detailed Routing: Generates actual wire paths with DRC compliance.
4. Search & Repair: Fix congestion, shorts, opens, antenna violations.
Post-Routing Checks: Verify DRC, IR drop, timing, and electromigration.
Output: Routed DEF, .spef files for extraction.
Static Timing Analysis
Static Timing Analysis will be done on the final routed netlist which will
represent/mimic the final layout of the chip that is going to be fabricated for validating
the timing performance of the chip and to ensure that, the chip will meet the timing
requirements such as maximum frequency of operation and the design works fine at
the desired frequency without any setup and hold time violations.
Physical Layout
If the timing requirements are not met or if there are any setup and hold time
violations identified, then, optimizing the placement and routing will be done, so that,
timing may be improved, and violations will be eliminated.
Post the timing requirements are satisfied, the physical layout as shown below will be
extracted, and these layouts will be used during the fabrication to prepare the required
mask layers which will be used in the photolithography processes.
Parasitic Extraction (PEX)
Parasitic Extraction (PEX)
Standard Parasitic Extraction Format (SPEF) allows the representation of parasitic
information of a design (R, L, and C) in an ASCII (American Standard Code for
Information Interchange exchange format). A user can read and check the values in a
SPEF file. Users would never create this file manually it is automatically generated
by the tool. It is mainly used to pass parasitic information from one tool to another.
Interconnect parasitic depends on the process. SPEF supports the specification of all
the cases like best-case, typical, and worst-case values. These triplets (best, typical, and
worst) are allowed for R, L, and C values, ports slows, and loads. The units of the
parasitic R, C, and inductance L are specified at the beginning of the SPEF file.
Parasitic Extraction (PEX)

SPEF can be generated by PnR tool or a parasitic extraction tool, and then this SPEF is
used by timing analysis tool for checking the timing, in-circuit simulation or to
perform crosstalk analysis.
Parasitic can be represented at many different levels. SPEF supports three models.
Parasitic Extraction (PEX)
Distributed net model: In this model (D_NET), each segment of a net
route has its own R and C values.

Reduced net model: In this model (R_NET), on the load pins of the
net have single reduced R and C, and on the driver pin of the net a
pie model (C-R-C) is considered.

Lumped capacitance model: In this model, only a single capacitance

is specified for the entire net.
Parasitic Extraction (PEX)
Parasitic extracted from a layout can be defined in three formats:
Detailed Standard Parasitic Format (DSPF)
Reduced Standard Parasitic Format (RSPF)
Standard Parasitic Extraction Format (SPEF)
The SPEF is a compact format of the detailed parasitic. A SPEF file for a design can be
split across multiple files and it can also be hierarchical. SPEF is the format of choice for
representing the parasitic in a design due to its compactness and completeness
 Parasitic Extraction (PEX)
An example of a net with two fanouts (*I *8 and *I *10) is given below. CONTENTS in SPEF FILE:
*D_NET NET_27 0.77181 header_definition: contains basic information such as the SPEF version number, design name,
*CONN
*I *8: Q O *L 0 *D CELL1 and units for R, L and C.
*I *10: I I*L 12.3 [name_map]: specifies the mapping of net names and instance names to indices.
*CAP [power_definition]: declares the power nets and ground nets.
1 *9:0 0.00372945
[external_definition]: defines the ports of the design.
2 *9:1 0.0206066
3 *9:2 0.035503 [define_definition]: identifies instances, whose SPEF is described in additional files
4 *9:3 0.0186259 internal_definition: contains the guts of the file, which are the parasitic of the design.
5 *9:4 0.0117878
6 *9:5 0.0189788
7 *9:6 0.0194256
8 *9:7 0.0122347
9 *9:8 0.00972101
10 *9:9 0.298681
11 *9:10 0.305738
12 *9:11 0.0167775
*RES
1 *9:0 *9:1 0.0327394
2 *9:1 *9:2 0.116926
3 *9:2 *9:3 0.119265
4 *9:4 *9:5 0.0122066
5 *9:5 *9:6 0.0122066
6 *9:6 *9:7 0.0122066
7 *9:8 *9:9 0.142205
8 *9:9 *9:10 3.85904
9 *9:10 *9:11 0.142205
10 *9:12 *9:2 1.33151
11 *9:13 *9:6 1.33151
12 *9:1 *9:9 1.33151
13 *9:5 *9:10 1.33151
14 *9:12 *8: Q 0
15 *9:13 *10: I 0
*END
Parasitic Extraction (PEX)
Purpose: Estimate capacitance (C), resistance (R), and inductance (L) for all nets.
Tools: Synopsys StarRC, Cadence QRC, Siemen’s MentorGraphics Calibre.
Output Formats: SPEF (Standard Parasitic Exchange Format), RSPF.
Significance:
▪ Back-annotate experience into post-layout timing (STA).
▪ Identify coupling capacitance for signal integrity checks.
Physical Verification (DRC/LVS)
Design Rule Check: The physical layout must obey the design rules imposed by the foundry to ensure that, the
layout is manufacturable with a minimum no. of fabrication faults. They act as an interface or communication link
between the circuit designer and the process engineer during the manufacturing phase. So, to ensure that the layout
obeys all the design rules, a DRC will be done.
Layout Vs Schematic: Finally, to ensure that the design’s functionality is not altered during the physical design
implementation Layout, the Layout Vs Schematic (LVS) equivalence checking as shown in the below picture will be
done. This equivalence as shown below will be able to identify if there are missing device terminals or extra device
terminals or unmatched devices and nets in the layout/schematic.
Physical Verification (DRC/LVS)
Design Rule Check (DRC): Verifies geometries comply with foundry rules.
Layout vs Schematics (LVS): Ensures logical connectivity matches schematic/netlist.
Tools: Calibre, Pegasus, ICV.
Outputs: DRC clean, LVS matched reports.

Once this implementation flow which includes floor planning, placement, CTS,
Routing, and Signoff flow with DRC and LVS is completed, the final GDS-II file will be
sent to the foundry where the actual silicon chips are created through a fabrication
process using Silicon wafer.
Guidelines for Floorplan
▪ Define die/core size and aspect ratio (ideally 1:1 for balanced routing).
▪ Place and fix macros and I/O pins carefully, avoiding notches or unnecessary gaps.
▪ Reserve regions for standard cells, power mesh, and blockages.
▪ Consider hierarchical (block-based) vs. flat floorplans, as hierarchical designs enable
team partitioning.
▪ Add special cells (tap, end cap) to prevent latch-up and edge issues.
▪ Output of floorplanning includes placed macros, pin assignments, and blocked
regions.
Guidelines for Placement
▪ Position standard cells optimally for timing, congestion, and area utilization.
▪ Follow stages: pre-placement, initial placement, legalization, buffering.
▪ Legalization ensures physical design rules and manufacturability are met, avoiding
overlaps.
▪ Insert spare cells for future ECOs and special protection cells (antenna diodes, well
taps).
▪ Key aims: minimize wirelength, congestion hotspots, and improve timing closure.
Guidelines for Clock Tree Synthesis (CTS)
▪ Balance clock skew and minimize insertion delay using buffers and inverters.
▪ Common structures: H-tree, Fishbone, X-tree, multi-level.
▪ CTS includes clustering, balancing, clock routing, and post-conditioning (fixing
skew, cleaning up after routing).
▪ Optimize by buffer sizing, gate sizing, and dedicated high-fanout net synthesis.
▪ Final checks: ensure clock latency and skew within specifications, optimize power
and area.
Guidelines for Routing
▪ Routing connects placed cells and pins following Design Rule Checks (DRC).
▪ Four-step process: global route, track assignment, detail routing, search & repair.
▪ Goals: minimal wirelength, via count, area footprint, and zero DRC violations.
▪ Post-routing, check for shorts, opens, antenna violations, and congestion.
▪ Routing tracks aligned to metal layers; proper pitch selection is critical.
ECO (Engineering Change Order)
The process of sending a clean layout file in form of gds/oasis to the
foundry for fabrication after passing all the checks set by the foundry is
termed as tapeout. But before the tapeout there might be many sleepless
nights which Physical Design engineers / Signoff engineers spend to close
the design. There are many signoffs like physical signoff, timing signoff
and IR signoff which we need to get a closer state after which our layout is
ready to send the foundry. And all these final achievements are done in the
ECO (Engineering Change Order) phase.
ECO Implementation
In the ECO cycle, we perform various analysis
one by one for every check which we need to
close but not closed till PnR stage. There are
specialized signoff tools that help us to analyze
the issue and also suggest the changes we need to
do in order to close the issue. The suggested
change is captured in an ECO file. Once we
generate the ECO file for the fixes, we implement
that on the PnR database on which we have
performed the analysis. After the implementation
of ECO file, we save the updated database which
we carry forward for the next ECO generation
and implementation. We repeat this ECO cycle
for every open issue and close one by one all
issues. There are chances that we might need
multiple ECO cycle to close a single issue.
ECO Implementation
Signoff tools are very specialized tools to perform the
analysis for a particular issue thoroughly and also have the
capability to generate the ECO file for the fixes. We have
various types of signoff tools as per the issue like timing
signoff tool, Physical Signoff tool and IR signoff tools.
ECO file contains a series of changes required in
the form of PnR tool command for fixing the issue. Based
on the analysis, sometimes we generate the eco file from the
signoff tool itself or sometimes we create our own eco file.
For example, to fix the setup timing, we need to
upsize the combinational cells or need to convert them to
lower Vth cells. In the case of a few hundred violating paths,
these conversions of cells might be in thousands or more.
So, signoff tool will generate commands for each cell that
need to be changed and write in a file that we call eco file.
Later we source these file in PnR tool followed by refine
placement and ECO route.
ECO Implementation
Once we have the solution of any issue in the
form of ECO file, we need to load the database
which was used to generate the ECO file and
source the eco file. ECO implementation is
generally done in the batch mode of the tool. We
need to delete the fillers before sourcing the eco
file. Once the ECO file is sourced, all the required
changes is done. Now there might be a change in
the size of cells or addition/deletion of some cells
so we need to do refine placement to followed by
the ECO route. These two steps will take care of
any overlap of cells and routing of cells. The
updated database need to be saved for next stage
of ECO or the final database in case of all issues
are fixed.
ECO Flow in Physical Design
ECO begins after logic synthesis and often post-place and route, during or after timing
closure signoff stages. The flow typically includes:
▪ Capturing ECO specifications (functional fixes or timing fixes).
▪ Making changes at the gate-level netlist directly corresponding to RTL changes or
timing adjustments.
▪ Updating placement and routing locally around the changes to minimize
disruption.
▪ Re-running local re-synthesis only on affected portions.
▪ Re-checking timing closure with the new changes.
▪ Verifying ECO correctness using functional verification and formal equivalence
checking with original RTL.
▪ Finalizing updated layout and physical design data before tapeout.
EDA tools help to manage ECO by enabling localized re-synthesis, minimizing changes
only to impacted modules or nets, and supporting incremental timing analysis to avoid
full re-implementation. Physical-aware ECO routing minimizes metal mask changes,
reducing cost and turnaround time.
Scenarios Requiring ECOs
▪ Functional bug fixes discovered after synthesis or layout.

▪ Customer-driven feature or specification changes late in the flow.

▪ Timing closure fixes addressing hold/setup violations.

▪ Power or clock network fixes and optimizations.

▪ Corrections of verification or formal checking failures after implementation.

Typical Design Changes in ECOs
▪ Functional ECOs: Gate-level netlist modifications to fix logical behavior or add
minor feature updates without a full resynthesis of the chip.

▪ Fix-based ECOs: Changes targeting timing violations such as buffer insertion, gate
sizing, upsizing drivers, rerouting nets, or clock tree resynthesis.

▪ Power/Clock ECOs: Adjustments to power gating cells, clock gating, or clock tree
network restructuring to meet power or timing goals.

▪ Metal-mask ECOs: Minimal routing or metal layer changes post-layout to fix

electrical issues or timing without changing standard cell placement significantly.
ECO managing Re-Synthesis, Timing Closure & Layout
Changes
▪ ECO tools perform incremental synthesis and optimization limited to affected
regions, preserving the remaining layout and constraints.
▪ Timing closure is maintained by selectively re-optimizing critical paths impacted by
ECO, often using late-stage optimization techniques like clock tree resynthesis and
local buffer insertion.
▪ Incremental place-and-route or ECO routing steps update metal layers or local
wiring with minimal impact to surrounding structures.
▪ Formal equivalence checking ensures that ECO logic changes correspond exactly to
RTL fixes and no unintended changes propagate.
▪ Design constraints are reused or selectively updated to maintain timing, power, and
design rule adherence without full redesign cycles.
▪ ECO flow attempts to minimize mask changes (pre-mask ECO) or apply metal-only
routing changes (post-mask ECO), preserving manufacturing schedules.
Signal Integrity
Signal could be defined as information in the form of wave/impulse which is used for
communication between two points. In digital form, it is either 1 (high) or 0 ( Low)

By definition, the integrity means “complete or unimpaired” or we can say that

maintaining the actual form of anything over time without any distortion.
So, signal integrity could be defined as replication of the entire signal while transmitting
from one point to another without any distortion in its quality.
or
Signal Integrity is the ability of an electrical signal to carry information
reliably and resist the effects of high-frequency electromagnetic
interference from nearby signals.
Signal Integrity Issues
Signal Integrity may be affected by various reasons, but major reasons are:
1. Crosstalk (Delay and Noise )
2. Ground bounce
3. IR Drop
4. Antenna effect
5. Electromigration
Signal Integrity Issues
What is Crosstalk?
Crosstalk could be defined as a phenomenon in which logic transmitted
in one net creates undesired effects on its neighboring nets. Or in
another world, we can say switching of a signal in one net can interfere in
the neighboring net, which is called crosstalk.
Signal Integrity Issues
When a signal switches, it may affect the voltage waveform of a
neighboring net. The switching net is typically identified as the
“aggressor” and the affected net is the “victim.”

Crosstalk is a very severe effect especially in lower technology

node and high-speed circuits and it could be one of the main reason
of chip failure.
Signal Integrity Issues
Crosstalk mechanism
Crosstalk occurs via two mechanisms:
[Link] Crosstalk
[Link] crosstalk
Inductive crosstalk occurs due to mutual inductance between two nets. A
varying current in a net creates a varying magnetic field around the net. A
varying magnetic field can either radiate energy by launching radio frequency
waves or it can couple to adjacent nets. Such coupling of the magnetic field is
called inductive crosstalk.
Electrostatic crosstalk occurs due to mutual capacitance between two nets. The
electric voltage in a net creates an electric field around it. If the electric field is
changing, It can either radiate the Radio waves or can couple capacitively to the
adjacent net. Such coupling of the electric field is called electrostatic crosstalk.
Electrostatic Crosstalk is significant & problematic than Inductive crosstalk.
Signal Integrity Issues
Fig. (a): Simple model to understand ground bounce
The inverter represents a driver in the lead frame of the package
driving a load CL. The inductances L1, L2, L3 represent the intrinsic
inductances in the ground lead, power lead and output lead of the
package receptively. R1 represents the output impedance of the driver.
Note that ideally, we would want inductances L1, L2, L3 to be absent.
The driver is now given a rising step input, so that its output falls
gradually. Figures (b), (c) and (d) show output waveforms for V , I and
(b) VGB against time (symbols are marked in Figure 4.1.1). The output
voltage V slew rate is dependent on CL, L3, L1 and the pull-down
transistor. For simplicity, the output voltage V is shown to fall at a
(a) constant rate in Figure (b). As the output voltage V falls, the capacitor
starts to discharge and generates a current I as shown in Figure (c).
This discharging current goes to the ground through the inductances
L3 and L1. The voltage waveform across the ground lead inductance
VGB is shown in Figure (d), clearly shows that the internal device
ground is not same as the external system ground at all times or in
other words, the internal device ground bounces.
(c) (d)
Signal Integrity Issues
Ground Bounce
A critical phenomenon that arises predominantly in high-speed
digital circuits, particularly where rapid signal switching occurs.
It is crucial to understand that ground bounce is the result of
changes in the return current path caused by the inductive effects
of circuit layout and design. When signals switch from low to
high states, they can generate a sudden demand for current,
which forces the return current to traverse a longer path. This
can lead to voltage discrepancies at the ground reference point,
causing the signal integrity to suffer significantly.
Signal Integrity Issues
IR Drop
The power supply (VDD and VSS) in a chip is uniformly distributed
through the metal rails and stripes which is called Power Delivery
Network (PDN) or power grid. Each metal layers used in PDN has finite
resistivity. When current flow through the power delivery network, a part
of the applied voltage will be dropped in PDN as per the Ohm’s law. The
amount of voltage drop will be V = I×R, which is called the IR drop.
Signal Integrity Issues
IR Drop
The below figure shows the IR drop in the Power net. Any metal net can be
assumed as a combination of small R and C. If the resistivity of metal wire
is high or the amount of current following through the power net is high,
A significant amount of voltage may be dropped in the power delivery
network which will cause a lesser amount of voltage available to the
standard cells than the actual amount of voltage applied.
Signal Integrity Issues
IR Drop
If V1 voltage is applied at the power port and current I is following in a
particular net which has total resistance R, then the voltage available (V2)
to the other end for the standard cell will be V2 = V1 – I×R
Signal Integrity Issues
IR Drop
Standard cells or macros sometimes do not get the minimum operating
voltage which is required to operate them due to IR drop in power
delivery network even the application of sufficient voltage in the power
port. Voltage drop in the power delivery network before reaching the
standard cells is called IR drop.
Signal Integrity Issues
Antenna Effect
The term Antenna Effect might not give you the right intuition about the
actual effect it may lead you to think about electromagnetic radiation or
transmitter-receiver concepts but here the case is different. So, it has
another popular name which is called “Plasma Induced Gate Oxide Damage”
which provides the right intuition about the effect. As this name itself
indicates that this is an effect caused by the Gate Oxide Damage due to the
Plasma Etching process during the fabrication process.
Signal Integrity Issues
Electromigration

The above figure shows the phenomenon of electromigration effect. A potential

difference is applied across a metal interconnect which setups an electric field from
anode side to cathode side as shown. This electric field causes to move the electron in
the opposite direction of the electric field. This momentum of electron cause flow of
current in the electron. These moving electrons have momentum and when it collides
with the metal ions the metal ions feel two forces in the opposite direction as shown in
the figure. One force and due to electric field and other is due to strike of electrons
wind. If the current density is high the force due to electron wind is greater than the
force due to the electric field.
Signal Integrity Issues
Electromigration

Depending on the current density, the subjected metal ion started drifting in the
opposite direction of the electric field. If the current density is high, the interconnect
may get affected of EM instantly or some times the effect may come after months/years
of operation depending on current density. So, the reliability of ASIC will depend upon
this EM effect.
Signal Integrity Issues
Electromigration
When a high current density passes through a metal interconnect, the
momentum of current-carrying electrons may get transferred to the metal
ions during the collision between them. Due to the momentum transfer,
the metal ions may get drifted in the direction of motion of electrons. Such
drift of metal ions from its original position is called the electromigration
effect. The current density J is defined as the current following per unit
cross-section area. J = I/A, where I is the current and A is the cross-section
of the area of interconnect. As the technology node shrinks, the cross-
sectional area of the metal interconnects also shrinks and the current
density increases in great extent in the lower node. Electromigration has
been a problem since 90 nm technology node or even earlier but it gets
worse in lower technology node 28nm or lower node.