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DDCO Assignment 2

The document is an assignment for the Digital Design and Computer Organization course at GM Institute of Technology, detailing various questions related to addressing modes, performance calculations, instruction execution, memory hierarchy, and processor organization. It includes a grading rubric for assignment submissions based on timeliness, neatness, relevance, correctness, and completeness. The assignment is prepared by Ms. Nanditha G, an assistant professor in the Department of Computer Science and Engineering.

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8 views2 pages

DDCO Assignment 2

The document is an assignment for the Digital Design and Computer Organization course at GM Institute of Technology, detailing various questions related to addressing modes, performance calculations, instruction execution, memory hierarchy, and processor organization. It includes a grading rubric for assignment submissions based on timeliness, neatness, relevance, correctness, and completeness. The assignment is prepared by Ms. Nanditha G, an assistant professor in the Department of Computer Science and Engineering.

Uploaded by

shashankshankra266
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Srishyla Educational Trust (R)

GM INSTITUTE OF TECHNOLOGY, DAVANAGERE


DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
(Accredited by NBA, New Delhi )

Digital Design and Computer Organization (BCS302)


Date: 30.12.2025
Assignment-2

[Link]. Marks Level


Questions CO’s
With relevant example, Explain the following modes of Addressing: 10 CO3 L2
i Indirect
ii Immediate
iii Register
Q1
iv Index
v Base with index and offset
vi Autoincrement
vii Autodecrement
A program with 7000 machine instructions needs an average of 3 basic steps 5 CO3 L3
Q2 to execute one instruction. Find the performance of the computer having a
clock speed of 700KHz.
Show how below expression will be executed in one address, two address 10 CO3 L1
Q3 zero address and three address processor in an accumulator organization
X=(A*B) + (C*D).
Demonstrate the instruction execution and sequencing for C –[A] +[B] with 10 CO3 L2
Q4
block diagram.
Q5 Describe Big Endian and Little-Endian methods of byte addressing with 10 CO3 L2
proper example and write a neat diagram.
Write a note on: 10 CO3 L2
Q6 i) Register Transfer Notation (RTN)
ii) Assembly Language Notation.
Q7 Describe DMA with its registers and controllers. 10 CO4 L2
Q8 Explain the effect of size, cost and speed in memory hierarchy. 10 CO4 L2
Explain hardware interrupt, enabling/disabling of interrupts and sequence of 10 CO4 L2
Q9
events in handling interrupt request from a single device.
Q10 Describe the different memory mapping functions. 10 CO4 L2
Explain the following terms a) interrupt service routine b) interrupt latency c) 10 CO4 L2
Q11
interrupt disabling.
Describe how an ALU performs an Arithmetic and logical operations along with 10 CO5 L2
Q12
input gating diagrams.
Q13 Explain 4-stage pipeline with diagrams 10 CO5 L2
Explain the complete set of operations involved in executing the instruction 10 CO5 L2
Q14 Add(R3), R1 along with control sequence.
Q15 What are Hazards? Explain data hazard, control hazard and structural hazard. 10 CO5 L2
Q16 Draw and explain the single-bus organization of the processor data path. 10 CO5 L2
Explain how the processor fetches a word from memory, stores a word, and 10 CO5 L2
Q17
completes an instruction execution cycle with microoperations.
1. Assignments Write-up

Sl. No Details Marks

1 On date submission 10

2 Write-up and Neatness with sketches 10

3 Relevancy and Correctness 10

4 Completeness of the Assignments 10

Assignments Write-up Marks Distribution (Max 10)


10 -- 8 8 -- 5 5 -- 0
One day after date One week after that
1 On date submission On date submission
of submission date of submission
Write-up with clear Figures with clear flow Figures without scale
2 Figures with scale
sketches and scale (Ratio) (Ratio)
Must be
Must be understandable Relevant but not
3 Correct answers understandable to
and relevant to questions understandable
reader
70% (Some 50% ( Only few
Completeness of the 100% (All questions
4 questions are not questioned are
Assignments answered 10/10)
answered 7/10) answered 5/10)

Prepared by:

Ms. Nanditha G
Asst. Professor
Dept. Of CS&E
GM Institute of Technology,
Davanagere.

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