FIELD-EFFECT TRANSISTOR

The field-effect transistor (FET) is a type of transistor that uses an electric field to control the
flow of current in a semiconductor. It comes in two types: junction-gate FET (JFET) and metal-oxide-
semiconductor FET (MOSFET). FETs have three terminals: source, gate, and drain. FETs control the
flow of current by the application of a voltage to the gate, which in turn alters the conductivity between
the drain and source.
FETs are also known as unipolar transistors since they involve single-carrier-type operation. That is,
FETs use either electrons (n-channel) or holes (p-channel) as charge carriers in their operation, but not
both. Many different types of field effect transistors exist. Field effect transistors generally display
very high input impedance at low frequencies. The most widely used field-effect transistor is
the MOSFET (metal–oxide–semiconductor field-effect transistor).

FET Working
When a voltage is applied to the gate electrode, an electric field is created across the insulating
layer, which in turn creates a depletion region in the channel. The depletion region reduces the number
of free charge carriers in the channel, and thus the conductivity of the channel is reduced. This effect is
known as the field-effect, and it is the basis of the FET operation. In the case of an n-type FET, a
negative voltage applied to the gate electrode creates a depletion region in the channel, which reduces
the flow of electrons from the source to the drain. In contrast, a positive voltage applied to the gate
electrode of a p-type FET creates a depletion region that reduces the flow of holes from the source to
the drain. Thus, by varying the voltage applied to the gate electrode, the conductivity of the channel can
be controlled, and the flow of current through the FET can be modulated.
To explain the working principle of FET, the analogy of a water pipe and vessel can be used. In
this analogy, the source of water can be considered as the source terminal of FET, while the vessel that
collects water can be analogous to the drain terminal of FET. The gate terminal can be compared to the
controlling tap that regulates the flow of water. Similar to how the tap modulates the flow of water, the
voltage applied at the gate terminal controls the flow of current from the source to the drain terminal of
FET. Thus, the FET operates by controlling the flow of current through the channel by modulating the
number of charge carriers in the channel using the voltage applied at the gate terminal.
Essential Information concerning FETs

Field-effect transistors (FETs) can be classified into two types: majority carrier devices, where
the current is carried primarily by the majority carriers, and minority carrier devices, where the current
flow is primarily due to the minority carriers. In FETs, electrons flow from the source to the drain
through active channels in the device, and ohmic contacts connect both the terminal conductors to the
semiconductor material. The source terminal and the gate have a potential between them, and the
conductivity of the channel is a function of this potential.
 FETs have three terminals:
The first terminal is the source (S), through which current enters the device, denoted by IS.
The second terminal is the drain (D), through which current leaves the device, denoted by ID.
The voltage between drain and source is VDS.
The third terminal is the gate (G), which modulates the channel conductivity. By applying a
voltage at the gate, ID can be controlled.
The names of the terminals are based on their functions, which are similar to real-life gates that
control when they open and close. The gate can permit the passage of electrons or block it.
Types of FETs
There are two types of Field Effect Transistors:
 Junction Field Effect Transistor (JFET)
 Metal oxide semiconductor Field Effect Transistor (MOSFET)

What is thermal runaway in transistor?

Thermal runaway is a phenomenon that can occur in transistors when the temperature of the transistor
increases due to excess heat generated by the device. This increase in temperature can cause the
transistor to become even more conductive, which leads to an increase in current flow through the
device. This in turn leads to an even greater increase in temperature, and so on, in a positive feedback
loop. If left unchecked, this process can eventually cause the transistor to fail, either by damaging the
device itself or by causing the surrounding circuit to malfunction

OR

The collector current, being equal increases with increase in temperature. This leads to
increased power dissipation with further increase in temperature. .Being accumulative
process it can lead to thermal runaway resulting in burn out of transistor. Self-
destruction of an un-stabilized transistor is called thermal runaway

Causes of thermal runaway

There are several factors that can contribute to thermal runaway in a transistor,

 High ambient temperatures.

 High levels of current flowing through the device.
 High levels of power dissipation.
Thermal runaway can occur in any type of transistor, including bipolar transistors (BJTs) and field-
effect transistors (FETs). In a bipolar transistor, thermal runaway is typically caused by high levels of
collector current and in a field-effect transistor, it is caused by high levels of drain current. In either
case, the increase in temperature can cause the transistor to become more conductive, leading to an
increase in current flow and an even greater increase in temperature.

FET Biasing Methods – Fixed Bias, Self Bias,

Potential Divider Bias and Current Source Bias:
Unlike BJTs, thermal runaway does not occur with FETs. However, the wide differences in maximum
and minimum transfer characteristics make ID levels unpredictable with simple fixed-gate bias voltage.
To obtain reasonable limits on quiescent drain currents ID and drain-source voltage VDS, source resistor
and potential divider bias techniques must be used. With few exceptions, MOSFET bias circuits are
similar to those used for JFETs. Various FET Biasing Methods are discussed below :
Fixed Bias:

In this FET Biasing Methods, DC bias of a FET device needs setting of gate-source voltage V GS to give
desired drain current ID. For a JFET drain current is limited by the drain-source saturation current I DSS.
Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate
set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery V GG. This battery ensures that the gate is always negative w.r.t.
source and no current flows through resistor RG and gate terminal i.e. IG ≡ 0. The battery provides a
voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the battery V GG.
Resistor RG is included to allow any ac signal applied through capacitor C to develop across R G. While
any ac signal will develop across RG, the dc voltage drop across RG is equal to IGRG i.e. 0 volt.
The gate-source voltage VGS is then

The drain-source current ID is then fixed by the gate-source voltage.

This current then causes a voltage drop across the drain resistor RD and is given as

and output voltage,

Since VGG is fixed value of dc supply and the magnitude of gate-to-source voltage V GS is also fixed,
hence this circuit is named as fixed bias circuit. Since this bias circuit uses two batteries V DD and VGG,
it is also known as two battery bias circuit.

A FET has a high input impedance. To make advantage of it, R G should be as large as possible so that
the input impedance of the circuit remains high. If R G is extremely large a charge accumulated on the
gate may take a long time to leak off. A reasonable upper limit is 1 MΩ. Normally R G should not
exceed this value.

Disadvantage
The fixed bias circuit of FET requires two power supplies.
Self-Bias:

This is the most common FET Biasing Methods. Self-bias for an N-channel JFET is shown in Fig.
13.15. This circuit eliminates the requirement of two dc supplies i.e., only drain supply is used and no
gate supply is connected. In this circuit, a resistor R S, known as bias resistor, is connected in the source
leg.
The dc component of drain current ID flowing through RS makes a voltage drop across resistor RS. The
voltage drop across RS reduces the gate-to-source reverse voltage required for FET operation. The
capacitor CS bypasses the ac component of the drain current I D. The addition of resistor RG in the circuit
does not disturb the dc bias. This is because gate current flowing through it is zero and the gate leakage
current is also almost zero.

Thus, gate is essentially at dc ground. The resistor R G is inserted in the circuit to avoid the short
circuiting of the ac input voltage. Further, if there is a leakage, the resistor R G will provide to it an
escape route. Otherwise, the leakage current would build up static charge (voltage) at the gate which
could change the bias. The resistor RS, the feedback resistor, also helps in preventing any variation in
FET drain current.

Since no gate current flows through the reverse-biased gate, the gate current IG = 0 and, therefore,

With a drain current ID the voltage at the S is

The gate-to-source voltage is then

So voltage drop across resistance RS provides the biasing voltage VGS and no external source is required
for biasing and this is the reason that it is called self-biasing.

The operating point (i.e. zero signal ID and VDS) can easily be determined and equation given below:

Thus dc conditions of JFET amplifier are fully specified.

Self-biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like
trans conductance. Let the given JFET be replaced by another JFET having the double conductance
then drain current will also try to be double but since any increase in voltage drop across R S, therefore,
gate-source voltage, VGS becomes more negative and thus increase in drain current is reduced.

Potential Divider Bias:

A slightly modified form of DC FET Biasing Methods is provided by the circuit shown in Fig. 13.16.
The resistors RG1 and RG2 form a potential divider across drain supply VDD. The voltage V2 across
RG2 provides the necessary bias. The additional gate resistor R G1 from gate to supply voltage facilitates
in larger adjustment of the dc bias point and permits use of larger valued RS.
The gate is reverse biased so that IG = 0 and gate voltage

The circuit is so designed that IDRS is larger than VG (or V2) so that VGS is negative. This provides
correct bias voltage.

The operating point can be determined as

Maximum gain is achieved by making resistance R D as large as possible and for a given level of I D it
needs maximum voltage drop across resistor R D. However, greatest bias stability is achieved by making
RS as large as possible.

If the gate voltage VG is very large as compared to gate-to-source voltage VGS, the drain current is
approximately constant. In practice, the voltage divider bias is less effective with JFET than BJT. This
is because in BJT, VBE = 0.7 V (silicon) with only minor variations from one transistor to another
transistor. But in a JFET, the VGS can vary several volts from one JFET to another.
Current-Source Bias:

In this FET Biasing Methods, When the drain supply voltage V DD is not large, there may not be enough
gate voltage to swamp out the variations in V GS. In such a case current-source bias (Fig. 13.17) may be
used. In this arrangement, the BJT pumps a fixed current through the JFET. The drain current is given
by

Figure 13.18 illustrates how effective current-source bias is. Both Q points have the same value of drain
current. Although VGS is different for each Q point, VGS no longer has any effect on the value of drain
current.

JFET
JFET is Junction gate field-effect transistor. Normal transistor is a current controlled device
which needs current for biasing, whereas JFET is a voltage controlled device. Same like MOSFETs, as
we have seen in our previous tutorial, JFET has three terminals Gate, Drain, and Source.

JFET is an essential component for precision level voltage operated controls in analog electronics. We
can use JFET as voltage controlled resistors or as a switch, or even make an amplifier using the JFET.
It is also an energy efficient version to replace the BJTs. JFET provides low power consumption and
fairly low power dissipations, thus improving the overall efficiency of the circuit. It also provides very
high input impedance which is a major advantage over a BJTs.

There are different types of Transistor, in FETs family, there are two subtypes: JFET and MOSFET.
We already discussed about MOSFET in previous tutorial, here will learn about JFET.

Types of JFET
Same like MOSFET it has two subtypes- N Channel JFET and P Channel JFET.
N channel JFET and P channel JFET schematic model are shown in the image above. The arrow
denotes the types of JFET. The arrow showing to the gate denotes that the JFET is N-channel and on
the other hand the arrow from the gate denotes P-channel JFET. This arrow also indicates the polarity
of P-N junction, which is formed between the channel and the gate. Interestingly, an English mnemonic
is this, that arrow of an N- Channel device indicates “Points in”.

The current flowing through the Drain and Source is dependable on the voltage applied to the Gate
terminal. For the N channel JFET, the Gate voltage is negative and for the P channel JFET the Gate
voltage is positive.

Working of JFET
One best example to understand the working of a JFET is to imagine the garden hose pipe. Suppose a
garden hose is providing a water flow through it. If we squeeze the hose the water flow will be less and
at a certain point if we squeeze it completely there will be zero water flow. JFET works exactly in that
way. If we interchange the hose with a JFET and the water flow with a current and then construct the
current-carrying channel, we could control the current flow.

When there is no voltage across gate and source, the channel becomes a smooth path which is wide
open for electrons to flow. But the reverse thing happens when a voltage is applied between gate and
source in reverse polarity that makes the P-N junction reversed biased and makes the channel narrower
by increasing the depletion layer and could put the JFET in cut-off or pinch off region.

In the below image we can see the saturation mode and pinch off mode and we will be able to
understand the depletion layer became wider and the current flow becomes less.

If we want to switch off a JFET we need to provide a negative gate to source voltage denoted as V GS for
an N-type JFET. For a P-type JFET, we need to provide positive VGS.

JFET only works in the depletion mode, whereas MOSFETs have depletion mode and enhancement
mode.
Biasing of JFET
Different types of techniques are used to bias the JFET in a proper manner. From various techniques,
below three are widely used:

 Fixed DC Biasing Technique

 Self-Biasing Technique
 Potential Divider Biasing

Before going to actual topic let us know what is a pinch-off voltage of a junction field effect transistor
because it takes a vital role to decide the biasing level of a junction field effect transistor.

Pinch Off Voltage

In an n channel JFET, if we apply positive potential at drain terminal keeping the source
terminal grounded, there is current from drain to source through the channel due to drift of free
electrons from source to drain. This current causes a voltage drop along the channel. By considering
this voltage distribution along the channel, we can say that the potential of the channel nearer to the
drain terminal is more than that nearer to the source terminal. At the same time if gate terminal is in
ground potential, then the PN junction between the gate region and channel becomes reverse biased,
and the width of the depletion layer towards drain terminal is more than that of the source terminal.

Now if we continuously increase the drain voltage, the width of the depletion layer gets
increased more rapidly than that towards source terminal. After a certain drain voltage, the depletion
layer towards drain terminal touches each other. This voltage is known as pinch-off voltage. That
means at zero gate voltage, the drain voltage at which depletion layers from both sides touch together is
called pinch-off voltage. It is found that the drain current is linearly proportional to the drain to source
voltage before the pinch-off occurs and the drain current becomes almost constant just after pinch-off
voltage. If we further increase the drain voltage beyond pinch off voltage the drain current remains
constant but after another higher value of drain voltage avalanche breakdown takes place in the reverse
biased junction and suddenly drain current rises very rapidly. This voltage is known as the breakdown
voltage of JFET. So any junction field effect transistor must be operated between pinch-off voltage and
breakdown voltage when it acts as an amplifier. To keep drain to source voltage within the range, a dc
voltage source or battery of suitable voltage is connected in series with load resistance or output
resistance. The voltage appears between drain and source would be
The pinch-off voltage appears between drain and source is Here IDSS is the drain
current flowing through the channel at pinch-off while the gate terminal is in ground potential.

Biasing of Junction Field Effect Transistor or Biasing of JFET

Biasing of JFET by a Battery at Gate Circuit

This is done by inserting a battery in the gate circuit. The negative terminal of the battery is connected
to the gate terminal. As the gate current in JFET is almost zero, there would be no voltage drop across
the input gate resistance. Hence the negative potential of the battery directly reaches to gate terminal.
The corresponding drain current and drain to source voltage would be the output operating point of the
transistor.

NB: – Here in all biasing circuits below, we have included the input AC signal for the better detailing
of the circuit, but during calculation of biasing point or operating point of the JFET, we will ignore the
AC signal as the biasing only deals with DC.

As, in JFET there is no gate current,

We can find the value of drain current ID from the relation given below as IDSS and VGS(off) (= – VP) are
given in transistor data sheet.
The value of VDS can be found by applying KVL at output circuit

The operating point of the JFET is located at the coordinate (VDS, ID) on the characteristic graph.

Fixed DC Biasing Technique

In fixed DC biasing technique of an N channel JFET, the gate of the JFET is connected in such a way
that the VGS of the JFET remains negative all the time. As the input impedance of a JFET is very high
there are no loading effects observed in the input signal. The current flow through the resistor R1
remains zero. When we apply an AC signal across the input capacitor C1, the signal appears across the
gate. Now, if we calculate the voltage drop across the R1, as per the Ohms law it will be V = I x R or
Vdrop = Gate current x R1. As the current flowing to the gate is 0 the Voltage drop across the gate
remains zero. So, by this biasing technique, we can control the JFET drain current by just changing the
fixed voltage thus changing the VGS.

Self Biasing of a JFET

In self-biasing technique, a single resistor is added across the source pin. The voltage drop across the
source resistor R2 creates the VGS to bias the voltage. In this technique, the gate current is zero again.
The source voltage is determined by the same ohms law V = I x R. Therefore source voltage = Drain
current x source resistor. Now, the gate to source voltage can be determined by the differences between
gate voltage and source voltage.

Since the gate voltage is 0 (as the gate current flow is 0, as per V = IR, gate voltage = Gate current x
gate resistor = 0 ) the VGS = 0 – Gate current x Source resistance. Thus there is no external biasing
source is needed. The biasing is created by self, using the voltage drop across source resistor.
 or

Here one resistance RS is inserted between source terminal and ground.

The voltage across RS would be

Here the gate terminal is also grounded through a resistance RG. As there is no gate current, zero ground
potential appears at the gate terminal.

The voltage between the gate and source is VGS.

This equation tells us that here the gate terminal always gets negative potential than the source terminal.

After determining the value of ID, and VDS from above relation, we can put the operating point on the
characteristic graph at the coordinate (VDS, ID).
Voltage Divider Biasing of a JFET
Two series connected resistors form a voltage divider circuit. The voltage at the gate terminal
can be calculated by voltage division rule. In this way, the applied drain voltage is utilized to get the
gate terminal voltage. A resistance is inserted into source terminal in series. The device current flows
through the resistance and causes a voltage drop. If this source voltage drop is greater than voltage
appears at the gate terminal, the gate to source voltage has a negative value which is desired for JFET
operation. Let us consider the following circuit.
 MOSFET Bias Circuits

The MOSFET is type of FET and stands for metal oxide field effect transistor used as amplifier and
switch in different circuit configuration. In digital and analog circuit MOSFET is commonly used
than BJT. There are 2 further main types of MOSFET first is E-MOSFET and second one D-MOSFET.
The main benefit which it provides over the BJT that it need very less amount of current at the input for
controlling of a load. we will have a detailed look at its different basing methods and their related
circuits with the detailed. So let get started with MOSFET Bias Circuits.
MOSFET Bias Circuits

E-MOSFET Bias Congifuration

 Since for E-MOSFET the value of VGS should be larger than the threshold value VGS(th), so zero
biasing cannot be used.

 In below figure you can see 2 configurations of E-MOSFET biasing.

 In these configurations n channels, MOSFET is used.

 Two biasing configurations are shown first is voltage divider and second one drain feedback bias.
 The benefits of the use of this 2 configuration is to make more positive at the gate than by the source
through amount VGS(th).
 The equation for voltage divider bias configuration is given here.
VGS=[R2/(R1 + R2)]VDD
VDS=VDD – IDRD
 In this equation ID will be equal to K(VGS – VGS(th))2we have discussed this expression in last
tutorial about MOSFET.
 In drain feedback bias circuitry shown in figure the gate current is very less and so there will be no
voltage drop about the resistance RG. So VGS = VDS.
D-MOSFET Bias Configuration

 As we know that D-MOSFET can operate with both positive and negative values of VGS voltage.
 The basic method of biasing is to make VGS=0 so ac voltage at gate changes the gate to source
voltage over this zero voltage biasing point.
 Zero bais configuration for MOSFET is shown in below figure.
 As VGS is zero and ID=IDSS as denoted. The drain to source voltage will be.
VDS = VDD – IDSSRD
 The main function of RG is to sustain an ac voltage input by separating it from ground as shown in
figure denoted as b.
 As there is no dc gate current there will be no effect of RG on zero gate to source bias.