Digital System Design 18EE35

3. FLIP FLOPS

A sequential Network is defined as a two valued network in which the outputs at any instant are
dependent not only upon the inputs present at that instant but also upon the past history of inputs. The
past history of inputs must be preserved by the network. For this reason, sequential networks are said to
have memory.

There are two basic types of sequential networks. They are distinguished by the timing of the signals
within the network. A synchronous sequential network is one in which its behavior is determined by
the values of the signals at only discrete instants of time. These networks typically have a master-clock
generator which produces a sequence of clock pulses. The second type of sequential network is
asynchronous sequential network. In this case the behavior of the network is immediately affected by
the input signal changes.

The basic logic element that provides memory in many sequential networks is the flip-flop.
Actually, the flip-flop itself is a simple sequential network. It can be shown that all sequential networks
require the existence of feedback. A flip-flop has two stable conditions. To each of these stable
conditions is associated a state or equivalently, the storage of a binary symbol.

Fig 3.1 Block diagram of Sequential Network

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 Digital System Design 18EE35

3.1 The Basic Bistable Elements

Fig 3.2 Basic bistable element

Central to all flip-flop circuits is the basic bistable element shown in fig 3.2. This circuit has two
outputs, Q and Q̅. It consists of two cross – coupled not gates, i.e the output of the first not-gate serving
as the input to the second and the output of the second not-gate serving as the input to the first. This
structure involves feedback.

The basic bistable element is a circuit having two stable conditions (or state). First assume x=0
in fig 3.2. The output of the upper not-gate is 1 i.e., Q = x̅ = 1. Since the output of the upper not-gate is
the input to the lower not gate, x̅ = y = 1. The output of the lower not-gate, i.e., y̅ is 0. However, since
the output of the lower not-gate is connected to the input of the upper not-gate, Q̅ = y̅ = x = 0. This is
what was assumed to be the value of x. Thus, the circuit is stable with Q̅ = y̅ = x = 0 and Q = x̅ = y = 1.

Similarly if it is assumed that x = 1, then the basic bistable element is stable with Q̅ = x = y̅ = 1 and
Q = x̅ = y = 0. This is the second stable condition associated with the basic bistable element. As a result
of having two stable conditions, the basic bitable element is used to store binary symbols. In the case of
positive logic, when the output line Q is 1, the element is said to be storing a 1; while when the output
line Q is 0, the element is said to be storing a 0. It should be noted that the two outputs are
complementary. That is when Q = 0, Q̅ = 1; and when q = 1, Q̅ = 0.

The binary symbol that is stored in the basic bistable element is referred as content or state of the
element. The state of the basic bistable element is given by the signal value at the Q output terminal.
Hence Q output terminal called the normal output; while the Q̅ output is referred to as the
complementary output. When the device is storing a 1, it is said to be in its 1-state or set. On the other
hand, when the device is storing a 0, it is said to be in its 0-state or reset.

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 Digital System Design 18EE35

Along with these two stable conditions one more equilibrium condition that can exist. This occurs
when the two output signals are about halfway between those associated with logic-0 and logic-1.
Thus, the output is not a valid logic signal. This is known as the metastable state. However, a small
change in any of the internal signal values of the circuit, say, due to circuit noise, quickly causes the
basic bistable element to leave the metastable state and enter one of its two stable states.
Unfortunately, the amount of time a device can stay in its metastable state is unpredictable. For this
reason this state should be avoided.

3.2 Latches

The storage devices called latches from one class of flip-flops. This class is characterized by the fact
that the timing of the output changes is not controlled. That is, the output essentially responds
immediately to changes on the input lines, although a special control signal, called the enable or clock,
might also need to be present.

3.2.1 The SR Latch

The SR ( or set-reset ) latch that consists of two cross-coupled nor-gates. It has two inputs, S and R,
referred to as the set and reset inputs, Q and Q̅. From the logic diagram fig 3.3 a when S = R = 0, the
logic diagram simplifies to the basic bistable element. Thus, the latch is in one of its two stable states
when these inputs are applied. This condition corresponds to the first row of the function table shown
in Fig 3.3 b. In the table Q denotes the present state of the latch. That is, Q is the state of the device at
the time of the input signals is applied. The response of the latch at the Q and Q̅ output terminals as a
consequence of applying the various inputs is denoted by Q+ and Q̅+, respectively. Thus Q+ is called
the next state of the latch. For S = R = 0, the entries Q and Q̅ in the Q+ and Q̅+ columns respectively.
That is, the outputs do not change and the present state is retained.

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 Digital System Design 18EE35

Fig 3.3 (a) Logic diagram

Fig 3.3 (b) Function table Fig 3.3 (c) Logic symbol

Now assume a 1 is applied to the R input of the upper nor-gate and 0 is applied to the S input of the
lower nor-gate. Regardless of the second input to the upper nor-gate, the output Q must become 0 since
R = 1. This signal, which is fed back to the lower nor-gate along with the 0 on the S input, causes the
output of the lower nor-gate, Q̅, to become 1. Thus it is seen that a 1 on the R input and 0 on the S input
results in the latch being reset. This is given by the second row of the table Fig 3.2 b. If the input R is
subsequently returned to 0, then the latch retains its present reset state since Q̅ = 1 signal applied to the
lower input of the upper nor-gate maintain the outputs Q = 0 and Q̅ = 1.

If a 1 is applied to the S input and a 0 is applied to the R input, then the latch becomes set regardless
of its present state. That is, the new out-puts are Q = 1 and Q̅ = 0. This corresponds to the third row of
table 3.2.b. The latch remains in the 1-state when the S input returns to 0.

For the three situations the outputs Q and Q̅ are complementary. Now when S = R = 1. This causes
the outputs of both nor-gates to become 0 and they are not complementary outputs. Difficulty is
encountered when the inputs return to 0. If one input should return to 0 before the other, then the final

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 Digital System Design 18EE35

state of the latch is determined by the order in which the inputs are changed. If both inputs returning to
0 simultaneously, the device may enter its metastable state.

From the function table of the SR latch it should be noted that a 1 serves as the activation signal of
the device. That is, a 1 on either the S or R input terminal causes the device to set or reset, respectively.
Since changes on the S and R inputs can immediately affect the outputs of the latch, the S and R inputs
are regarded as asynchronous inputs.

3.2.2 Application of the SR latch: A switch debouncer

A common problem involving switches in the occurrence of contact bounce. This is illustrated in Fig
3.4 (a). As indicated by the waveforms, with the centre contact of the switch in its lower position, the
voltage at terminal B is +V volts, while the voltage at terminal A is zero. Now if the center contact is
moved from its lower position to its upper position, then it is noted that the voltage at terminal B first
becomes zero, followed by the voltage at terminal A becoming +V volts when the center contact
reaches the upper terminal. However, as result of contact bounce, the center contact of the switch
leaves terminal A, causing the output voltage at that terminal to return to zero, and then upon returning
to terminal A, causing the voltage at terminal A to become +V volts again. This opening and closing
effect, due to the springiness of the contacts, may occur several times before the center contact of the
switch remains in its upper position. It is important to note that during contact bounce, the center
contact does not return all the way to terminal B. similarly, as indicated by the waveform of Fig 3.4 (a),
contact bounce again occurs when the switch is moved from its upper position to its lower position.
The effect of contact bounce is normally undesirable.

Fig 3.4 (a) Effects of contact bounce

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 Digital System Design 18EE35

Fig 3.4 (b) An application of the SR latch A switch debouncer.

A very simple, but important, application of the SR latch is to eliminate the effect of contact bounce.
A switch debouncer circuit and corresponding waveforms are shown in Fig 3.4(b). Assume positive
logic so that +V volts corresponds to logic-1 and ground to logic-0. By use of the two pull-down
registers, logic-0 values are ensured at the S and R terminals of the SR latch whenever the center
contact of the switch is not connected to either terminals A or B, i.e., whenever the switch is open.
Thus, when the center contact moves from its lower position to its upper position, the SR latch remains
in its reset state until the center contact reaches terminal A, at which time the Q output of the SR latch
becomes 1. If the switch now opens, as a result of contact bounce, then the 0 input to the S and R
terminals of the latch causes the Q and Q̅ outputs to remain unchanged. Hence, by use of the SR latch,
the effect of contact bounce is eliminated. In a similar manner, the effect of contact bounce is also
eliminated when the switch moves from its upper position to its lower position.

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3.2.3 S̅ R̅ Latch

Another type of latch, the S̅ R̅ latch, is constructed by cross- coupling two NAND-gates. Such a latch is
shown in Fig 3.5 (a) and its function table is given in Fig 3.5 (b). From the second logic diagram of Fig
3.5 (a), it is immediately seen that when S̅ = R̅ = 1 the logic diagram reverts to the basic bistable
element i.e., the cross coupling of two not-gates. Thus the device has two stable states. This is indicated
by the last row of the function table.

Fig 3.5 (a) S̅ R̅ latch logic diagram

Fig 3.5 (b) Function Table Fig 3.5 (c) Logic Symbols

If just one of the inputs to the S̅ R̅ latch is made 0 while the other is 1, then the output of the NAND-
gate having the 0 input becomes 1. This, in turn, is applied as an input to the second NAND-gate that
also has a 1 as its other input. Consequently, the output of the second NAND-gate becomes 0. Thus, if
R̅ = 0 and S̅ = 1, then the latch resets; while if R̅ = 1 and S̅ = 0, then the latch sets. These conditions are
described by the two middle rows of the function table. In either case, when the 0 input returns to 1, the
S̅ R̅ latch remains its present state.

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 Digital System Design 18EE35

Similar to the SR latch, the fourth possible input combination causes difficulty. In this case, if 0 is
applied to both the S̅ and R̅ inputs, then both outputs become 1. Now if the inputs subsequently return
to 1 simultaneously, then unpredictable behavior will exist. Thus, the application of S̅ = R̅ = 0 is
normally not recommended.

From the function table Fig 3.5 (b) 0 serves to initiate action in the S̅ R̅ latch. That is, a 0 on the S̅
terminal causes the latch to set; while a 0 on the R̅ terminal causes it to reset.

3.2.4 The gated SR latch

The inputs for both SR latch and the S̅ R̅ latch are asynchronous or direct. That is, a change in value of
these inputs causes an immediate change of the outputs. To allow the input changes to be effective only
during a prescribed period of time, a Gated SR latch is used. It is also called a SR latch with enable.

Fig 3.6 (a) Gated SR latch logic diagram Fig 3.6 (b) Function table

Fig 3.6 ( c ) Logic Symbol

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 Digital System Design 18EE35

A gated SR latch is shown in Fig 3.6 (a). It consists of the S̅ R̅ latch along with two additional
NAND-gates and a control input, C, referred to as the enable, gate or clock input. The enable input, C
determines when the S and R inputs become effective. As long as the enable input is 0, the outputs of
the NAND gates A and B are 1, which keeps the gated SR latch in its current stable state. In this case
any changes on the S and R lines are blocked and the output is said to be latched in its present state.
The latch is said to be disabled. This is indicated by the last row of function table.

The remaining four rows of the function table correspond to those situations when the enable signal
C is 1. In these cases the gated latch is said to be enabled. Here the latch behaves as a regular SR latch.
A 1 on just one S or R input, becomes 0 to the cross coupled NAND gates and causes the latch to set or
reset respectively. Applying 1 simultaneously to both the S and R input terminals when C = 1 is not
recommended in order to avoid the unpredictable state. Since the effects of the S and R inputs are
dependent upon the presence of an enable signal, these inputs are classified as synchronous inputs.

3.2.5 The Gated D Latch

The SR, S̅ R̅ and Gated SR latch has an input combination that is not recommended. The Gated D-
latch does not have this problem. The logic diagram and function table of Gated D latch is shown in Fig
3.7 ( a) and 3.7 (b).

Fig 3. 7 (a) Gated D latch Logic diagram

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 Digital System Design 18EE35

Fig 3.7 (b) Function table Fig 3.7 (c) Logic symbol

The gated D latch is a gated SR latch in which a not gate is connected between the S and R
terminals. Thus the latch consists of a single input D that determines its next state and a control, i.e.,
enable input C that determines when the D input is effective. As indicated in the function table, when
the latch is enabled, i.e., C = 1, the output of the latch follows the values applied to the D input
terminal. In particular D = 0, then the latch switches to or remains in the 0-state; while if D = 1, then
the latch switches to or remains in the 1-state. However, when the latch is disabled, i.e., C = 0, the latch
remains in the state prior to the enable signal going to 0.

3.3 Master Slave Flip-flops ( Pulse-Triggered flip-flops )

In addition to latches, there are two other general categories of flip-flops. These are the master slave
flip-flops and edge triggered flip-flops. It was observed that latches have the common property of
immediate output responds while enabled caused by changes on the information input lines, i.e., the S,
R and D lines. This property is referred to as transparency. It is necessary that the output changes occur
only coincident with changes on a control input line. The property of having the timing of a flip-flop
response being related to a control input signal is achieved with master-slave and edge triggered flip-
flops.

A master-slave flip-flop consists of two cascaded sections, each capable of storing a binary symbol.
The first section is referred to as the master and the second section as the slave. Information id entered
into the master on one edge or level of a control signal and is transformed to the slave on the next edge
or level of the control signal. In its simplest form, each section is a latch.

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3.3.1 The Master-Slave SR Flip-flop

Mater-Slave Flip-flops are constructed from two gated SR latches and an inverter. The information
input lines S and R are used to set and reset the flip-flop. A clock signal, C, is applied to the control
input line. The timing behavior of the master-slave flip-flop is referred to the control signal. This
behavior is illustrated in Fig 3.8 (b). The transition of the control signal from its low to high value, i.e.,
0 to 1 in positive logic, is called the rising or leading or positive edge of the control signal; while the
transition of the control signal from its high to low value i.e., 1 to 0 in positive logic is called the falling
or trailing or negative edge of the control signal.

As long as C = 0 the master, being a gated SR latch, is disabled and any changes on the S and R
input lines are ignored. At the same time, the slave is enabled due to the presence of the inverter.
Hence, the slave is in the same state as that of the master since QM and Q̅M outputs of the master are
connected to the S and R inputs respectively, of the slave. As the control signal starts to rise, the slave
is disabled, by design, at time t1; while the master remains disabled. Thus, the slave becomes
disconnected from the master but retains the state of the master. The control signal continues to rise,
and it is at time t2 that the master is enabled. While C = 1, the master, being a gated SR latch, responds
to the inputs on the S and R lines. Since the slave is disabled due to the presence of the inverter, any
changes to the state of the master are not reflected to the slave. The control signal is subsequently
returned to its low level at time t3. At this time, the master is disabled, causing it to latch onto its new
state. It is not until time t4 that the slave is enabled. This results in the slave taking on the state of the
master as the connection is made. It is important to note that for every short periods during the rising
and falling edges of the control signal both the master and slave latches are disabled. This is critical to
the operation of a master-slave flip-flop.

It should be observed that although the master can change its state ( and, correspondingly, its
output) at any time while the control signal is 1, it is only as the control signal goes from 1 to 0 that the
slave changes its state. Thus, the output change of the master-slave flip-flop is synchronized to the
falling edge of the control signal. This controlling of the output change to be coincident with the
change on the control input line is precisely the property being sought by flip-flops not in the latch
category. The master-slave principles is one way in which this property is achieved.

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 Digital System Design 18EE35

Fig 3.8 (a) Master-Slave SR Flip-flop logic diagram

Fig 3.8 (b) Flip-flop actions during the control signal

Fig 3.8 ( c) Function table Fig 3.8 ( d) Logic symbol

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 Digital System Design 18EE35

The behavior of the master-slave SR flip-flop is shown in fig 3.8 (c ) function table. The pulse
symbol in the C column, , indicates that the master is enabled while the control signal is high and
that the state of the master is transferred to the slave, and correspondingly, to the output of the flip-flop,
at the end of the pulse period. The fourth row of the function table corresponds to the situation of both
S and R being 1 when the control signal goes from high to low. Since the master is a latch, it enters the
unpredictable state, including the possibility of the metastable state. This state then transferred to the
slave. Hence the output of master-slave SR flip-flop itself becomes unpredictable. Such condition
should be avoided. Since the behavior of the master-slave Flip-flop depend upon the rising edges of the
control signal as well as the period of time in which the control signal is high, hence they are referred
as ‘pulse-triggered flip-flops’.

Fig 3.8 ( e) Timing diagram for a master-slave SR flip-flop

Fig 3.8(e) shows the timing diagram for the input and the output terminals of a master-slave SR flip-
flop along with some propagation delays.

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 Digital System Design 18EE35

3.3.2 The Master-Slave JK Flip-Flop

In the master slave JK flip flop, the unpredictable condition when S = R = 1 will be avoided and
toggling of the output will takes place. That is if the present state is 0, then the next state is 1.; while if
the present state is 1, then the next state is 0. In addition to master-slave SR flip flop two AND gates
are included at the input side to sense and steer the state of the slave.

Assume the master-slave JK flip-flop is in its 1-state, the control signal is 0 and that J = K = 1, thus,
the master and slave latches are both in the 1-state with Q = QS = 1 and Q̅ = Q̅S = 0. As the result of the
feedback lines, the output of the J-input AND gate is logic 0 and the output of the K-input AND gate is
logic-1. The net effect is that S = 0 and R = 1 at the inputs to the master latch, although these inputs
cannot affect the state of the master at this time since C = 0. If the clock is now changed from 0 to 1,
then the master resets; while the slave being disabled remains in its 1-state. However, upon the clock
returning to 0, the content of the master is transferred to the slave, causing the new state of the master-
slave JK flip-flop to become the 0-state. Thus, the output of the master-slave JK flip-flop toggled when
J = K = 1.

Now assume the master-slave JK flip-flop is in its 0-state, again J = K = 1, and the control signal (
clock ) is low. Thus, Q = QS = 0 and Q̅ = Q̅S = 1. In this case the output of the J-input And gate is logic-
1; while the output of the K-input AND gate is logic-0. At the master input terminals, S = 1 and R = 0.
Hence, when the clock is changed from 0 to 1, the master enters its 1-state, which is subsequently
transferred to the slave when the clock changes from 1 to 0. Again the state of the master-slave JK flip-
flop toggled. This toggling behavior is indicated by last row of the function table.

Consider the third row of the function table that indicates that a 1 on just the J input line has the
effect of setting the flip-flop. Assume the master-slave JK flip-flop is in its 1-state when the clock is
low. Thus, Q = QS = 1 and Q̅ = Q̅S = 0. Since the slave is enabled and in its 1-state, the master must also
be in its 1-state, i.e., QM = 1 and Q̅M = 0. If J = 1 and K = 0, then the outputs of both AND gates are
logic-0 since they each have a 0 on one of their inputs, i.e., the upper AND gate has Q̅S = 0 and the
lower AND gate has K = 0. Consequently, at the input terminals of the master, S = R = 0. When the
clock becomes 1, the state of the master does not change , it remains in its 1-state. Upon returning the
clock to 0, the slave which in turn takes on the value of master, also remains in its 1-state.

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 Digital System Design 18EE35

Fig 3.9 (a) Master-slave JK flip-flop Logic diagram

Fig 3.9 (b) Function table Fig 3.9 ( c) Logic Symbol

On the other hand, if the master and slave latches are in their 0-state when J = 1, K = 0 and the clock
is low, then Q = QM = QS = 0 and Q̅ = Q̅M = Q̅S = 1. The output of the J-input AND gate is logic 1 and
the output of the K-input AND gate is logic-0. Thus S = 1 and R = 0 at the inputs to the master. When
the clock goes high, the master is set. The 1-state of the master is then subsequently transferred to the
slave when the clock returns to 0. In summary, regardless of its present state when J = 1 and K = 0, the
master-slave JK flip-flop enters or remains in its 1-state upon the occurrence of the pulse signal on the
control line. This corresponds to the third row of the function table.

If J = 0 and K = 1, then the master –slave JK flip-flop enters or remains in its 0-state after a clock
pulse has occurred. This is shown in the second row of the function table. The first row indicates that

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the master-slave JK flip-flop retains its current state when J = K = 0 during a clock pulse. Similarly, the
last row indicates that whenever the clock is low i.e., C = 0, the state of the flip-flop does not change.

From the above analysis, the logic-1 values on the J and K lines were assumed to be applied prior to
the application of the clock pulse. In actually these values can occur anytime while the control signal is
1 the master is enabled. The timing diagram is shown in Fig 3.9 (d). For simplicity propagation delays
are assumed to be equal.

Fig 3.9 ( d) Timing diagram for a Master-slave JK flip-flop.

3.3.3 Additional Types of Master-lave flip-flops

From the master-slave SR and JK flops additional types of flip-flops can be constructed. By placing an
inverter between the S and R inputs of a master-slave SR flip-flop, master-slave D flip-flop is obtained
and shown in Fig 3.10 (a) and Fig 3.11 (b)

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 Digital System Design 18EE35

Fig 3.10 (a) Master-slave D flip-flop Logic diagram Fig 3.10 (b) Logic symbol

Another type of master slave flip-flop is shown in Fig 3.11(a) where the J and K input terminals are
tied together so that T = J = K. In this case the flip-flop changes state or toggles with each control pulse
if T = 1 and retains its current state with each control pulse if T = 0. This is called a master-slave T flip-
flop. The function table and logic symbol are shown in Fig 3.11(b ) and Fig 3.12 (c)

Fig 3.11 (a) Master-slave T flip-flop Fig 3.11 (b) Function table

Fig 3.11 ( c) Logic Symbol

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3.4 Edge-Triggered Flip-Flops

The basic master-slave flip-flop, the master is enabled during the entire period the control input is 1.
This results in 0’s and 1’s catching. To avoid the catching problem, the signals on the information lines
are restricted from changing during the time the master is enabled. In this way the state of the master is
established during the positive edge of the control signal and then transferred to the slave on the
negative edge of the control signal.

Edge triggered flip-flops use just one of the edges of the control. i.e., clock signal to affect the
reading of the information input lines. This is referred to as the triggering edge. These flip-flops are
designed to use either positive or negative transition of the control signal for this purpose. Once the
triggering edge occurs, the flip-flop remains unresponsive to information input changes until the next
triggering edge of the control signal.

3.4.1 The Positive – Edge- Triggered D Flip-Flop

Positive Edge Triggered D Flip-flop Logic diagram

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 Digital System Design 18EE35

Table Symbol

The logic diagram of a positive-edge-triggered D flip-flop is shown above where D is the information
input and C is the control, or clock, input. By positive- edge-triggered it is meant that the setting or
resetting of the flip-flop is established by the rising, or positive, edge of the control signal. The
behavior of the positive- edge-triggered D flip-flop, given, is similar to that of the D latch, with the
major difference being that the value of the D input is transferred to the output only as a consequence
of the rising edge of the signal on the control line. Thus, the positive edge of the control input has the
effect of sampling the D input line. This is indicated in the function table by the ↑ symbol. At all other
times, including the time while the clock is at 1, the D input is inhibited and the state of the flip-flop
can- not change.

To see how the positive-edge-triggered D flip-flop operates, consider the logic diagram Nand-gates 5
and 6 serve as an SR latch whose behavior was previously described by the function table Thus, as long
as 5 = R = 1, the state of the latch cannot change; while whenever either S or R is 0, but not both, the
latch sets or resets, respectively.

Assume the control input, i.c., clock, C, is 0. Regardless of the input at D, the outputs of nand-gates 2
and 3 are 1. These signals are applied to the SR output latch, causing it to hold its current state. Now
assume that D is also 0. This holds the output of gate 4 at 1. In turn, the output of gate 1 is 0 since the
outputs of gates 2 and 4 are 1's. When the clock goes from 0 to 1, i.e., the positive edge of the control
signal, all three inputs to gate 3 become 1, causing the output of the gate to change to 0. Meanwhile, the
output of gate 2, 5, remains at 1 since the output of gate 1 is still 0. The 0 on the R line and the 1 on the
S line cause the SR latch to enter or re- main in its reset state, i.e., Q = 0 and Q = 1. In addition, the

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output of gate 3, which is currently 0, is also fed back as an input to gate 4. This now keeps the output
of gate 4 at 1, and any subsequent changes in the D input while C is I have no effect upon the output of
gate 4 and, correspondingly, gate 1. Thus, after the occurrence of the positive edge of the clock signal
when D= 0, the flip-flop is in its 0-state and any changes in the D input are inhibited even though the
clock is 1. Again assume C = 0, but now let D 1. As before, the outputs of gates 2 and 3 are 1, causing
the SR latch to hold its current state. However, the D 1 input causes the output of gate 4 to be 0, and
this output, in turn, causes the output of gate I to be 1. Now when the clock changes to 1, both inputs to
gate 2 are 1 and, consequently, its output, S, becomes 0. Since the output of gate 4 is 0, the output of
gate 3. R. remains at 1. The S 0 and R= 1 results in the setting of the SR latch consisting of gates 5 and
6. The 0 output from gate 2 serves as an input to both gates 1 and 3 that, in turn, guarantees that their
outputs remain at 1. Thus, if D should subsequently change from 1 to 0 while the clock is 1, causing the
output of gate 4 to change, then the outputs of gates 1 and 3 do not change. Therefore, once the posi-
tive edge of the clock has occurred, changes in the D input while C I have no effect upon the state of
the flip-flop.

In summary, only upon the occurrence of the positive edge of the clock signal does the flip-flop
respond to the value of the D input. Once the new output state is established, changes in the D input
while C = 1 are ineffectual. When the clock signal returns to 0, both S and R become 1, and the SR
latch retains the state entered as a consequence of sampling the D input by the positive edge of the
control signal.

Two logic symbols for the positive-edge-triggered D flip-flop are shown. Since the outputs of the flip-
flop respond essentially immediately to the positive edge of the control signal, postponed-output
indicators do not appear. To signify that the output change can only occur as a consequence of the
transition of the control signal, a triangular symbol, called the dynamic-input indicator, is used at the
control input of the logic symbol.

Below shows the timing diagram for the positive-edge-triggered D flip-flop. For simplicity, the finite
slopes of the rising and falling edges of the signals are not shown and all propagation delays are
assumed to be equal.

Padmashree H R, Dept. of E&E, JNNCE Shivamogga. page 20

 Digital System Design 18EE35

Timing Diagram of Positive Edge Triggered D flip-flop

Padmashree H R, Dept. of E&E, JNNCE Shivamogga. page 21