Project Report
On
A Robust and Low Power 7T Dual-Vt SRAM Circuit
Submitted by:
Anant Tiwari (2021H1230226H)
Arpit Goel (2021H1230219H)
Aakash Guwalani (2021H1230235H)
Aviral Srivastava (2021H1230233H)
Maharshi Pandya(2021H1230215H)
ABSTRACT
A seven transistors (7T) dual threshold voltage SRAM cell is implemented in this paper for
improved Static noise Margin (SNM), improved leakage power consumption and improved
read & write delays. We used Minimum sized dual-threshold-voltage transistors in the cross-
coupled inverters that contributes in significant reduction of the leakage power consumption.
With the proposed 7T SRAM cell, the storage nodes are isolated from the bitlines during a
read operation, thereby it enhances the data stability as compared to the conventional six
transistors (6T) SRAM cell.
CIRCUIT SCHEMATICS (45nm Technology node)
CONVENTIONAL 6T SRAM CELL
PROPOSED 7T SRAM CELL WITH PRE-CHARGE CIRCUIT
Explanation of the Circuit operation
The circuit schematic of the proposed SRAM cell with transistors sized for a 45nm CMOS
technology is shown in above Fig. The cross-coupled inverters that are formed by the
transistors NM0, PM1, NM3, and PM2 store a single bit of information. The new data on to
the cell is passed through write bitline WBL and the pass transistor NM1. Alternatively,to read
data into the cell the read bitline RBL and the transistor stack formed by NM2 and NM4 are
used. Two separate control signals Read and Write are used for controlling the read and the
write operations, respectively, with the proposed circuit as shown in above Figure.
READ OPERATION
RBL is pre-charged to VDD, before the start of Read operation . As the read signal Read
transitions to VDD the read operation begins but the Write signal Write is maintained at
VGND. If “1” is stored at Node1, RBL is discharged through the transistor stack formed by
N4 and N5. Alternatively, if a “0” is stored at Node1 RBL is maintained at VDD. During read
operation,the storage nodes (Q and Q_Bar) are completely isolated from the bitlines. So there
is a significant improvement in data stability in comparison to the standard 6T SRAM cell.
The RBL through the pre-charge circuit is conditionally discharged through the NM2- NM4
stack during a read operation.
WRITE OPERATION
Prior to a write operation the WBL is charged (discharged) to VDD (VGND) to get ready to
force a “1” (“0”) onto Q. To start the write operation, the write signal Write transitions to
VDD while the read signal Read is maintained at VGND. The data is forced onto Node Q
through the low-Vt bitline access transistor NM1.
To be able to write a “0” onto Node Q, the pass transistor NM1 must be stronger as compared
to the pull-up transistor PM2. Alternatively, to be able to write a “1” onto Node Q, the pass
transistor NM1 must be stronger as compared to NM0. Furthermore, since NM1 transfers a
degraded “1” (due to the Vt drop across the N-channel access transistor), the inverter formed
by NM3 and PM1 is required to have a low switching threshold voltage that assists the transfer
of a full “1’ onto Node Q. These design requirements are achieved by employing dual-Vt
transistors within the cross-coupled inverters (high-Vt transistors NM0, PM2, and PM1 and
a low-Vt transistor NM3), as shown in Fig.
The use of minimum sized high-Vt transistors reduces the leakage power without degrading
the read speed with the proposed technique.
RESULTS (45nm Technology Node)
WRITE-OPERATION
Here, in the write operation we can observe that with every rising pulse edge of Write Signal,
output node Q stores data whatever is fetched from word bit-line Vin and opposite value is
stored at node Q_Bar of the cross coupled inverters.
READ-OPERATION
In the Read operation the pre-charge circuit is forced to VDD followed by an alternating pulse
wave. Whenever the read signal transitions to High, Vout follows Q_Bar. Here also
complementary data (Q and Q_Bar) are read into the cross-coupled inverters. Here Vout
transitions occur at every rising edge of Read enable signal whenever pre-charge waveform is
activated.
The pre-Charge consists of a PMOS transistor PM3 and a load capacitance connected across
the stacking and read enable transistors NM2 and NM4.
So we can observe that read and write operations are successfully implemented.
READ & WRITE DELAY
Read and Write delays are calculated as the time-difference of output waveform (Read
/Write) to make transition from 10% to 90% of final values of Q and Q_Bar.
Read delay for 7T SRAM (45 nm) = (18.2 ns -18 ns) [10%-90% value for falling edge]
= 200 ps.
Write delay for 7T SRAM (45 nm) = (33.43 ns -33.20 ns) [90%-10% value for rising edge]
= 230 ps.
Comparing results with conventional 6T SRAM at 45 nm.
Read delay for 6T SRAM (45 nm) = (30.97 ns -30.55 ns) [10%-90% value for falling edge]
= 420 ps.
Write delay for 6T SRAM (45 nm) = (10.213 ns -10.11 ns) [90%-10% value for rising edge]
= 103 ps.
Subsequently the results are compared with 6T SRAM (90nm) ,7T (65nm) and 6T(65nm)
with cell ratio 2.
STATIC NOISE MARGIN (SNM) [45 nm Technology Node]
The stability of SRAM cell is mainly defined by the use of SNM which is the maximum value
of DC noise voltage that can be tolerated without changing/flipping the internal storage state
of the SRAM.
When VDD is maintained in Node Q of the 7T SRAM cell , Node Q_Bar is switches strictly
to 0V due to the total decoupling of the bitlines from the data storage nodes at the time of read
operation. Alternatively, when VDD is set at Node Q of standard 6T SRAM cell , Node Q_bar
jumps to a higher steady state voltage as there is voltage division between the access transistor
and pull-down transistor in the inverter at the time of read [Link], Data stored in
conventional 6T SRAM cell is more prone to noise disturbance during read access as Node
Q_Bar voltage is already high. On the other hand, by decoupling the data from the bit lines the
cell stability is notably increased in the new 7T SRAM cell.
We calculate SNM by taking minimum of the two largest possible squares that we can fit in
the upper and lower butterfly curve.
Here, dimensions of largest square in upper butterfly curve = (351 mV * 351 mV)
And, dimensions of largest square in lower butterfly curve = (409 mV * 409 mV)
So, the calculated SNM is minimum of the two is 351 mV.
LEAKAGE POWER CONSUMPTION [45 nm Technology Node]
The leakage power consumption of 7T SRAM at 45 nm is 57.7 nW ( as VDD=1 V at 45nm).
The leakage power is calculated as the average of current flowing from negative terminal of
VDD multiplied with VDD.
Results at the Other Technology Nodes
6T SRAM (at 90nm)
READ-OPERATION CIRCUIT
WRITE OPERATION CIRCUIT
READ OPERATION WAVEFORM
WRITE OPERATION WAVEFORM
READ & WRITE DELAY
Read and Write delays are calculated as the time-difference of output waveform (Read
/Write) to make transition from 10% to 90% of final values of Q and Q_Bar.
Read delay for 7T SRAM (45 nm) = (10.252 ns -10.152 ns) [10%-90% value for falling
edge]
= 100 ps.
Write delay for 7T SRAM (45 nm) = (10.23 ns -10.15 ns) [90%-10% value for rising edge]
= 80 ps.
STATIC NOISE MARGIN (SNM)
We calculate SNM by taking minimum of the two largest possible squares that we can fit in
the upper and lower butterfly curve.
Here, dimensions of largest square in upper butterfly curve = max (370 mV * 407 mV)
And, dimensions of largest square in lower butterfly curve = max (373 mV * 380 mV)
So, the calculated SNM is minimum of the two is 370 mV.
LEAKAGE POWER CONSUMPTION
The leakage power consumption of 6T SRAM at 90 nm is 151 nW ( as VDD=1.2 V at 90nm).
The leakage power is calculated as the average of current flowing from negative terminal of
VDD multiplied with VDD (1.2V).
6T SRAM (at 45nm)
READ-OPERATION CIRCUIT
WRITE OPERATION CIRCUIT
READ OPERATION WAVEFORM
WRITE OPERATION WAVEFORM
READ & WRITE DELAY
Read and Write delays are calculated as the time-difference of output waveform (Read
/Write) to make transition from 10% to 90% of final values of Q and Q_Bar.
Read delay for 6T SRAM (45 nm) = (30.87 ns -30.54 ns) [10%-90% value for falling edge]
= 420 ps.
Write delay for 6T SRAM (45 nm) = (10.31 ns -10.18 ns) [90%-10% value for rising edge]
= 103 ps.
STATIC NOISE MARGIN (SNM)
We calculate SNM by taking minimum of the two largest possible squares that we can fit in
the upper and lower butterfly curve.
Here, dimensions of largest square in upper butterfly curve = max (415 mV * 433 mV)
And, dimensions of largest square in lower butterfly curve = max (424 mV * 413 mV)
So, the calculated SNM is minimum of the two is 424 mV.
LEAKAGE POWER CONSUMPTION
CONCLUSION
READ DELAY ANALYSIS
Delay(ps)
600
500
400
300
Delay(ps)
480
200 420
320
100 200
100
0
6T(45nm)[CR=2]7T(45nm)[CR=2]6T(65nm)[CR=2]7T(65nm)[CR=2]6T(90nm)[CR
=1]
WRITE DELAY ANALYSIS
Delay(ps)
350
300
250
200
310 Delay(ps)
150
270
230
100
50 103
80
0
6T(45nm)[CR=27] T(45nm)[CR=26] T(65nm)[CR=27] T(65nm)[CR=26] T(90nm)[CR=1]
Here, we have compared the read and write delays between conventional 6T and
proposed 7T across 45nm,65nm(referred paper) and 90nm.
Here at 45 nm read delay performance of 7T SRAM is 52.3% better than
corresponding 6T SRAM .However the write delay has degraded by 68%.The read
delay is reduced with the proposed technique due to the lower resistance of the
read access delay path as compared to the standard 6T SRAM cells.
Also we can observe that when we scale down from 65nm to corresponding 45nm
both read and write delays are reduced .I have also compared the read and write
delays with 6T SRAM at 90nm and we see delays are much less. The inconsistency
is due to different cell ratio and beta value of 1.
STATIC NOISE MARGIN ANALYSIS
SNM(mV)
6T(90nm)[CR=1] 380
7T(65nm)[CR=2] 370
6T (65nm)[CR=2] 445
SNM(mV)
7T(45nm)[CR=2] 351
6T (45nm)[CR=2] 424
0 50 100 150 200 250 300 350 400 450 500
So, here we can observe that SNM decreases with technology scaling as we scale
down to 45nm from 65nm. The SNM is the minimum DC noise voltage necessary
to flip the state of an SRAM cell.
At each corresponding technology (be it 45nm or 65nm ) we can observe that our
proposed 7T SRAM has better SNM than conventional 6T SRAM which ensures
better cell stability. The SNM of 6T SRAM at 90nm is taken considering cell ratio
[Link] all are observed with cell ratio 2.
LEAKAGE POWER CONSUMPTION ANALYSIS
LEAKAGE POWER CONSUMPTION(nW)
6T(90nm)[CR=1] 151
7T(65nm)[CR=2] 22
6T(65nm)[CR=2] 38 LEAKAGE POWER
CONSUMPTION(nW)
7T(45nm)[CR=2] 57.7
6T(45nm)[CR=2] 73.9
0 20 40 60 80 100 120 140 160
As ,we can observe here as we scale down from 65nm to 45nm the corresponding
static leakages have increased. But both in 45nm and 65nm leakage power
consumption of 7T SRAM is significantly lower than conventional 6T SRAM due
to stacking effect of transistors NM2 and NM4.
Leakage power of 6T SRAM at 90nm is abruptly high cause of different supply
voltage and different cell ratio(beta=1).