Class D amplifier

 Class D amplifiers are much more efficient than Class AB power amplifiers.

 As such, Class D amplifiers do not need large transformers and heavy heat
sinks, which means that they are smaller and lighter in weight than an
equivalent Class AB amplifier.

 All power devices in a Class D amplifier are operated in on/off mode.

 These amplifiers use pulse width modulation.

Comparison of Amplifier classes

Parameters A AB B C D
Operating 3600 1800-3600 1800 Less than Pulse
Cycle 1800 operation
Power 25-50% Between 78.5% Typically
efficiency 25%(50%) over 90%
and 78.5%
Series fed class A amplifiers

 It is a fixed bias circuit.

 The transistor used is a power transistor that is capable of operating in the

range of a few to tens of watts.
 This circuit is not the best to use as a large-signal amplifier because of its poor
power efficiency.

 The beta of a power transistor is generally less than 100, the overall amplifier
circuit using power transistors that are capable of handling large power or
current while not providing much voltage gain.

DC bias operation

 The dc bias set by 𝑉𝐶𝐶 and 𝑅𝐵 fixes the dc base-bias current at

𝑉𝐶𝐶 − 0.7V
𝐼𝐵 =
𝑅𝐵

with the collector current then being

𝐼𝐶 = 𝛽𝐼𝐵
 with the collector–emitter voltage then

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶

 To appreciate the importance of the dc bias on the operation of the power

amplifier, consider the collector characteristic shown in Fig .

 The intersection of the dc bias value of 𝐼𝐵 with the dc load line then
determines the operating point (Q-point) for the circuit.

 If the dc bias collector current is set at one-half the possible signal swing
𝑉
(between 0 and 𝐶𝐶⁄𝑅 ), the largest collector current swing will be possible.
𝐶

 Additionally, if the quiescent collector-emitter voltage is set at one-half the

supply voltage, the largest voltage swing will be possible.

AC Operation

 When an input ac signal is applied to the amplifier, the output will vary from
its dc bias operating voltage and current.

 A small input signal, as shown in Fig., will cause the base current to vary
above and below the dc bias point, which will then cause the collector current
(output) to vary from the dc bias point set as well as the collector–emitter
voltage to vary around its dc bias value.
  As the input signal is made larger, the output will vary further around the
established dc bias point until either the current or the voltage reaches a
limiting condition.

 For the current this limiting condition is either zero current at the low end or
𝑉𝐶𝐶
⁄𝑅 at the high end of its swing.
𝐶
 For the collector–emitter voltage, the limit is either 0 V or the supply
voltage𝑉𝐶𝐶 .

Power Considerations

 The power into an amplifier is provided by the supply.

  With no input signal, the dc current drawn is the collector bias current,𝐼𝐶𝑄 .

 The power then drawn from the supply is

𝑃𝑖 (𝑑𝑐 ) = 𝑉𝐶𝐶 𝐼𝐶𝑄

Output power

 The output voltage and current varying around the bias point provide ac power
to the load.

 The ac signal,𝑉𝑖 , causes the base current to vary around the dc bias current and
the collector current around its quiescent level, 𝐼𝐶𝑄 .

 The larger the input signal, the larger the output swing, up to the maximum set
by the circuit.

Using rms signals

P0 (ac) = VCE (rms)IC (rms)

= IC 2 (rms)R C

VC 2 (rms)
=
RC

Using peak signals

The ac power delivered to the load may be expressed using

VCE (p)IC (p)

P0 (ac) =
2

IC 2 (p)
= RC
2
 VCE 2 (p)
=
2R C

Using peak-to-peak signals

The ac power delivered to the load may be expressed using

VCE (pp)IC (pp)

P0 (ac) =
8

IC 2 (pp)
= RC
8

VCE 2 (pp)
=
8R C

Efficiency

The efficiency of an amplifier represents the amount of ac power delivered (transferred)

from the dc source. The efficiency of the amplifier is calculated using

P0 (ac)
%η = × 100%
Pi (dc)

Maximum Efficiency

 For the class A series-fed amplifier, the maximum efficiency can be

determined using the maximum voltage and current swings.

 For the voltage swing it is

 VCE (pp) = VCC
 For the current swing it is
VCC
IC (pp) =
RC

 Using the maximum voltage swing in the equation below yields

VCE (pp)IC (pp)

P0 (ac) =
8

VCC
VCC
⁄R
C
=
8
𝑉𝐶𝐶 2
=
8𝑅𝐶
 The maximum power input can be calculated using the dc bias current set to
one-half the maximum value:

VCC /RC
Maximum Pi (dc) = VCC (maximumIC ) = VCC 2

𝑉𝐶𝐶 2
=
2𝑅𝐶
 Then the maximum efficiency is given by,

P0 (ac)
%η = × 100%
Pi (dc)

𝑉𝐶𝐶 2⁄
8𝑅𝐶
= 2
𝑉𝐶𝐶 ⁄
2𝑅𝐶
= 25%
 The maximum efficiency of a class A series fed amplifier is thus seen to be
25%.

 The maximum efficiency occurs only for ideal conditions of both voltage and
current swing .thus practical circuits will have less than this percentage.
TRANSFORMER-COUPLED CLASS A AMPLIFIER

 A form of class A amplifier having maximum efficiency of 50% uses a

transformer to couple the output signal to the load as shown in Fig.

 The transformer can step up or step down a voltage applied to primary coil.

VOLTAGE TRANSFORMATION

 The transformer can step up or step down a voltage applied to one side directly
as the ratio of the turns (or number of windings) on each side.

 The voltage transformation is given by

𝑉2 𝑁2
=
𝑉1 𝑁1
  Equation shows that if the number of turns of wire on the secondary side is
larger than on the primary, the voltage at the secondary side is larger than the
voltage at the primary side.

CURRENT TRANSFORMATION

 The current in the secondary winding is inversely proportional to the number

of turns in the windings.

 The current transformation is given by

I2 N1
=
I1 N2

 If the number of turns of wire on the secondary is greater than that on the
primary, the secondary current will be less than the current in the primary.

IMPEDANCE TRANSFORMATION

 Since the voltage and current can be changed by a transformer, an impedance

“seen” from either side (primary or secondary) can also be changed.
  As shown in Fig, impedance 𝑅𝐿 is connected across the transformer
secondary.

 This impedance is changed by the transformer when viewed at the primary

side (𝑅𝐿 ′ ).

𝑉2
𝑅𝐿 𝑅2 ⁄𝐼 𝑉2 𝐼1 𝑉2 𝐼1 N2 N2 N2
2
′ = = = = = = ( )2
𝑅𝐿 𝑅1 𝑉1⁄ 𝐼2 𝑉1 𝑉1 𝐼2 N1 N1 N1
𝐼1

N
 If we define a = N1 , where a is the turns ratio of the transformer, the above
2
equation becomes
𝑅𝐿 ′ 𝑅1 N1
= = ( )2 = a2
𝑅𝐿 𝑅2 N2

 We can express the load resistance reflected to the primary side as

𝑅𝐿 ′ = a2 𝑅𝐿
Where 𝑅𝐿 ′ is the reflected impedance.

Signal Swing and Output Ac Power

 Figure shows the voltage and current signal swings from the circuit of
Transformer-coupled audio power amplifier.

 From the signal variations shown in Fig, the values of the peak-to-peak Signal
swings are

𝑉𝐶𝐸 (𝑝𝑝) = 𝑉𝐶𝐸𝑚𝑎𝑥 − 𝑉𝐶𝐸𝑚𝑖𝑛

 𝐼𝐶 (𝑝𝑝) = 𝐼𝐶𝑚𝑎𝑥 − 𝐼𝐶𝑚𝑖𝑛

 The ac power developed across the transformer primary can then be calculated
using

(𝑉𝐶𝐸𝑚𝑎𝑥 − 𝑉𝐶𝐸𝑚𝑖𝑛 )(𝐼𝐶𝑚𝑎𝑥 − 𝐼𝐶𝑚𝑖𝑛 )

𝑃0 (𝑎𝑐 ) =
8

 For the ideal transformer, the voltage delivered to the load can be calculated
using the following equation.
N2
𝑉𝐿 = 𝑉2 = V
N1 1
 The power across the load can then be expressed as
𝑉𝐿 2 (𝑟𝑚𝑠)
𝑃𝐿 =
𝑅𝐿

N
 Similarly the load current can be calculated as 𝐼𝐿 = 𝐼2 = N1 IC with the output
2
ac power
𝑃𝐿 = 𝐼𝐿 2 (𝑟𝑚𝑠)𝑅𝐿

Efficiency

 The input dc power obtained from the supply is calculated from the supply dc
voltage and thus average power drawn from the supply.

Pi (dc) = VCC ICQ

 For the transformer-coupled amplifier, the power dissipated by the transformer
is small (due to the small dc resistance of a coil) and is ignored.
  The only power loss considered here is that dissipated by the power transistor
and calculated by

𝑃𝑄 = 𝑃𝑖 (𝑑𝑐 ) − 𝑃0 (𝑎𝑐)

Where 𝑃𝑄 is the power dissipated as heat.

P0 (ac)
%η = × 100%
Pi (dc)

Maximum theoretical efficiency

 For a class A transformer-coupled amplifier, the maximum theoretical

efficiency goes up to 50%.

 Based on the signals obtained using the amplifier, the efficiency can be
expressed as

VCE − VCEmin 2
%η = 50( max ) %
VCEmax + VCEmin

 Larger the value of VCEmax and smaller the value of VCEmin , the closer the
efficiency approaches the theoretical limit of 50%.

Class B Amplifier operation

 Class B operation is provided when the dc bias leaves the transistor biased just
off, the transistor turning on when the ac signal is applied.

 This is essentially no bias and conducts for only one half cycle.

 To obtain output for full cycle, it is required to use two transistors and have
each conduct on opposite half-cycles, the combined operation providing a full
cycle of output on opposite half cycles of output signal.
  Since one part of the circuit pushes the signal high during one half cycle and
other part pulls the signal low during the other half cycle, the circuit is referred
to as push-pull circuit.

 Class B operation provides greater efficiency than was possible using single
transistor in class A operation.

Input (DC) Power

 The amount of input power can be calculated using

𝑃𝑖 (𝑑𝑐 ) = 𝑉𝐶𝐶 𝐼𝑑𝑐
Where 𝐼𝑑𝑐 is the average or dc current drawn from the power supplies.

 In class B operation, the current drawn from a single power supply has the
form of a full-wave rectified signal, while that drawn from two power supplies
has the form of a half wave rectified signal from each supply.

 In either case, the value of the average current drawn can be expressed as
2
𝐼𝑑𝑐 = 𝐼(𝑝)
𝜋
where I(p) is the peak value of the output current waveform.
 Hence input power is equal to
2
𝑃𝑖 (𝑑𝑐 ) = 𝑉𝐶𝐶 𝐼(𝑝)
𝜋

Output (AC) Power

  The power delivered to the load (usually referred to as a resistance,𝑅𝐿 ) can be
calculated using any one of a number of equations.

 If one is using an rms meter to measure the voltage across the load, the output
power can be calculated as

𝑉𝐿 2 (𝑟𝑚𝑠)
𝑃0 (𝑎𝑐 ) =
𝑅𝐿
 If one is using an oscilloscope, the peak, or peak-to-peak, output voltage
measured can be used:

𝑉𝐿 2 (𝑝𝑝) 𝑉𝐿 2 (𝑝)
𝑃0 (𝑎𝑐 ) = =
8𝑅𝐿 2𝑅𝐿
 The larger the rms or peak output voltage, the larger the power delivered to the
load.

Efficiency

 The efficiency of the class B amplifier can be calculated using the basic
equation:

P0 (ac)
%η = × 100%
Pi (dc)

𝑉𝐿 2 (𝑝)⁄
2𝑅𝐿
=
2
𝑉𝐶𝐶 𝜋 𝐼 (𝑝)

𝑉𝐿 (𝑝)
using 𝐼 (𝑝 ) = ⁄𝑅
𝐿

π 𝑉𝐿 (𝑝)
%η = × 100%
4 𝑉𝐶𝐶
  Equation shows that the larger the peak voltage, the higher the circuit
efficiency, up to a maximum value when 𝑉𝐿 (𝑝) = 𝑉𝐶𝐶 , this maximum
efficiency then being

π
maximum efficiency = × 100% = 78.5%
4

Power dissipated by output transistors

 The power dissipated (as heat) by the output power transistors is the difference
between the input power delivered by the supplies and the output power
delivered to the load.
𝑃2𝑄 = 𝑃𝑖 (𝑑𝑐 ) − 𝑃0 (𝑎𝑐)
where𝑃2𝑄 is the power dissipated by the two output power transistors
 The dissipated power handled by each transistor is then
𝑃2𝑄
𝑃𝑄 =
2

Maximum Power Considerations

 For class B operation, the maximum output power is delivered to the load
when 𝑉𝐿 (𝑝) = 𝑉𝐶𝐶
𝑉𝐶𝐶 2
𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑃0 (𝑎𝑐 ) =
2𝑅𝐿
 The corresponding peak ac current I(p) is then
𝑉𝐶𝐶
𝐼 (𝑝 ) =
𝑅𝐿
 The maximum value of average current from the power supply is
2 2 𝑉𝐶𝐶
𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝐼𝑑𝑐 = 𝐼 (𝑝) =
𝜋 𝜋 𝑅𝐿
 Using this current to calculate the maximum value of input power results in
2 𝑉𝐶𝐶 2𝑉𝐶𝐶 2
𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑃𝑖 (𝑑𝑐 ) = 𝑉𝐶𝐶 (𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝐼𝑑𝑐 ) = 𝑉𝐶𝐶 ( )=
𝜋 𝑅𝐿 𝜋𝑅𝐿
 The maximum circuit efficiency for class B operation is then
P0 (ac)
%η = × 100%
Pi (dc)
 𝑉𝐶𝐶 2⁄
2𝑅𝐿
= 2 × 100%
2𝑉𝐶𝐶 ⁄
𝜋𝑅𝐿
𝜋
= × 100%
4
= 78.54%

Efficiency in another form

 The maximum efficiency of a class B amplifier can also be expressed as

follows:
𝑉𝐿 2 (𝑝)
𝑃0 (𝑎𝑐 ) =
2𝑅𝐿

2 𝑉𝐿 (𝑝)
𝑃𝑖 (𝑑𝑐 ) = 𝑉𝐶𝐶 𝐼𝑑𝑐 = 𝑉𝐶𝐶 [ ]
𝜋 𝑅𝐿

𝑉𝐿 2 (𝑝)⁄
P0 (ac) 2𝑅𝐿
%η = × 100% = × 100%
Pi (dc) 2 𝑉 (𝑝)
VCC [ 𝐿 ]
𝜋 𝑅𝐿

𝑉𝐿 (𝑝)
= 78.54 × 100%
𝑉𝐶𝐶

Class B amplifier circuits

 A number of circuit arrangements for obtaining class B operation are possible.

 The input signals to the amplifier could be a single signal, the circuit then
providing two different output stages, each operating for one-half the cycle.

 If the input is in the form of two opposite polarity signals, two similar stages
could be used, each operating on the alternate cycle because of the input
signal.
 One means of obtaining polarity or phase inversion is using a transformer, the
transformer coupled amplifier having been very popular for a long time.

 Figure shows a center-tapped transformer to provide opposite phase signals.

 If the transformer is exactly center-tapped, the two signals are exactly opposite
in phase and of the same magnitude.

 Opposite polarity inputs can easily be obtained using an op-amp having two
opposite outputs or using a few op-amp stages to obtain two opposite polarity
signals.

 The circuit of Fig. uses a BJT stage with in-phase output from the emitter and
opposite phase output from the collector.
Transformer coupled push-pull amplifier

 The circuit of Fig. uses a center-tapped input transformer to produce opposite

polarity signals to the two transistor inputs and an output transformer to drive
the load in a push-pull mode of operation.

 During the first half-cycle of operation, transistor 𝑄1 is driven into conduction,

whereas transistor 𝑄2 is driven off.

 The current 𝐼1 through the transformer results in the first half-cycle of signal to
the load.

 During the second half-cycle of the input signal 𝑄2 conducts whereas 𝑄1 stays
off, the current 𝐼2 through the transformer resulting in the second half-cycle to
the load.

 The overall signal developed across the load then varies over the full cycle of
signal operation.
Complementary symmetry circuits

 Every transistor will conduct for half cycle.

 Single input signal is applied to the base of both transistors.
 npn transistor will be biased in conduction for positive half cycle of the input.
 During negative half cycle pnp transistor is biased into conduction when input
goes to negative.

Disadvantages

 One disadvantage is that the need of two separate voltage supplies.

  Cross over distortion in the output signal.
 This cross over distortion is referred to as the nonlinearity in the output signal
during cross over from positive to negative or vice-versa.

Amplifier distortion

 Any signal varying over less than the full 3600 cycle is considered to have
distortion.

 An ideal amplifier is capable of amplifying a pure sinusoidal signal to provide

a larger version, the resulting waveform being a pure sinusoidal frequency
sinusoidal signal.

 When distortion occurs, output will not be an exact duplicate of input signal
(except for magnitude).

 Distortion can occur because the device characteristic is not linear. In this case
non linear or amplitude distortion occurs.

 Distortion can also occur because the circuit elements and devices respond to
the input signal differently at various frequencies, this being frequency
distortion.

 One technique for describing distorted but period waveforms uses Fourier
analysis, a method that describes any periodic waveform in terms of its
fundamental frequency component and frequency components at integer
multiples- these components are called harmonic components or harmonics.

Harmonic Distortion

 A signal is considered to have harmonic distortion when there are harmonic

frequency components.

 If fundamental frequency has amplitude A1, and nth frequency component has
an amplitude of An.

 Harmonic distortion can be defined as

 |𝐴 𝑛 |
% 𝑛𝑡ℎ ℎ𝑎𝑟𝑚𝑜𝑛𝑖𝑐 𝑑𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛 = %𝐷 = × 100%
|𝐴1 |

Total harmonic distortion

When an output signal has a number of individual harmonic distortion components, the
signal can be seen to have a total harmonic distortion based on the individual elements as
combined by relation

%THD = √(D2 2 + D3 2 + D4 2 + ⋯ . . ) × 100%

Second harmonic distortion

1
((ICmax + ICmin ) − ICQ
D2 = |2 | × 100%
(ICmax − ICmin )

In voltage terms,

1
(VCEmax + VCEmin ) − VCEQ
D2 = |2 | × 100%
(VCEmax − VCEmin )

Power of signal having distortion

 Power delivered to the load resistor 𝑅𝐶 due to the fundamental component of

the distorted signal is
𝐼1 2 𝑅𝐶
𝑃1 =
2
 Total power due to all the harmonic components of the distorted signal is,
𝑅𝐶
𝑃 = (𝐼1 2 + 𝐼2 2 + 𝐼3 2 + ⋯ )
2

 In terms of Total harmonic distortion

2 𝑅𝐶
𝑃 = (1 + 𝐷2 2 + 𝐷3 2 + ⋯ )𝐼1
2

𝑃 = (1 + 𝑇𝐻𝐷2 )𝑃1
UNIT- V VLSI DESIGN

As seen the capacitances of drain diffusion region, source diffusion regions and gate over field region are
denoted by Cdb, Csb and Cgb. The capacitances of gate- drain and gate- source are denoted by Cgd and Cgs.

The above high frequency small signal model can be further simplified as shown below,

SIMPLIFIED HIGH FREQUENCY SMALL SIGNAL MODEL

The current gain can be given as,

𝒊𝒅𝒔 𝜷 𝑽𝒈𝒔 − 𝑽𝑻𝑯𝑵

=
𝒊𝒈 𝒋𝟐𝝅𝒇 𝑪𝒈𝒃 + 𝑪𝒈𝒔 + 𝑪𝒈𝒅

What is a Current Mirror/ Ideal Current Mirror?

An ideal current mirror is a two-port circuit that accepts an input current Iin and produces and output current
Iout = Iin. Since current sensing is best done with a low resistance, for example an ammeter, the ideal current
source will have zero input resistance. An ideal current source has a high output resistance and,
hence, so will an ideal current mirror. In this way, the ideal current mirror faithfully reproduces the input
current regardless of the source and load impedances to which it is connected.

Simple CMOS Current Mirror:

A SIMPLE CMOS CURRENT MIRROR

Page 3
UNIT- V VLSI DESIGN

A simple CMOS current mirror is shown in figure, in which it is assumed that both the transistors are in the
active region. If the finite output impedances of the transistors (Q1 and Q2) are ignored and are of same size,
then Q1 and Q2 will have the same current since both have same gate- source voltage Vgs.

When considering finite output impedance, which ever transistor has a larger drain- source voltage Vds will
also have a larger current and the finite output impedance of the transistors will cause the small signal output
impedance of the current mirror i.e. the small signal impedance looking into the drain of Q2, to be less than
infinite.

To find the output impedance of the current mirror, rout, the small signal circuit is analyzed after placing a
signal source X, at the output node. As per definition,

𝑉𝑋
𝑟𝑜𝑢𝑡 =
𝑖𝑋

Where iX is the current flowing out of the source and into the drain of Q2.

SMALL SIGNAL MODEL FOR Q1 EQUIVALENT SMALL SIGNAL MODEL FOR Q1

Consider the small signal model of Q1 alone as shown which is a low frequency small signal model. It is to
be noted that Q1 is diode connected i.e. its drain and gate are connected and Iin does not exist in the small
signal model, Iin is replaced with an open circuit because it is an independent current source. This model can
further be reduced by Thevenins equivalent circuit. The Thevenins equivalent output voltage is 0 since the
circuit is stable and contains no input signal. This circuit’s Thevenins equivalent output impedance is found
by applying a test signal voltage, Vy at V1 and measuring the signal current, iY, as shown. Here the current
iy is given as,

𝑽𝒚 𝑽𝒚
𝒊𝒚 = + 𝒈𝒎𝟏 𝑽𝒈𝒔𝟏 = + 𝒈𝒎𝟏 𝑽𝒚
𝒓𝒅𝒔𝟏 𝒓𝒅𝒔𝟏

Recalling the output impedance is given by,

𝑉𝑦 1
𝑟𝑜𝑢𝑡 = = || 𝑟
𝑖𝑦 𝑔𝑚1 𝑑𝑠1

This is because rds1 >> 1/ gm1. We approximate the output impedance equal to 1/ gm1, which results in the
equivalent model as shown for Q1.

Page 4
UNIT- V VLSI DESIGN

SMALL SIGNAL MODEL FOR CMOS CURRENT MIRROR EQUIVALENT SMALL SIGNAL MODEL FOR CMOS CURRENT MIRROR

Further we lead to the small signal model of the CMOS current mirror as shown, where Vgs2 has been
connected to ground via a resistance of 1/ gm1. Since no current flows through 1/ gm1 resistor, Vgs2 = 0, no
matter what voltage Vx is applied to the current mirror output. This is no surprise since MOS transistors
operate unilaterally at low frequencies. Thus, since gm2 Vgs2 = 0, the circuit is simplified to the equivalent
small signal model as shown. The small signal output impedance, rout is equal to rds2.

Therefore, a simple CMOS current mirror has a small-signal input resistance of 1/ gm1 and a small-signal
output resistance rds2.

Common Source Amplifier:

A COMMON SOURCE AMPLIFIER

SMALL SIGNAL EQUIVALENT MODEL FOR COMMON SOURCE AMPLIFIER

Page 5
UNIT- V VLSI DESIGN

The common-source amplifier is a popular gain stage, especially when high input impedance is desired as
shown. The use of an active load takes advantage of the nonlinear, large-signal transistor current–voltage
relationship to provide large small-signal resistances without large dc voltage drops.

Here, an n- channel common-source amplifier has a p- channel current mirror used as an active load to
supply the bias current for the drive transistor. By using an active load, a high- impedance output load can
be realized without using excessively large resistors or a large power- supply voltage. As a result, for a given
power supply voltage, a larger voltage gain can be achieved using an active load than would be possible if a
resistor were used for the load.

For example, if a 100 kΩ load were required with a bias current, a resistive- load approach would require a
power- supply voltage of 100 kΩ × 100 µA. An active load takes advantage of the nonlinear, large-signal
transistor current voltage relationship to provide large small-signal resistances without large dc voltage
drops.

The small- signal equivalent circuit for the low-frequency analysis of the common-source amplifier as
shown, where Vin and Rin are the Thévenin equivalent of the input source. It is assumed that the bias
voltages are such that both transistors are in the active region. The output resistance, R 2- is made up of the
parallel combination of the drain- to- source resistance of Q1, i.e. rds1, and the drain- to- source resistance of
Q2, i.e. rds2. Notice that the voltage- controlled current source modeling the body effect has not been
included since the source is at a small signal ground, and, therefore, this source always has 0 current.

Using the small signal analysis, we have vgs1 = vin and, therefore,

Depending on the device sizes, currents, and the technology used, a typical gain for this circuit is in the
range of -5 to -100. To achieve similar gains with resistive loads, much larger power-supply voltages must
be used which also greatly increases the power dissipation.

Common Drain Amplifier or Source Follower:

A COMMON DRAIN AMPLIFIER OR SOURCE FOLLOWER

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UNIT- V VLSI DESIGN

A general use of current mirrors is to supply the bias current of source- follower amplifiers, as shown. Here
Q1 is the source follower and Q2 is an active load that supplies the bias current of Q1. These amplifiers are
commonly used as voltage buffers and are therefore commonly called source followers.
They are also referred to as common-drain amplifiers, since the input and output nodes are at the gate and
source nodes respectively, with the drain node being at small-signal ground. Although the dc level of the
output voltage is not the same as the dc level of the input voltage, ideally the small-signal voltage gain is
close to unity. In reality, it is somewhat less than unity. However, although this circuit does not generate
voltage gain, it does have the ability to generate current gain.

LOW FREQUENCY SMALL SIGNAL MODEL EQUIVALENT SMALL SIGNAL MODEL

It is to be noted that the voltage-controlled current source that models the body effect of MOS transistors has
been included because the source is not at small- signal ground. The body effect is a major limitation on the
small signal gain. From the small signal it is seen that rds1 is parallel to rds2, also that the voltage-controlled
current source modelling the body effect produces a current that is proportional to the voltage across it. This
relationship makes the body effect equivalent to a resistor of size 1/ gs1, which is also in parallel with
rds1 and rds2. Thus the small signal model is reduced to equivalent small signal model as shown in which
Rs1 = rds1 || rds2 || 1/ gs1.

Now writing the nodal equation at Vout, and noting that Vgs1 = Vin – Vout, we have,

To minimize circuit equation errors, a consistent methodology should be maintained when writing nodal
equations. The methodology employed here is as follows: The first term is always the node at which the
currents are being summed. This node voltage is multiplied by the sum of all admittances connected to the
node. The next negative terms are the adjacent node voltages, and each is multiplied by the connecting
admittance. The last terms are any current sources with a multiplying negative sign used if the current is
shown to flow into the node.

Solving for Vout/ Vin, we have,

Normally, gs1 is on the order of one-tenth to one-fifth that of gm1. Also, the transistor output admittances, gds1
and gds2, might be one-tenth that of the body-effect parameter, gs1. Therefore, it is seen that the body-effect
parameter is the major source of error causing the gain to be less than unity. Notice also that at low
frequencies the stage is completely unilateral. In other words, there is no signal flow from the output to the
input.

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UNIT- V VLSI DESIGN

Common Gate Amplifier:

The common-gate amplifier as shown provides a voltage gain comparable to that of the common-source
amplifier, but with a relatively low input resistance on the order of 1/gm.

A COMMON GATE AMPLIFIER- WITH CURRENT MIRROR ACTIVE LOAD

A common application for a common- gate amplifier is as the first stage of an amplifier where the input
signal is a current, in such cases a small input impedance is desired in order to ensure all of the current
signal is drawn into the amplifier, and none is “lost” in the signal source impedance. Aside from its low
input impedance, the common gate amplifier is similar to a common-source amplifier, in both cases the
input is applied across Vgs, except with opposite polarities, and the output is taken at the drain. Hence, in
both cases the small signal gain magnitude approximately equals the product of gm and the total impedance
at the drain.

If we use straightforward small-signal analysis, when the impedance seen at (in this case, the output
impedance of the current mirror formed by Q2) is much less than rds1, the input impedance, rout, is found to
be 1/ gm1 at low frequencies. However, in integrated applications, the impedance seen at Vout is often on the
same order of magnitude or even much greater than rds1. In this case, the input impedance at low frequencies
can be considerably larger than 1/ gm1. To see this result, consider the small-signal model as shown. In this
model, the voltage-dependent current source that models the body effect has been included. It is noticed that
Vgs1 = - Vs1 and therefore the two current sources can be combined into a single current source, as shown in
the simplified small signal model. This simplification is always possible for a transistor that has a grounded
gate in a small-signal model, and considerably simplifies taking the body effect into account.

LOW FREQUENCY SMALL SIGNAL MODEL EQUIVALENT OR SIMPLIFIED SMALL SIGNAL MODEL

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UNIT- V VLSI DESIGN

The body effect for transistors with grounded gates can be ignored, and then, after the analysis is complete,
simply replace the constants gmi with gmi + gsi. However, now we include the body-effect parameter
throughout the analysis.

At node Vout, we have

(Equation 1)

Rearranging slightly, we have,

(Equation 2)
g m1
Here the gain is approximately equal to GL + g ds 1 .

The current going into the source of Q1 is given by,

(Equation 3)

Combining equations 2 and 3 to find the input admittance yin = 1 rin we have,
is g m 1 +g s 1 +g ds 1 gm 1
yin = = g = g (Equation 4)
vs1 1+ ds 1 1+ ds 1
GL GL

Alternatively, we have,
1 1 RL
rin = = 1+
yin g m1 rds 1

With the p- channel active load, RL = rds2. Since, in this case, is approximately the same magnitude as rds1,
the input impedance, rin, is about 2/ gm1for low frequencies- twice as large as the expected value of 1/ gm1.
This increased input impedance must be taken into account in applications such as transmission- line
terminations. In some examples, the current-mirror output impedance realized by is much larger than
(i.e. RL >> rds1, ), and so the input impedance for this common-gate amplifier is much larger than
1/ gm1. This increased input impedance often occurs in integrated circuits and is not commonly known.

The attenuation from the input source to the transistor source can be considerable for a common-gate
amplifier when Rs is large. This attenuation is given by,
Vs1 Gs
=
Vin Gs + yin
Using equation 4 to replace yin, we have- using admittance- divider rule,
Vs1 Gs
= gm 1 (Equation 5)
V in Gs + g
1+ ds 1
GL

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UNIT- V VLSI DESIGN

Using equation 2 and 5, to find the overall dc gain- which is given as,

𝑉𝑜𝑢𝑡 Gs g m1
𝐴𝑉 = =
𝑉𝑖𝑛 GL + g ds 1
g m1
Gs + g
1 + Gds 1
L

Source Degenerated Current Mirror:

SOURCE DEGENERATED CURRENT MIRROR AND ITS SMALL SIGNAL MODEL

A source degenerated current mirror is used to increase the output impedance. A source degenerated current
mirror is shown along with its small signal model.

Here since no current flow through the gate, the gate voltage is 0 V. The current ix sourced by the applied
voltage source is equal to the current through the degeneration resistor Rs. Therefore, we have,

(Equation 1)

And

(Equation 2)

Setting ix equal to the total current through gm2 Vgs and rds2 gives,

(Equation 3)

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UNIT- V VLSI DESIGN

Substituting equation 1 and 2 in 3 gives,

(Equation 4)

Rearranging, we find the output impedance to be given as,

(Equation 5)

Where gds2 is equal to 1/ rds2, which is much less than gm2.

Since the gate is at a small signal ground, the body effect can be considered by replacing gm2 in the above
equation with gm2 + gs2.

Therefore equation 5 becomes,

HIGH OUTPUT IMPEDANCE CURRENT MIRRORS:

The current mirrors which have output impedances that are larger than that of a simple current mirror by a
factor of gm rds- the maximum gain of a single transistor are high output impedance current mirrors.

The two types of high output impedance current mirrors are:

1. Cascode Current Mirror

2. Wilson Current Mirror

Cascode Current Mirror:

CASCODE CURRENT MIRROR

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UNIT- V VLSI DESIGN

A cascode current mirror is shown in figure, where the output impedance looking into the drain of Q 2 is rds2,
which is analysed very similar to the analysis of a simple current mirror. Therefore the output impedance
can be immediately derived by considering Q4 as a current source with a source degeneration resistor of
value equal to rds2.

It is to be noted that the addition of a cascode device to a CMOS current mirror increases its output
resistance by approximately the gain of the cascode device, gm rds.
Using,

And noting that Q4 is now the cascode transistor rather than Q2, we have,

Where now Rs = rds2. Therefore the output impedance is given as,

Thus, the output impedance has been increased by a factor of gm rds2, which is an upper limit on the gain of a
single transistor MOS gain- stage, and might be a value between 10 and 100, depending on the transistor
sizes and currents and the technology being used. This significant increase in output impedance can be
instrumental in realizing single stage amplifiers with large low frequency gains.

The disadvantage in a cascode current mirror is that it reduces the maximum output signal swings possible
before transistors enter the triode region. This can be illustrated by having a n- channel transistor to be in the
active region- also called the saturation or pinch- off region, its drain- source voltage must be greater than
Veff, where Veff is,

Which is further given by,

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UNIT- V VLSI DESIGN

Wilson Current Mirror:

The Wilson current mirror is an example of using shunt- series feedback to increase the output impedance.
The Wilson current mirror is shown in figure.

WILSON CURRENT MIRROR

Here Q2 senses the output current and then the mirrors it to ID1, which in turn is subtracted from the input
current Iin, it is to be noted that ID1 must be precisely equal Iin- otherwise the voltage at the gate of Q3, Q4
would either increase or decrease, and the negative feedback loop forces this equality. This feedback
arrangement increases the output impedance by an amount equal to 1 plus the loop gain.

Assuming all devices are matched, the output impedance without the feedback due to Q1, Q3 would be 2 rds4,
taking into account that Q4 has source degeneration equal to 1/ gm2 (i.e. the small signal impedance of diode
connected Q2), which is responsible for the 2 factor.

The loop gain is approximately given as,

g m1 (rds 1 || rin )
AL =
2
Where rin is the input impedance of the biasing current source Iin.

The factor of 1/ 2 is due to the voltage attenuation from the gate of Q4 to its source, caused by the source
degeneration of the diode connected Q2.

Assuming rin is approximately equal to rds1, then the loop gain is given by,

g m1 rds 1
AL =
4
And the output impedance is therefore given as,

g m1 (rds 1 || rin ) g m1 rds 1

rout = rds 4 = rds 4
2 2

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UNIT- V VLSI DESIGN

It is seen from the equation of output impedance that the output impedance of the Wilson current mirror is
roughly one- half the output impedance for that of a cascode current mirror. For this reason the cascode
current mirror is often preferred over the Wilson current mirror.

The output voltage swing, the minimum allowed voltage across the current mirror before Q4 enters the triode
region is 2 Veff1 + Vin, which is similar to that of the cascode current mirror.

Therefore, it is noted that in the Q3 is not required in the Wilson current mirror, it has been included to give
Q1 and Q2 the same drain- source bias voltages and thus minimizes the inaccuracies caused by the large
signal output impedances of the transistors. Without this transistor the output current would be slightly
smaller than the input current because VDS1 would be larger than VDS2, keeping the small signal output
impedance remaining the same.

Cascode Amplifier or Cascode Gain Stage:

The cascode amplifier is commonly used configuration in digital IC design which consists of a
common source connected transistor feeding into a common gate connected transistor.

Two illustrations/ types of cascode amplifiers are:

1. Telescopic cascode amplifier

2. Folded- cascode amplifier

TELESCOPIC CASCODE AMPLIFIER FOLDED CASCODE AMPLIFIER

As seen telescopic cascode amplifier has both common n- channel transistors Q1- common source and
Q2- common gate, this is referred as a telescopic cascode amplifier and as seen a folded cascode amplifier
has a n- channel common source transistor Q1 and a p- channel common gate , this is referred as a
folded cascode amplifier.

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UNIT- V VLSI DESIGN

The folded cascode amplifier allows the dc level of the output signal to be the same as the dc level of the
input signal, but this folded cascode amplifier is slower than the telescopic cascode amplifier because of the
impedance levels of the folded cascode is roughly three times larger due to the smaller transconductance of
the p- channel transistors as compared to n- channel transistors, although parasitic capacitances at the source
of the cascode transistor are similar in both the amplifier cases.

There are two major reasons for the demand of these amplifier stages i.e.:

1. They can have larger gain for a single stage due to large impedances at the output- to enable this high
gain the current sources connected to the output nodes are realized using high quality cascode current
mirrors. This gain is obtained without degradation in speed and sometimes also with an increase in
speed.
2. They limit the voltage across the input drive transistor- this minimizes any shorted short channel
effects which becomes more important with modern technologies having very low short channel
length transistors.

The analysis of the cascode gain stage/ amplifier is based on the telescopic stage,

WKT, using current mirrors, the impedance looking into the drain of cascode transistor Q2 is approximately
given by,

rd2 = g m2 rds 1 rds 2

The total impedance at the output node is rds2 in parallel with RL, where RL is the output impedance of the
bias current source, Ibias. Assuming Ibias is a high quality source with output impedance of the order of,

R L = g m−p r 2 ds −p (Equation 1)

Then the total impedance at the output node is,

g m r 2 ds
R out = (Equation 2)
2
Now, to find the approximate low- frequency gain, we use a part of the analysis of the common gate
amplifier. i.e.

is g m1 + g s1 + g ds 1 g m1
yin = = g = g
vs1 1 + Gds 1 1 + Gds 1
L L

Therefore, the low frequency impedance looking into the source of the common gate or cascode, transistor
Q2 is given as,
g m2 + g s2 + g ds 2 g m2
yin 2 = g ds 2 = g (Equation 3)
1+ G 1 + Gds 2
L L

Substituting equation 1 in equation 3, we get,

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UNIT- V VLSI DESIGN

gm
yin 2 = g = g ds Equation 3
1 + 2 ds
g ds
gm

Therefore, the gain from the input to the source of Q2 is given by,
vs2 g m1 gm
= =−
vin g ds 1 + yin 2 2g ds

Therefore, the overall gain is given by,

vs2 vout gm g m2 g m g m2 1 gm 2
AV = =− =− =−
vin vs2 2g ds GL + g ds 2 2g ds g ds 2 2 g ds

Problems:

1. Considering the current mirror shown, where Iin = 100 µA and each transistor has
W/L = 100 µm/ 1.6 µm. Given that µnCox = 92 µA/ V2, Vtn = 0.8V and
rds = [8000L (µm)] / [ID (mA)], find rout for the current mirror and the value of gm1. Also, estimate the
change in Iout for 0.5V change in the output voltage.

Sol.

Given:

Iin = 100 µA

W/L = 100 µm/ 1.6 µm

µnCox = 92 µA/ V2

Vtn = 0.8V

rds = [8000L (µm)] / [ID (mA)]

∆V = 0.5V

To find:

rout = ?

gm1 = ?

∆Iout = ?

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UNIT- V VLSI DESIGN

Here, W/L ratios of Q1 and Q2 are same, the nominal value of Iout equals that of Iin = 100 µA.

Therefore, rout is given as,

8000 L (μm) 8000 × 1.6

rout = rds 2 = = = 128 kΩ
ID (mA) 0.1

The value of gm1 is given by,

100
g m1 = 2μn Cox (W/L) ID1 = 2 × 92 × 100 = 1.07 mA/ V
1.6

The change in the output current can be estimated as,

∆V 0.5
∆Iout = = = 3.9 μA
rout 128

2. Assuming all transistors have W/L = 100 µm/ 1.6 µm as shown with µ nCox = 90 µA/ V2,
µpCox = 30 µA/ V2, Ibias =100 µA, rds- n = [8000L (µm)] / [ID (mA)] and
rds- p = [12000L (µm)] / [ID (mA)]. Find the gain of the stage?

Sol.

Given:

W/L = 100 µm/ 1.6 µm

µnCox = 90 µA/ V2

µpCox = 30 µA/ V2

Ibias =100 µA

rds- n = [8000L (µm)] / [ID (mA)]

rds- p = [12000L (µm)] / [ID (mA)]

To find:

AV = ?

WKT, the gain AV is given as,

AV = −g m (rds 1 || rds 2 )

Now finding,

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UNIT- V VLSI DESIGN

100
g m1 = 2μn Cox (W/L) Ibias = 2 × 90 × 100 = 1.06 mA/ V
1.6

8000 L (μm) 8000 ×1.6 12000 L (μm) 12000 ×1.6

rds 1 = = = 128 kΩ and rds 2 = = = 192 kΩ
I D (mA ) 0.1 I D (mA ) 0.1

Now substituting the above found values in,

AV = −g m (rds 1 || rds 2 )

We get,

AV = −1.06(128 || 192) = −81.4

Therefore, the gain of the stage/ amplifier is – 81.4 respectively.

3. Consider a source follower as shown, where all transistors have W/L = 100 µm/ 1.6 µm with
µnCox = 90 µA/ V2, µpCox = 30 µA/ V2, Ibias =100 µA, rds- n = [8000L (µm)] / [ID (mA)] and
1
γn = 0.5 V 2. Find the gain of the stage?

Sol.

Given:

W/L = 100 µm/ 1.6 µm

µnCox = 90 µA/ V2

µpCox = 30 µA/ V2

Ibias =100 µA

rds- n = [8000L (µm)] / [ID (mA)]

1
γn = 0.5 V 2

To find:

AV = ?

WKT, the gain AV of a source follower is given as,

g m1 g m1
AV = =
g m1 + g s1 + g ds 1 + g ds 2 g m1 + g s1 + 1 r + 1 r
ds 1 ds 2

Now finding,

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UNIT- V VLSI DESIGN

100
g m1 = 2μn Cox (W/L) Ibias = 2 × 90 × 100 = 1.06 mA/ V
1.6

8000 L (μm) 8000 × 1.6

rds 1 = rds 2 = = = 128 kΩ
ID (mA) 0.1

γ gm 0.5 g m
g s1 = = = 0.15 g m = 0.15 × 1.06 = 0.16 mA/ V
2 VSB + 2∅F 2 2 + 0.7

(Here VSB = 2 and ∅F = 0.35 → Standard Values)

Therefore, the gain is given by,

1.06
AV = = 0.86
1.06 + 0.16 + 1 128 + 1 128

Therefore, the gain of the source follower is 0.86 respectively.

4. Consider a source degenerated current mirror as shown, where Iin = 100 µA, each transistor
W/L = 100 µm/ 1.6 µm, Rs = 5 kΩ, µnCox = 92 µA/ V2, Vtn = 0.8V and
rds = [8000L (µm)] / [ID (mA)]. Find rout for the current mirror. Assume the body effect can be
approximated by gs = 0.2 gm.

Sol.

Given:

W/L = 100 µm/ 1.6 µm

Rs = 5 kΩ

µnCox = 92 µA/ V2

Vtn = 0.8V

rds = [8000L (µm)] / [ID (mA)]

gs = 0.2 gm

Iin = 100 µA

To find:

rout = ?

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UNIT- V VLSI DESIGN

WKT,

rout = rds 2 1 + R s (g m2 + g s2 )

Iout = Iin

Now finding,

100
g m2 = 2μn Cox (W/L) Iout = 2 × 92 × 100 = 1.07 mA/ V
1.6

8000 L (μm) 8000 × 1.6

rds 2 = = = 128 kΩ
ID (mA) 0.1

Therefore, the rout is given by,

rout = 128 1 + 5 1.07 + 0.2 × g m

rout = 128 1 + 5 1.07 + 0.2 × 1.07 = 950 kΩ

Therefore, the output resistance rout of the source denegation current mirror is 950 kΩ respectively.

5. Consider a cascode current mirror as shown, where Iin = 100 µA, each transistor
W/L = 100 µm/ 1.6 µm, µnCox = 92 µA/ V2, Vtn = 0.8V and
rds= [8000L (µm)] / [ID (mA)]. Find rout for the current mirror. Assume the body effect can be
approximated by gs = 0.2 gm. Also find the minimum output voltage at Vout such that the output
transistors remain in the active region.

Sol.

Given:

W/L = 100 µm/ 1.6 µm

µnCox = 92 µA/ V2

Vtn = 0.8V

rds = [8000L (µm)] / [ID (mA)]

gs = 0.2 gm

Iin = 100 µA

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UNIT- V VLSI DESIGN

To find:

rout = ?

Vout = ?

WKT,

rout = rds 4 1 + rds 2 (g m4 + g s4 )

Iout = Iin

Now finding,

100
g m4 = 2μn Cox (W/L) Iout = 2 × 92 × 100 = 1.07 mA/ V
1.6

8000 L (μm) 8000 × 1.6

rds 2 = rds 4 = = = 128 kΩ
ID (mA) 0.1

Therefore, the rout is given by,

rout = 128 1 + 128(1.07 + 0.2 × 1.07) = 21 MΩ

The maximum output voltage is determined by,

Vout = 2 × Veff + Vtn

Now finding,

2Iout 2 × 100
Veff = = = 0.19V
W 100
μn Cox 92 ×
L 1.6

Therefore,

Vout = 2 × 0.19 + 0.8 = 1.18V

Therefore, the output resistance rout of the cascode current mirror is 21 MΩ and the maximum output voltage
is 1.18V respectively.

Assignment:

1. What is transistor sizing?

2. Assuming gm is on the order of 0.5 mA/ V and rds is on the order of 100 kΩ, then what is the gain of
the cascode amplifier?

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