Chapter 1

Introduction to 8051
Microcontroller and its
Architecture

Microcontrollers have become the heart of modern embedded systems ( ),

enabling intelligent control in countless devices from appliances to indus-
trial machines. In this chapter, we introduce the 8-bit 8051 microcon-
troller—one of the classic and widely studied microcontrollers developed
by Intel in 1981. We will explore how microcontrollers differ from general-
purpose microprocessors, understand the classification and applications of
microcontrollers, and then delve into the architecture of the 8051 including
its internal components, memory organization, and pin configuration. Impor-
tant concepts like the stack, program counter, data pointer, and clock/reset
mechanisms will be explained in detail.

1.1 Microcontroller vs. Microprocessor

A microcontroller (MCU) is essentially a small computer on a single
chip, containing a processor core, memory, and input/output peripherals in-
tegrated together. In contrast, a microprocessor (MPU) is a CPU (central
processing unit) that lacks on-chip memory and I/O – it requires external
components to function as a system01. Microcontrollers are designed for spe-
cific control-oriented tasks (as in embedded applications), whereas micropro-
cessors are geared toward general-purpose computing with higher processing
power.
Table 1.1 summarizes the key differences between microcontrollers and
microprocessors:

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 In summary, a microcontroller can be thought of as a single-chip computer
optimized for controlling devices, whereas a microprocessor is a powerful CPU
chip that forms the brain of a computer and needs additional support chips.
For instance, an 8051 microcontroller can be used to automatically control
appliances like a washing machine or microwave (specific task), while an
Intel Pentium microprocessor would be used in a PC for general computing
needs23.

1.2 Hierarchy of Microcontrollers

Microcontrollers can be categorized in a hierarchy based on their architecture
and capabilities:

• By Word Length (Bit-Width): Microcontrollers come in 4-bit, 8-

bit, 16-bit, 32-bit, and even 64-bit varieties. Low-end MCUs (4-bit,
8-bit) are used for simple tasks (e.g. in toys or simple sensors), 16/32-
bit MCUs handle moderate complexity (e.g. automotive controllers,
appliances), while high-end 32-bit or 64-bit MCUs (often with ARM
Cortex cores) can run complex applications and basic operating sys-
tems.

• By Memory Architecture: **Harvard architecture** vs. **Von

Neumann (Princeton) architecture**: Harvard MCUs have separate
memories for program and data (which allows simultaneous access, im-
proving speed), whereas Von Neumann MCUs use a single unified mem-
ory for instructions and data. The 8051 uses a Harvard architecture,
with separate code (program) memory and data memory.

• By Instruction Set: **RISC (Reduced Instruction Set Computer)**

vs. **CISC (Complex Instruction Set Computer)** microcontrollers.
RISC microcontrollers (like AVR, some ARM MCUs) have a smaller,
highly optimized set of instructions executing in uniform time, whereas
CISC microcontrollers (like the original Intel 8051) have a larger set of
more complex instructions. Modern microcontrollers often blend fea-
tures of both, but this classification helps understand design philoso-
phies.

This hierarchy illustrates that not all microcontrollers are equal—there is

a spectrum from very simple controllers to sophisticated ones. The Intel 8051
is an 8-bit CISC microcontroller with a Harvard architecture, representative
of early-generation MCUs. Newer families (PIC, AVR, ARM Cortex-M) are

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largely 8/16/32-bit RISC Harvard-architecture MCUs with higher perfor-
mance and more peripherals on chip.

1.3 Applications of Microcontrollers

Microcontrollers are used in almost every industry segment due to their ver-
satility, low cost, and compact size. Some broad application areas (with
examples) are:
• Consumer Electronics and Home Appliances: e.g. microwave
ovens, washing machines, air conditioners, television remote controls,
digital cameras. A microcontroller in these devices manages user in-
puts, sensor readings, and controls outputs (motors, displays) to achieve
the desired functionality.
• Automotive and Transportation: e.g. engine control units (ECU)
in cars, anti-lock braking systems (ABS), airbag controllers, electronic
fuel injection systems, dashboard instrument clusters. Modern vehicles
contain dozens of MCUs ensuring safety and efficiency.
• Industrial Automation and Control: e.g. programmable logic con-
trollers (PLCs), robotic arm controllers, process control in factories,
motor drives, smart sensors. Microcontrollers handle real-time control
tasks and interface with various industrial sensors/actuators.
• Communications and Networking: e.g. routers and networking
equipment, IoT (Internet of Things) devices, wireless sensor nodes.
MCUs manage communication protocols (like WiFi, Bluetooth, Zig-
Bee) and data processing in connected devices.
• Medical Devices: e.g. blood glucose monitors, digital thermometers,
ECG machines, infusion pumps. Reliability of microcontrollers allows
life-critical devices to function consistently.
• Security and Surveillance: e.g. security alarm panels, electronic
door locks, CCTV camera controllers, biometric access systems.
In summary, any product that needs “smarts” and autonomous control likely
has a microcontroller inside. The classification of applications can also be
made by environment: for instance, household, office equipment (printers,
copiers), telecommunications, healthcare, etc. In each case, the microcon-
troller is programmed to handle a dedicated task or a set of tasks for that
product.

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1.4 Embedded Systems Overview and Clas-
sification
An **embedded system** is a specialized computing system that performs
dedicated functions within a larger mechanical or electronic system. It typi-
cally consists of a microcontroller or microprocessor that runs firmware (soft-
ware) to control the device’s operation. Unlike a general-purpose computer,
an embedded system is designed for a specific task. For example, a digital
camera’s embedded system manages capturing images, storing them, and
interfacing with the user controls.
Definition: Embedded System. An embedded system is an electronic
system that integrates hardware and software (and perhaps mechanical
parts) to perform a specific dedicated function or set of functions. It is
“embedded” as part of a larger system or product and is not typically
directly visible as a standalone computer.
Embedded systems can be classified based on functionality and perfor-
mance requirements:

• Real-Time Embedded Systems: These systems must respond to

events or inputs within strict time constraints. Real-time systems are
often used in critical applications. They are further categorized into:

– Hard real-time systems – missing a deadline could lead to fail-

ure (e.g. automobile airbag controller, anti-lock brakes, medical
monitors).
– Soft real-time systems – deadlines are important but occasional
lapses are tolerable (e.g. audio/video streaming devices).

• Stand-alone Embedded Systems: Systems that operate indepen-

dently without a host computer. They take inputs (sensors or user
input), process data, and produce outputs. Examples: microwave oven
controller, MP3 player, digital thermostat. These systems are self-
contained.

• Networked Embedded Systems (Distributed Embedded Sys-

tems): Systems connected to a network (wired or wireless) to com-
municate and cooperate with other systems. For instance, home au-
tomation devices or a security system’s components communicate over
a network, or a smart IoT sensor node sending data to a cloud server.
Network connectivity adds complexity and capability (e.g. smart home
hubs, industrial SCADA systems).

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 • Mobile Embedded Systems: Portable devices powered by micro-
controllers, designed with emphasis on battery efficiency and compact-
ness. Examples: smartphones (which have multiple embedded con-
trollers for different subsystems), fitness wearables, portable medical
devices. Mobility imposes constraints like low power consumption and
lightweight design.

Embedded systems can also be described as small-scale, medium-scale,

or complex based on the complexity of hardware/software and the bit-width
of the microcontroller used45. Small-scale systems might use 8-bit MCUs and
simple loops (often with no operating system), medium-scale might use 16
or 32-bit MCUs and a real-time operating system (RTOS), while complex
embedded systems may involve 32/64-bit processors and large software with
an OS (for example, the computing system in an advanced drone or an info-
tainment system in a car).
Regardless of category, the 8051 microcontroller can be found at the heart
of many small to medium embedded systems due to its simplicity and reli-
ability. Next, we focus specifically on the architecture and features of the
8051 MCU.

1.5 Architecture of 8051 Microcontroller

The 8051 is an 8-bit microcontroller featuring a Harvard architecture and
originally a CISC instruction set. It integrates CPU, memory, and peripherals
on a single chip. Figure 1.5 shows a simplified block diagram of the 8051
architecture, highlighting its key components:

• An 8-bit CPU (central processing unit) with an Arithmetic Logic Unit

(ALU) that performs arithmetic and logical operations.

• On-chip memory: 4 KB of program memory (ROM/EPROM) and 128

bytes of data memory (RAM).

• 8-bit registers including an Accumulator (register A) and register B,

used for arithmetic operations, and a set of 8 general-purpose working
registers (R0–R7).

• A 16-bit Program Counter (PC) to track the address of the next

instruction, and a 16-bit Data Pointer (DPTR) register for external
data memory addressing.

• A Stack Pointer (SP) register to manage the stack in RAM.

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 • Special Function Registers (SFRs) – various control registers mapped
in upper memory (e.g. timers, I/O ports, serial port, interrupt regis-
ters).

• Four parallel I/O ports (Port 0,1,2,3, each 8-bit) providing 32 I/O
pins.

• Two 16-bit timers/counters for timing operations.

• A serial UART port for serial communication.

• An interrupt controller supporting 5 interrupts (2 external, 3 inter-

nal).

• Oscillator and clock circuitry (which uses an external crystal or clock

input) and a reset circuit.

Simplified block diagram of 8051 Microcontroller Architecture. The 8051

includes a CPU core (with ALU, registers, PC, etc.), on-chip program ROM
and data RAM, I/O ports, timers, serial interface, and an interrupt con-
troller. The oscillator provides the clock signal, and a reset circuit initializes
the system.
The 8051’s CPU is an 8-bit processor, meaning it processes data 8 bits
at a time. It has several important registers:

1.5.1 CPU Registers and Flags

Accumulator (A) and B Register: The Accumulator (A register) is
the primary register used in arithmetic and logic operations – most 8051
instructions involve the Accumulator. The B register is used mainly for
multiplication and division instructions (MUL AB, DIV AB) as a second
operand or to hold results alongside A6. Together, A and B facilitate 16-bit
multiply/divide and act as general-purpose registers if needed.
General Purpose Registers (R0–R7): These eight registers are used
as scratchpad registers for data manipulation. They are not fixed in hardware
locations; instead, they are mapped into the internal RAM. The 8051 has
four register banks (Bank 0 to Bank 3) that each contain 8 registers (R0–R7).
Only one bank is active at a time, determined by the bank select bits (RS0,
RS1) in the Program Status Word (PSW). By default, Bank 0 is selected on
reset, which corresponds to internal RAM addresses 0x00–0x07 for R0–R7.
This banking mechanism allows quick context switching or use of multiple
register sets by changing PSW bits.

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 Program Status Word (PSW) – Flags: The PSW is an 8-bit register
that contains condition flags and status bits reflecting the outcome of oper-
ations and the current state of the processor. Only 6 of the 8 bits are used;
the remaining 2 are user-definable for general use78. The PSW bits are:
The flags CY, AC, and OV are affected by arithmetic operations (useful
for conditional branching or multi-byte math), while P provides a simple
even-parity check of the accumulator. The RS1–RS0 bits are critical for
switching register banks:

RS1 RS0 (PSW.4, PSW.3) Register Bank Address Range for R0–R7
002 Bank 0 (default) 0x00–0x07
012 Bank 1 0x08–0x0F
102 Bank 2 0x10–0x17
112 Bank 3 0x18–0x1F

By changing RS0/RS1, the base address of R0–R7 is changed as shown above.

For example, if RS1RS0 = 102 , then any instruction using R0 refers to address
0x10, R1 refers to 0x11, and so on.

1.5.2 Program Counter (PC) and Data Pointer (DPTR)

The Program Counter is a 16-bit register that always points to the address
of the next instruction to be fetched from program memory10. Each time
an instruction is executed, the PC increments to point to the subsequent
instruction (unless a jump/branch alters the flow). Because it is 16-bit, the
PC in 8051 can address up to 64 KB of program memory (addresses 0000h
to FFFFh). However, the standard 8051 has only 4 KB on-chip ROM; if
external program memory is used, the full 64 KB range can be utilized (with
help of pins like EA, PSEN as discussed later).
The DPTR (Data Pointer) is a 16-bit register primarily used to point
to data in external memory. It is split into two 8-bit registers, DPH (high
byte) and DPL (low byte). DPTR is often used in instructions that involve
external RAM or code memory access (such as moving external data, or as
a pointer in lookup table operations). It can also serve as a general 16-bit
counter or address register in some contexts. Only one DPTR exists in 8051
(some enhanced variants have dual DPTR for faster block moves).

1.5.3 Stack and Stack Pointer (SP)

The stack in 8051 resides in the internal RAM and is used for temporary
storage of data and return addresses during subroutine calls and interrupt

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service routines. It operates in a last-in-first-out (LIFO) manner. The Stack
Pointer (SP) is an 8-bit register that holds the address of the top of the
stack11. On the 8051, the stack grows upward (towards higher memory
addresses).
When data is PUSHed onto the stack, the SP is first incremented by
1, then the value is stored at the new top address. Conversely, on a POP,
the value is read from the address pointed by SP, then SP is decremented
by 1. Because SP is 8-bit, it can point anywhere in the 00h–FFh address
range of internal RAM; however not all of that is actual RAM (beyond 7Fh
is SFR space). In practice, the stack should be kept in the on-chip RAM
area (00h–7Fh, or up to 0xFF if the device has 256 bytes RAM).
By default, after a reset, SP = 0x0712. This means the stack will start
at address 0x08 for the first push (since SP is incremented then used). The
default location (0x08) is right after the register bank 0 area. This default
is chosen so that the registers R0–R7 (which occupy 0x00–0x07 in bank 0)
are not overwritten by the stack. The programmer can reinitialize SP to a
different address if needed (for example, to start the stack at a higher address,
leaving more room for global/variable storage below it).
Definition: Stack. A stack is a section of memory used for temporary
storage in a LIFO manner (Last In, First Out). In 8051, it is typically
used to store return addresses during function calls or interrupts, and to
save registers or data temporarily. The Stack Pointer (SP) register keeps
track of the top of this stack. Each PUSH adds an item to the stack and
increments SP, and each POP removes an item and decrements SP.

1.6 Memory Organization of 8051

The 8051 microcontroller has a Harvard architecture, so it has separate mem-
ory spaces for program code and data:

1. Program Memory (Code Memory): This is where the executable

program code is stored. In a standard 8051, 4 KB of on-chip ROM
(address range 0000h–0FFFh) is provided. Program memory can be
extended externally up to 64 KB total. The PC (program counter)
addresses this memory. If the EA (External Access) pin is pulled low,
the 8051 will fetch code exclusively from external memory (allowing for
bigger programs in ROMs).

2. Data Memory: This is the RAM used for variable storage, stack,
and SFRs. The 8051 has 128 bytes of on-chip internal RAM (00h–7Fh
addresses) plus a separate 128-byte area for SFRs (80h–FFh addresses,

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 not all locations used). Additionally, the 8051 can address up to 64
KB of external data memory (using DPTR and MOVX instructions) if
needed.

1.6.1 Internal RAM Structure (128 bytes)

The internal RAM from 0x00 to 0x7F is organized into several regions (as
depicted in Figure 1.1):
• Register Banks (00h–1Fh): The lowest 32 bytes are grouped into 4
banks of 8 registers each, as discussed earlier. Bank 0 occupies 00h–07h,
Bank 1 occupies 08h–0Fh, Bank 2 is 10h–17h, and Bank 3 is 18h–1Fh.
On reset, Bank 0 is active by default. The registers in the non-selected
banks can also be used as general-purpose RAM if the program is not
actively using those banks.
• Bit-Addressable RAM (20h–2Fh): A unique feature of 8051 is
that 16 bytes of internal RAM (addresses 20h through 2Fh) are bit-
addressable. This means each bit in this range (a total of 16 * 8 =
128 bits) has a unique bit address (00h–7Fh in bit-address space). In-
structions can directly set, clear, AND, OR individual bits in this area
using single-bit instructions. This is extremely useful for flags, status
bits, or boolean variables.
• General Purpose RAM (30h–7Fh): The remaining internal RAM
from 0x30 to 0x7F (80 bytes) is general-purpose memory for data stor-
age, variables, stack (if extended), etc. It can be accessed as bytes.
This is where most user-defined variables and the stack (by default)
reside.
The internal data memory is supplemented by the Special Function
Registers (SFRs) which occupy addresses 0x80 to 0xFF. These are not
RAM locations for general use, but rather each address in this range corre-
sponds to an important control or data register for the 8051’s peripherals.
Not all addresses 0x80–0xFF are implemented; only specific ones mapped to
actual SFRs. Examples of SFRs include:
• Port latches: P0 at 0x80, P1 at 0x90, P2 at 0xA0, P3 at 0xB0 (each byte
controls the digital I/O lines of that port, and is also bit-addressable).
• Processor registers: IE (Interrupt Enable) at 0xA8, IP (Interrupt Pri-
ority) at 0xB8, TMOD (Timer Mode) at 0x89, TCON (Timer Control)
at 0x88, SCON (Serial Control) at 0x98, PCON (Power Control) at
0x87, etc.

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 0x7F

0x80 (SFRs)
General
Purpose
RAM
0x30-0x7F

Bit-
addressable 0x30
RAM
Register
(128 bits) 0x20
Banks
0x20-0x2F
(Bank
Default Stack Start (0x08)
0-3) 0x00
0x00-0x1F

Figure 1.1: Internal RAM layout of 8051 (128 bytes). The lower 32 bytes are
divided into 4 register banks (each bank has registers R0–R7). The next 16
bytes (0x20–0x2F) are bit-addressable memory. The addresses 0x30–0x7F
are general purpose RAM. By default, the stack pointer (SP) is initialized to
0x07, so the first available stack address is 0x08 (indicated by the arrow).

• Data registers: ACC (Accumulator) at 0xE0, B register at 0xF0, SP

at 0x81, DPL at 0x82, DPH at 0x83, PSW at 0xD0.

Some SFRs are bit-addressable (those ending in 0x0 or 0x8 typically). For
instance, PSW at 0xD0 is bit-addressable (so CY is D7h in bit-address space,
etc.), P0–P3 are bit-addressable (each port pin can be accessed as a bit).
It’s important to note that internal RAM (00h–7Fh) and SFRs (80h–FFh)
share the same address range numerically but are separate in how they are ac-
cessed: instructions that reference addresses above 7Fh automatically direct
to SFR memory space. If an 8051 variant has 256 bytes of RAM, the “upper”
128 bytes (0x80–0xFF) are accessed differently (via indirect addressing) to
avoid collision with SFR addresses.

1.6.2 External Memory (Program and Data)

The original 8051 (Intel 8051) is designed to support external memory ex-
pansion:

• External Program Memory: If the on-chip 4 KB is insufficient,

external ROM/EPROM can be connected. The 8051 uses Port 0 and

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 Port 2 to form a 16-bit address bus for external memory (Port 0 serves
as multiplexed low-address/data bus AD0–AD7, Port 2 provides high
address A8–A15). The signal PSEN (Program Store Enable) is an
active-low output that the 8051 uses to read bytes from external pro-
gram memory. The pin EA (External Access) must be held low to
force all fetches to external memory; if EA is high, addresses in range
0000h–0FFFh are fetched from internal ROM, and above that from
external.

• External Data Memory: The 8051 can also interface up to 64 KB of

external RAM or memory-mapped I/O. This is done via the MOVX
(move external) instructions, which use DPTR to supply the address
and use Port 0 (AD0–AD7) and Port 2 (A8–A15) similarly. The signals
RD and WR on Port 3 (P3.7 and P3.6) are used to activate external
data memory read/write. This separate data space is only needed in
applications that require more RAM than the on-chip 128 bytes (for
example, storing large buffers or lookup tables in external RAM).
In many typical embedded projects, external memory is not needed because
the on-chip memories suffice, which simplifies the hardware design.

1.7 8051 Pin Diagram and I/O Ports

The 8051 is commonly available as a 40-pin Dual Inline Package (DIP). The
pins can be grouped as follows:
• 32 pins dedicated to the four 8-bit I/O ports (Port 0, Port 1, Port 2,
Port 3).

• 2 pins for the crystal oscillator input/output (XTAL1, XTAL2).

• 2 pins for power supply (VCC and GND).

• 4 additional control pins: Reset (RST), ALE (Address Latch Enable),

PSEN (Program Store Enable), and EA (External Access).
Figure 1.2 shows the pin layout of the 8051 microcontroller with pin
numbers and their functions:
From the figure and list: - **Port 0 (P0.0–P0.7)**: Pins 32–39. Port 0 is
an 8-bit open-drain bidirectional I/O port. It is the only port without internal
pull-up resistors, meaning it will output a floating high (high-impedance)
when set to logic 1, unless external pull-up resistors are provided. Port 0 has
a dual role: it is also the multiplexed address/data bus for external memory

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 40 - VCC
39 - P0.0 (AD0)
38 - P0.1 (AD1)
P1.0 - 1
37 - P0.2 (AD2)
P1.1 - 2
36 - P0.3 (AD3)
P1.2 - 3
35 - P0.4 (AD4)
P1.3 - 4
34 - P0.5 (AD5)
P1.4 - 5
33 - P0.6 (AD6)
P1.5 - 6
32 - P0.7 (AD7)
P1.6 - 7
P1.7 - 8 31 - EA
RST - 9 30 - ALE
8051 29 - PSEN
P3.0 (RXD) - 10
P3.1 (TXD) - 11 28 - P2.7 (A15)
P3.2 (/INT0) - 12 27 - P2.6 (A14)
P3.3 (/INT1) - 13 26 - P2.5 (A13)
P3.4 (T0) - 14 25 - P2.4 (A12)
P3.5 (T1) - 15 24 - P2.3 (A11)
P3.6 (/WR) - 16 23 - P2.2 (A10)
P3.7 (/RD) - 17 22 - P2.1 (A9)
21 - P2.0 (A8)
XTAL2 - 18
XTAL1 - 19
GND - 20

Figure 1.2: 8051 Pin Configuration (40-pin DIP). Port pins are labeled with
their port designations and alternate functions (for Port 0, Port 2, Port 3).

access. During external memory operations, Port 0 outputs the low-order

address (A0–A7) and then acts as data bus (D0–D7). The ALE signal is
used to latch the address. When not using external memory, Port 0 can be
used as general-purpose I/O (but requires pull-ups for output high). Because
of its open-drain nature, it’s also suitable for bus-oriented applications and
can sink more current. - **Port 1 (P1.0–P1.7)**: Pins 1–8. Port 1 is a pure
8-bit I/O port with internal pull-up resistors. It does not have any alternate
functions in the basic 8051, making it a straightforward general-purpose port.
Writing a 1 to a Port 1 pin will drive it high (logic 1 via internal pull-up),
and writing 0 will drive it low. Port 1 is often used for interfacing with
external devices when no special function is needed on those pins. - **Port
2 (P2.0–P2.7)**: Pins 21–28. Port 2 is an 8-bit I/O port with internal
pull-ups. It serves as the high-order address bus (A8–A15) when interfacing
with external memory (for both program and data memory). If no external
memory is used, Port 2 functions as a normal I/O port. If external memory
is used but the address space is less than 256 bytes, Port 2 lines above the

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address range remain available as I/O. - **Port 3 (P3.0–P3.7)**: Pins 10–17.
Port 3 also has internal pull-ups and is an 8-bit bidirectional port, but each
pin of Port 3 has an alternate function (mostly related to interrupts and
serial I/O): - P3.0 (pin 10) – RXD: Serial input (receive data) for UART. -
P3.1 (pin 11) – TXD: Serial output (transmit data) for UART. - P3.2 (pin
12) – INT0: External Interrupt 0 input. - P3.3 (pin 13) – INT1: External
Interrupt 1 input. - P3.4 (pin 14) – T0: Timer 0 external input (counter
trigger). - P3.5 (pin 15) – T1: Timer 1 external input. - P3.6 (pin 16) –
/WR: External Data Memory Write strobe (active low). - P3.7 (pin 17) –
/RD: External Data Memory Read strobe (active low).
When these functions are not needed, Port 3 pins can be used as gen-
eral I/O. But designers must be careful, e.g., if external interrupts are en-
abled, P3.2/P3.3 will be sampled for interrupt signals. - **XTAL1 (pin 19)
and XTAL2 (pin 18)**: These are connections for the external crystal or
resonator that provides the clock to the 8051. XTAL1 is the input to an
inverting oscillator amplifier, and XTAL2 is the output. Typically a quartz
crystal (such as 11.0592 MHz or 12 MHz) is connected across these pins with
small capacitors (20pF–40pF range) to ground (forming a Pierce oscillator).
Alternatively, an external clock source can be fed into XTAL1 while leaving
XTAL2 unconnected. - **RST (Reset, pin 9)**: This input is an active-high
reset signal. A high on this pin (for a minimum duration of 2 machine cycles)
will reset the microcontroller, terminating all activity and clearing registers
to default states. On reset, the program counter is set to 0000h (beginning
of program memory). Typically, a circuit (as described in the next section)
ensures that RST is held high momentarily at power-up. - **ALE (Address
Latch Enable, pin 30)**: This output pin provides a latch pulse for external
address demultiplexing. It emits a periodic square wave at 1/6th the oscilla-
tor frequency when the 8051 is accessing external memory. During external
memory operations, ALE is high during the byte where Port 0 has address
A0–A7, and falling edge of ALE signals that Port 0 will switch to data for
the next byte. ALE is usually connected to the enable of an external latch
(74HC373 or 74HC573) which holds the low address. If no external memory
is used, ALE still toggles at a constant rate (which can be used for timing
or as a general-purpose clock output in some cases). There is also a setting
in some 8051 variants to turn off the ALE toggling if not needed (to reduce
noise). - **PSEN (Program Store Enable, pin 29)**: This is an active-low
output control signal used to read external program memory. When the
8051 fetches code from external ROM, it activates PSEN (low) to enable the
ROM’s output. PSEN is essentially the read strobe for external program
memory. It is generally connected to the OE (Output Enable) of an external
EPROM or ROM. PSEN is not used for internal code fetches (when running

13
from internal ROM). - **EA (External Access, pin 31)**: EA is an active-
low input that determines the source of program code. If EA is held high
(logic 1) and the address is within the on-chip ROM range (0x0000–0x0FFF
for 4KB), the 8051 will fetch instructions from internal ROM. If the address
exceeds internal memory range or if EA is low, the 8051 will fetch from ex-
ternal program memory. In typical usage, EA is tied high when an on-chip
program is used exclusively. To use all code from external memory, EA is
tied low (in which case the internal ROM is ignored). - **VCC (pin 40) and
GND (pin 20)**: These are the power supply pins. The 8051 requires a +5V
DC supply (VCC = +5V, GND = 0V reference). Some modern variants
might run at lower voltages, but the classical 8051 is 5V.
In summary, the pins of the 8051 either serve as I/O lines or have ded-
icated roles in external memory interfacing and system control. An under-
standing of the pin functions is crucial when designing hardware with the
8051, to ensure proper connections for clock, reset, and any needed external
memory or peripherals.

1.8 Clock Oscillator and Reset Circuitry

The 8051 requires a clock source to drive its operation cycle. It has an on-chip
oscillator amplifier that typically uses an external crystal connected across
XTAL1 and XTAL2. The frequency of the crystal (or external clock input)
determines the speed of the microcontroller.

1.8.1 Clock Oscillator

A common choice is an 11.0592 M Hz crystal for the 8051. This some-
what odd value is popular because it allows standard serial baud rates to be
achieved easily. Another common choice is 12 M Hz for simplicity (which re-
sults in neat timing of 1 µs per machine cycle). The 8051 divides the crystal
frequency by 12 to derive the fundamental machine cycle frequency13. That
is, one machine cycle = 12 oscillator periods in the original 8051 design.1
For example, at 12 MHz crystal frequency: - 1 machine cycle = 12 / 12
MHz = 1 µs. - Many simple instructions execute in 1 machine cycle (1 µs
each), while some take 2 cycles (2 µs), etc. This makes timing calculations
straightforward. - At 11.0592 MHz, one machine cycle = approximately
1.085 µs. This frequency is chosen as it results in integer divides for standard
UART baud rates (e.g., 9600, 19200) using Timer 1.
1
Some modern 8051 derivatives have improved designs with different divisors (e.g. 4
or 6) to achieve higher throughput per MHz, but the classic 8051 uses 12.

14
 To connect a crystal, one end of the crystal is connected to XTAL1 and
the other to XTAL2. Additionally, two small capacitors (typically 20pF
to 33pF) are connected from each XTAL pin to ground. These capacitors
stabilize the oscillation. If a precise external clock source is available, it
can be injected into XTAL1, with XTAL2 left unconnected. Alternatively, a
ceramic resonator can be used instead of a quartz crystal for the oscillator.
Some systems opt for an external oscillator module. In such cases, the
module’s output can drive XTAL1 directly. The oscillator circuit is crucial
because a stable clock ensures the microcontroller’s proper timing.

1.8.2 Reset Circuit

The 8051 must be properly reset on power-up to start execution from the
beginning of memory (0x0000). The RST pin (pin 9) is active high. To
ensure a proper power-on reset (POR), the RST pin should be held high
briefly when power is applied, then allowed to go low so the program can
run.
A typical power-on reset circuit uses a resistor and capacitor (RC)
connected to RST, as shown in Figure 1.3. The capacitor is connected be-
tween RST and VCC, and the resistor between RST and ground (with maybe
a diode for discharge). When power is turned on: - VCC rises, the capacitor
initially behaves like a short, pulling RST towards VCC (logic High). - This
keeps RST high for a short duration (until the capacitor charges through
the resistor). - After some time (determined by the RC time constant), the
capacitor charges and RST voltage drops towards 0 (as the resistor pulls it
down). - This generates a brief high pulse on RST at power-up, resetting the
microcontroller. Manual reset can be implemented by a push-button switch
connected from RST to VCC (often through a series resistor) so that pressing
the button momentarily drives RST high, and a release allows it to return
low.
The reset signal must be held high for at least 2 machine cycles (at least
24 oscillator cycles) to be recognized14. In practice, the RC is chosen to
provide a few milliseconds of High on RST at startup, which is plenty.
After a reset, the 8051 will: - Reload PC to 0000h (so it starts executing
from the first instruction in program memory). - Set the Stack Pointer to 07h
(so stack starts at 08h). - Clear or set specific SFRs to default states (e.g.,
PSW = 0x00, ACC = 0x00, B = 0x00, etc.). Notably, the internal RAM is
not cleared – its contents are indeterminate, but often remain as they were
before reset15 (so a power-on reset may find RAM in a random state). - The
Timer registers, interrupt enable, serial registers all come to a known reset
state (e.g., timers off, interrupts disabled, serial port off).

15
 The designer should ensure the reset circuit is reliable. If RST is not given
a proper pulse at startup, the 8051 might start executing from an undefined
state or not execute the program reliably. Hence the emphasis on a proper
POR circuit or supervisor chip to manage reset.

VCC (+5V)

RST
10 µF
8.2 kΩ

GND

Figure 1.3: Typical reset circuit for 8051 (power-on and manual reset). On
power-up, the capacitor C charges, briefly pulling RST high. The resistor R
then pulls RST low allowing normal operation. The push-button provides a
manual reset by connecting RST to VCC when pressed.

In summary, the clock and reset are fundamental parts of the micro-
controller system design. The clock frequency chosen affects the instruction
timing and peripheral operation (e.g., timer tick rates, serial baud base). The
reset circuit ensures the 8051 starts cleanly. Once the clock is running and
the chip is out of reset, the 8051 will continuously fetch, decode, and execute
instructions from program memory, thus bringing the embedded system to
life.

1.9 Summary
In this unit, we have covered the foundational aspects of microcontrollers
using the 8051 as a representative example:
• Microcontrollers integrate CPU, memory, and I/O peripherals on one
chip, making them ideal for dedicated embedded applications. In con-
trast, microprocessors are standalone CPUs intended for general com-
puting, requiring external resources.

• Microcontrollers can be classified by architecture (Harvard vs. Von

Neumann), instruction set (RISC vs. CISC), and word length (8-bit,

16
 16-bit, 32-bit, etc.), and they are used in a vast array of applications
from home appliances to industrial systems.

• Embedded systems are purpose-built control systems often centered

around a microcontroller. They can be real-time, stand-alone, net-
worked, or mobile systems depending on their design requirements.

• The Intel 8051 microcontroller has an 8-bit CPU and Harvard architec-
ture. It provides on-chip program ROM (4KB) and data RAM (128B),
along with special function registers for controlling built-in peripherals
like timers, serial port, and interrupt logic.

• Key CPU elements of the 8051 include the accumulator (for arith-
metic/logic operations), B register (for multiply/divide), general reg-
isters R0–R7 (which are bank-selectable), and the PSW register con-
taining status flags (carry, auxiliary carry, overflow, parity) and bank
select bits.

• The 8051 uses a stack in internal RAM for temporary storage, with
the stack pointer initialized to 0x07 on reset (stack starts at 0x08 by
default). The program counter (16-bit) tracks instruction addresses,
enabling up to 64KB of code space. The DPTR is a 16-bit index
register mainly for external memory addressing.

• Memory in 8051 is organized into distinct spaces: code (program) mem-

ory and data memory. Internal data memory (128 bytes) is structured
into register banks, a bit-addressable area, and general RAM. Impor-
tant control registers are memory-mapped as SFRs in the upper ad-
dress space. External memory can be added for larger programs (via
PSEN, ALE, EA pins) or additional data storage (via MOVX, using
Port0/Port2 and /RD, /WR strobes).

• The pin configuration of 8051 includes four 8-bit I/O ports. Port 0 and
Port 2 serve a dual role for external memory bus. Port 3 pins have
alternate functions (two external interrupts, two timer inputs, serial
RXD/TXD, and external memory read/write control). Proper use of
these pins is crucial when interfacing the 8051 with other hardware.

• The 8051 requires an external clock source (commonly a crystal res-

onator). One machine cycle consists of 12 oscillator cycles in the stan-
dard 8051, so a 12 MHz crystal yields a 1 µs machine cycle. The reset
input must be handled such that the microcontroller is reliably initial-
ized on power-up or by user command.

17
Overall, the 8051 architecture demonstrates the essential features of a mi-
crocontroller: a self-contained computing unit that can read sensors, make
decisions (based on its program logic), and control outputs in a timely man-
ner. Understanding these fundamentals will aid in learning to program the
8051 and interface it with external devices, which are covered in subsequent
units.

1.10 Multiple Choice Questions (MCQs)

1. Which of the following best describes a microcontroller?

(a) A CPU with integrated memory and peripherals, for dedicated

tasks.
(b) A high-speed CPU meant for general-purpose computations.
(c) An external memory device for storing large programs.
(d) A power supply regulator for circuits.

2. The Intel 8051 microcontroller has an internal RAM of:

(a) 4 KB
(b) 128 bytes
(c) 256 bytes
(d) 4 MB

3. In the 8051, the register that holds the address of the next instruction
to execute is:

(a) The Stack Pointer (SP)

(b) The Program Counter (PC)
(c) The Data Pointer (DPTR)
(d) The Accumulator (A)

4. Which port of 8051 is used as a multiplexed address/data bus when

accessing external memory?

(a) Port 0
(b) Port 1
(c) Port 2
(d) Port 3

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 5. Upon reset, the 8051’s Stack Pointer is set to 07h. What will be the
address of the first value pushed onto the stack after reset (assuming
Bank 0 is in use)?

(a) 07h
(b) 08h
(c) 06h
(d) 0Fh

1.11 Descriptive Questions (GTU Style)

1. Compare microcontrollers and microprocessors. Explain at least
five key differences in terms of architecture, integration of components,
typical applications, and provide examples of each.

2. Draw and explain the architecture of the 8051 microcontroller.

Provide a labeled block diagram and describe the function of each major
component (CPU, memory, I/O ports, timers, serial interface, etc.).

3. Describe the memory organization of 8051. How are the internal

RAM, register banks, bit-addressable area, and SFRs arranged in the
address space? Include a memory map diagram in your explanation.

4. Discuss the 8051 I/O port structure and pin functions. How
do the alternate functions of Port 3 pins differ from Ports 0, 1, and 2?
What are the roles of ALE, PSEN, EA, XTAL1/2, and RST pins in an
8051 system?

5. What is an embedded system? Give a definition and classify em-

bedded systems into different types. Provide an example of each type
and explain how a microcontroller is used in that context.

1.12 Exercises
1. Find at least two everyday devices in your home or surroundings that
likely contain a microcontroller. Identify the tasks the microcontroller
performs in those devices.

2. The 8051 is running with a 11.0592 MHz crystal. Calculate the approx-
imate time for one machine cycle and determine how many machine
cycles occur in one second.

19
3. If the PSW register in an 8051 has the value 0x50 (in hex), identify
which register bank is currently in use and the status of the CY and
AC flags. (Hint: 0x50 in binary is 0101 00002 .)

4. Write the direct memory addresses (in hex) for the following 8051 SFRs:
Accumulator, B register, Stack Pointer, and Port 1. Why can’t these
SFR addresses be used for general RAM access?

5. Suppose you want to interface an external 8 KB RAM to an 8051.

Which pins and signals would be involved in reading from and writing
to this RAM? Sketch a simple diagram showing the connection of the
RAM with the 8051 (no need for exact hardware, just show port usage
and control signals).

20
 Table 1.1: Differences between a Microcontroller and a Microprocessor
Aspect Microcontroller (µC) Microprocessor (µP)
Integration CPU, memory (RAM/ROM), CPU is standalone; requires
I/O ports, etc. all on a single external memory, I/O ports,
chip (self-sufficient system) and peripherals (dependent on
external chips)
Application Designed for specific control Designed for general-purpose
tasks in embedded systems computing tasks (can run large
operating systems)
Memory Includes on-chip program No on-chip program memory;
ROM/Flash and data RAM uses external memory (which
(small, e.g. a few KB) can be large in size)
I/O Multiple built-in I/O ports Limited or no built-in I/O
and interfaces for direct sen- ports; must interface via exter-
sor/actuator connection nal circuits for I/O
Power Consumption Generally low power consump- Higher power consumption
tion (suitable for battery- (due to higher clock speeds
powered devices) and external interfacing)
Performance Typically runs at lower clock Capable of high clock speeds
speeds (e.g. a few MHz) for (hundreds of MHz to GHz) for
simple control tasks complex computations
Architecture Often Harvard architecture Often Von Neumann architec-
(separate program and data ture (shared memory) and can
memory) and many are RISC- be CISC or superscalar designs
based
Cost Overall system cost is low Overall system cost is higher
(many functions on one chip) (requires multiple compo-
nents)
Examples 8051, AVR ATmega, Intel 8086, Intel Pentium,
PIC16F877, ARM Cortex- ARM Cortex-A72 (as part of
M series smartphone SoC)

21
 Bit Name Description
PSW.7 CY (Carry) Carry flag (set if an arithmetic operation results in a carry out or bo
PSW.6 AC (Auxiliary Carry) Auxiliary carry for BCD (binary-coded decimal) arithmetic (carry fr
PSW.5 F0 User flag 0 (available for general purpose use).
PSW.4 RS1 Register bank select bit 1 (with RS0, selects active R0–R7 bank).
PSW.3 RS0 Register bank select bit 0.
PSW.2 OV (Overflow) Overflow flag (set if result of signed arithmetic is out of range).
PSW.1 – (User-definable flag, general purpose).
PSW.0 P (Parity) Parity flag. Set/cleared by hardware after each instruction to indica

Table 1.2: Program Status Word (PSW) Register Bits in 8051. Two bits
(PSW.5 and PSW.1) are available as user-defined flags9.

22