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Practical 10

The document outlines a practical exercise aimed at designing and verifying 4-bit synchronous and asynchronous counters using JK flip-flops. It explains the differences between asynchronous counters, which use a ripple effect driven by the output of previous flip-flops, and synchronous counters, which utilize a global clock for simultaneous output changes. The procedure involves making connections, applying clock signals, and observing the output, with results obtained from simulations on a virtual lab.

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5 views4 pages

Practical 10

The document outlines a practical exercise aimed at designing and verifying 4-bit synchronous and asynchronous counters using JK flip-flops. It explains the differences between asynchronous counters, which use a ripple effect driven by the output of previous flip-flops, and synchronous counters, which utilize a global clock for simultaneous output changes. The procedure involves making connections, applying clock signals, and observing the output, with results obtained from simulations on a virtual lab.

Uploaded by

chaudhariaarzu6116
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Practical: 10

Aim: To Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK flip
flop.

Apparatus: Digital Trainer Kit, IC 7473, Connecting Wires, Etc.

Theory: A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal. Counters are
used in digital electronics for counting purpose, they can count specific event happening in
the circuit. For example, in UP counter a counter increases count for every rising edge of
clock.

1) Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following counters is driven by output of previous flip
flops. We can understand it by following diagram-

Figure-1: Asynchronous Counter Circuit and Timing Diagram

Subject Code: Digital Logic and Design Computer Engineering Department,


Subject Name: 203ES Birla Vishvakarma Mahavidyalaya
It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock
pulse is encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is
like clock pulse for second flip flop) and so on. In this way ripples are generated through Q0,
Q1, Q2, Q3 hence it is also called RIPPLE counter.

2) Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop.

Figure-2: Synchronous Counter Circuit and Timing Diagram

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while
Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.

Subject Code: Digital Logic and Design Computer Engineering Department,


Subject Name: 203ES Birla Vishvakarma Mahavidyalaya
Procedure:

 Do the required connections.


 Give the clock signals and observe the output.

Results:

The simulation of this practical was performed on Virtual lab and the output of the
simulations is as shown below:

4-bit Asynchronous Counter using JK Flip-flop

Subject Code: Digital Logic and Design Computer Engineering Department,


Subject Name: 203ES Birla Vishvakarma Mahavidyalaya
4-bit Synchronous Counter using JK Flip-flop

Conclusion:

Subject Code: Digital Logic and Design Computer Engineering Department,


Subject Name: 203ES Birla Vishvakarma Mahavidyalaya

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