Microprocessor Instructions

General Concepts
A microprocessor instruction is essentially a binary number made up of bit fields that respectively tell the microprocessor the
operation to be performed and the location(s) of the number(s) to be operated.

The bit field of an instruction that tells the operation to be performed is referred to as the opcode. It could specify a move
operation, an add operation, a multiply operation or a branch operation, etc. The numbers that an instruction operates on are
referred to as operands. An operand can be located in a register, a memory location, on a port or can be constructed as part of
the instruction. The bit fields of an instruction that specify the locations of the operands are called operand fields.

In any given bit field of an instruction, a different binary pattern means a different kind of information e.g., different opcodes
have different bit patterns, different registers have different bit pattern representations, different addressing modes have
different bit patterns, etc.

Opcode Mnemonics
It is difficult for human beings to interpret, understand and remember meanings of instructions that are expressed as binary
numbers. To ease this difficult, opcodes are represented using short abbreviations derived from meanings of opcodes. These
symbols are known as opcode mnemonics. Examples of common mnemonics are:
 MOV is the mnemonic representing the operation move data (copy data).
 ADD is the mnemonic representing the operation add data items.
 ROL is mnemonic representing the operation rotate left bits in a data item.
 JMP is the mnemonic representing the operation jump or branch to.

Assembly Instructions
An assembly instruction is an instruction that is written using an opcode mnemonic and numbers or symbolic names to represent
operands (or locations of operands). The opcode mnemonic and operands are written on the same line. The opcode is separated
from the operands using at least one space. If there are more than one operands, they are separated from each other using
commas. Examples of assembly are:
1. MOV DX,BX means copy contents of register BX into DX.
2. SUB AX,CX means subtract contents of register CX from contents of AX.
3. JMP 5600h means branch and begin executing instructions from location 5600h.

The x86 Assembly Syntax

Different manufacturers may use different assembly language syntaxes. A single manufacturer may also use different assembly
syntaxes for its different products. In this course, the Intel x86 / x64 assembly language syntax shall be explored and used.

Addressing Modes
The ways in which locations of operands are specified in an instruction are known as addressing modes. The following are the
different types of addressing modes.

Register Addressing
The operand is contained in a register. The instruction specifies the register that contains the operand in the operand field. In
the x86 assembly format, the name of the register is specified in the operand field.

Immediate Addressing
The operand is constructed as part of the instruction. An operand constructed as part of an instruction is called an immediate
value. The instruction, thus, specifies the immediate value. In the x86 assembly format, the immediate value or a user-defined
symbol representing the value is specified in the operand field.

Addressing of Operands in Memory

There are a number of ways in which addresses of operands located in memory can be specified by an instruction. These are:
1. Direct addressing – the memory address is constructed as part of the instruction. A memory address constructed as
part of an instruction is called a direct address. The instruction, thus, specifies the direct address.

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 2. Indirect addressing – the memory address of the operand is contained in a pointer register. The instruction specifies
the memory pointer register in the operand field. A memory address held in a pointer register is called an indirect
address.
3. Based addressing – it is a variation of indirect addressing where the memory address is a result of adding a
displacement value to a value contained in a base register, i.e. 𝑚𝑒𝑚𝑜𝑟𝑦 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 = 𝑏𝑎𝑠𝑒 + 𝑑𝑖𝑠𝑝𝑙𝑎𝑐𝑒𝑚𝑒𝑛𝑡. The
instruction specifies the base register in the operand field and the displacement is constructed as part of the instruction.
4. Indexed addressing – the memory address of the operand is a result of adding a displacement value to a value contained
in an index register, i.e. 𝑚𝑒𝑚𝑜𝑟𝑦 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 = 𝑖𝑛𝑑𝑒𝑥 + 𝑑𝑖𝑠𝑝𝑙𝑎𝑐𝑒𝑚𝑒𝑛𝑡. The instruction specifies the index register
in the operand field and the displacement is constructed as part of the instruction.
5. Based index addressing – the memory address of the operand is a result of adding values in base register and index
registers, i.e. 𝑚𝑒𝑚𝑜𝑟𝑦 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 = 𝑏𝑎𝑠𝑒 + 𝑖𝑛𝑑𝑒𝑥. The instruction specifies the base and index registers in the
operand field.
6. Based index with displacement – the memory address of the operand is a result of adding together a base value, an
index value and a displacement value, i.e. 𝑚𝑒𝑚𝑜𝑟𝑦 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 = 𝑏𝑎𝑠𝑒 + 𝑖𝑛𝑑𝑒𝑥. The instruction specifies the base and
index registers in the operand field. The displacement is constructed as part of the instruction.

In the x86 assembly format, memory addresses are indicated by placing the memory address, memory pointer register or an
expression that gives the address in parenthesis in the operand field. The general format of indicating a memory address is
[𝒃𝒂𝒔𝒆 + 𝒊𝒏𝒅𝒆𝒙 + 𝒅𝒊𝒔𝒑𝒍𝒂𝒄𝒆𝒎𝒆𝒏𝒕]. The actual expression could be made up of any one component, a combination of any
two components or all components to give the various memory addressing modes outlined above.

Addressing of Ports
In general, ports can be addressed in two ways. These are:
1. Fixed port addressing – the port address is constructed as part of the instruction. The operand field, thus, contains the
port address. It is the same as direct addressing, i.e., the instruction specifies the port address.
2. Variable port addressing – the port address is contained in a pointer register. The instruction specifies the memory
pointer register in the operand field. It is similar to indirect addressing.

In the x86 format, the port address or port pointer register is specified in the operand field. Only register DX is used as a port
pointer.

Program Branching
A branch instruction specifies the address of the instruction to be branched to either as a direct address or an indirect address.
In the x86 assembly format:
 For direct calls and jumps, the address to be branched to is specified in the operand field.
 For indirect calls and jumps, the pointer register is specified in the operand field.

Implied Addressing
The operand is always in a particular register or is a particular bit such that there is no need for the instruction to specify the
operand location. A register or bit that is always operated on by an opcode is called an implied register/bit. In the x86 format,
an implied operand is not shown in the operand field.

8086 Instruction Examples in x86 Format

Examples of Intel 8086 instructions written using the x86 assembly format are given in Table 3.1.

Table 3.1 Examples of Intel 8086 Instructions in the Intel x86 Assembly Syntax
Instruction mnemonic Addressing Modes
ADC DX,7856h Register; immediate
MOV [BX],25h Indirect; immediate
OR BP,[DI] Indirect; register
CLC Implied addressing (carry flag)
MUL [1547h] Indirect ; implied (registers AX and DX)
CMP CX,[BX+SI+25h] Register; based index with displacement addressing
XCHG BP,[SI+56h] Register; Indexed addressing
ROR [BP+DI] Based index addressing
IN 80h Fixed port addressing
JMP 8090h Direct jump within segment
JMP BX Indirect jump within segment
JMP 4005:4399 Intersegment jump

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Word Equations
Word equations are shorthand descriptions of the meaning of a microprocessor instruction. The equation contains an expression
that represents the operation that is performed when the instruction is executed. If the results are to be stored in some destination,
the destination specifier is added to the left of the expression with an arrow pointing from the expression to the destination of
the results. Table 3.2 shows word equations for the instructions in Table 3.1.

Table 3.1 Examples of Intel 8086 Instructions in the Intel x86 Assembly Syntax
Instruction mnemonic Word Equation Instruction Description
ADC DX,7856h DX ← DX + 7856h Add value 7856h to contents of register DX and store
result in register DX
MOV [BX],25h [BX] ← 25h Load the number 25h into memory location pointed
to by register BX
OR BP,[DI] BP ← BP OR [DI] Logic OR the contents of the register BP with
contents of memory location pointed to by register
DI and store result in register BP
CLC CF ← 0 Clear the carry flag
MUL [1547h] DX:AX ← AX × [1547h] Multiply contents of memory location 1547h with
contents of register AX; store results in 32 bit
register formed as DX:AX
CMP CX,[BX+SI+25h] CX - [BX+SI+25h] Compare contents of register CX to contents of
memory location with address given by BX+SI+25h
XCHG BP,[SI+56h] BP ↔ [SI+56h] Exchange contents of register BP with contents of
memory location with address given by SI+56h
ROR [BP+DI] Rotate right the contents of memory location with
address given by BP+DI
IN 80h AL ← port 80h Input from port 90h.
JMP 8090h IP ← 8090h Branch and begin executing instructions from
memory address 8090h
JMP BX IP ← [BX] Branch and execute instructions starting from the
instruction pointed to register BX

Instruction Set
An instruction set is a set of instructions that a microprocessor can execute. An instruction set normally lists the instructions
using their assembly language representations. The instruction descriptions may be represented using equations or word
descriptions. The corresponding binary representations may also be given.

The 8086 set is given in Appendix A in two tables. In the first table, each instruction entry has the assembly language general
format of the instruction and word equation describing the instruction. The second table has the binary instruction formats that
can be used to work out the equivalent machine codes of instructions.

The 8086 Instruction Set

8086 instructions can be put into a number of groups as outlined next.

Data Transfer Instructions

1. Move – register to register, register to memory, memory to register
2. Immediate load – into register, into memory
3. Exchange – between registers, between memory and register
4. Input from port, output to port
5. Push register to stack, push memory to stack, pop from stack into register, pop from stack into memory.
6. Load segment register with far pointer; load effective address into register.

The operations only alter values in the destination without altering the data in the source.

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Binary Arithmetic Instructions:
1. Addition, subtraction and compare operations – between two GPRs, between a GPR and memory, between a GPR and
an immediate value, between memory and an immediate. Operation can be on signed or unsigned numbers using same
instructions; result is stored in either a GPR or memory; compare operation performs subtraction operation without
storing results.
2. Multiplication and division – between accumulator and a GPR, between accumulator and memory, between
accumulator and immediate value. Operation can be on signed or unsigned numbers using different instructions; result
is stored in AX and DX.
3. Increment, decrement and negate operations – value GPR, value in memory.
4. Conversion between precisions – from byte to word, from word to double word.

Decimal Arithmetic on accumulator

1. Decimal adjust after addition
2. Decimal adjust after subtraction
3. ASCII adjust after addition
4. ASCII adjust after subtraction
5. ASCII adjust after multiplication
6. ASCII adjust before division.

The operand can only be on the accumulator.

Logic Instructions:
1. AND, OR, XOR and TEST operations – between two GPRs, between a GPR and memory, between a GPR and an
immediate value, between memory and an immediate. Result is stored in either a GPR or memory; TEST operation
performs AND operation without storing results.
2. NOT operation – on a GPR, on memory.

Shift and Rotate Instructions

1. Shift arithmetic right
2. Shift logical right
3. Shift logical left / Shift arithmetic left
4. Rotate right
5. Rotate left
6. Rotate right through carry
7. Rotate left through carry

The operands can be in a register or in memory.

String Instructions
1. String move
2. String load
3. String store
4. String compare
5. String scan
6. Repeat prefixes to above instructions

The instructions operate on values pointed to by index registers. The count value for the number of times that the instruction is
executed is held in CX. After a string operation, the pointers and the counter are updated to point to the next data item.

Control Transfer Instructions

1. Unconditional jumps – within segment, intersegment
2. Conditional jumps – relative to current origin
3. Calls – within segment, intersegment
4. Software interrupts
5. Returns – from subroutine within segment, from subroutine intersegment, from interrupt

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Flag Control Instructions
1. Set a flag bit, clear a flag bit, complement a flag bit (apply to select flags)
2. Push and pop flags from the stack
3. Store and load flags to/from register AH.

Processor Control
1. Halt – pause execution until a reset, INTR or NMI.
2. Wait – wait until BUSY input to microprocessor goes inactive.
3. Escape – to processor extension/coprocessor.

Instruction prefixes
Lock and segment override prefixes.

8086 Instruction Encoding

Intel 8086 instructions are 1 to 6 bytes long. The first byte is the opcode byte; it defines the opcode, the width of data and the
destination of the results. The second byte is the addressing mode byte; it defines the location of the operands. Combined, the
opcode and the addressing mode bytes give up to 6 bit fields. Figure 3.1 shows how these bit fields are used.

Figure 3.1.

The fields in the opcode and addressing mode bytes are used as follows:
• The opcode field specifies the operation to be carried out.
• The reg field is used to specify a register that holds one of the operands. 8 different registers can be specified using
this field. In some instructions reg field is used as an extension to the opcode field.
• The r/m field is used to specify a register or memory location that holds one of the operands.
• The mod field is used to specify the addressing mode for the r/m field. Combined with the r/m field, the two fields
give 32 different ways of specifying the location of an operand. 8 of them specify 8 different registers. The other 24
are 24 different ways of specifying addresses of operands in memory.
• The d field is the direction bit; it specifies the destination of the result as either specified by the reg or r/m field.
• The w field is the data width field; it specifies the operand size as either 8 bits or 16 bits.

There are some variations to the opcode structure:

• In some instructions d may be used to: (i) indicate whether or not to sign extend an immediate operand to match the
register width; or (ii) indicate whether a rotate or shift operation is carried out once or a number of times – if the
number of times is more than one, it is stored in register CL.
• In some instructions w is used to indicate when a repeat operation occurs – i.e. if the zero flag is set or if it is cleared.
• In some instructions opcode and an operand field are encoded in the first byte.
• In some instructions, the whole first byte represents the opcode or part of the opcode.

Immediate, Displacement (or address) Values

Immediate, address and displacement values are encoded in up to four bytes that follow the opcode byte. The displacement (1
or 2 bytes) follows the addressing mode byte. The immediate data (1 or 2 bytes) follows the displacement byte(s); in the case
a displacement value is not required, the immediate data follows the addressing mode byte. 16-bit immediate and displacement
values are stored in memory with the higher byte occupying higher address, i.e. in reverse order. This is known as a little
endian style. For example, the value 8570h is stored in memory as 7085h. Please note that the opcode and addressing mode
bytes are stored opcode first, i.e., in their natural sequence. Figure 3.2 shows the general structure of an 8086 instruction.

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 View (a)

View (b)
Figure 3.2. The 8086 Instruction structures.

Table 3.3 shows the binary construction of some Intel 8086 instructions as examples. Addressing modes are also given. The
instructions are usually expressed using their hexadecimal equivalents as given in the last column.

Table 3.2
Assembly Instruction Binary code showing bit fields Hex code
MOV DX,BX 10001011 11010011 8BD3h
Register addressing, register addressing
SBI [DI],SI 00101001 00101100 292Ch
Register addressing, indirect addressing
MOV [4508h],SP 10001001 00110110 000010000 01000101 89360845h
Register addressing, direct addressing
ADD CX,5600h 10000001 11000001 00000000 01010110 81C10056h
Register addressing, immediate addressing
DIV SI 11110111 11101110 F7DCh
Register addressing, implied addressing
STC 11111001 F9h
Implied addressing
CMP AX,(BP + DI) 00111001 00000011 3903h
Register addressing, based index addressing
JMP 8090h 11000011 10010000 10000000 C99080h
Direct addressing
Key: red – opcode green – operand 1 (destination of result) purple – operand 2 (source)
blue or blue – operand width / destination of results / addressing mode specifier
orange – immediate value or direct address

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Instruction Prefixes
Instruction prefixes are specific numbers that are added as prefixes to instructions to bring about some way of executing the
instruction. In assembly language, there is at least one space between the prefix mnemonic and the opcode mnemonic. For
example, to repeat the string move operation, the prefix REP is added to produce the assembly instruction REP MOVSB. In
machine, code, the prefix code is stored before the opcode byte.

8086 instruction prefixes are divided into two groups as follows:

1. Group 1 – lock and repeat prefixes.
a) F0H – LOCK prefix – prevents execution of an instruction from being interrupted.
b) F2H – REPNE/REPNZ – causes an instruction to be repeatedly executed as long as the zero flag is not set
and the counter is not zero. It applies only to chain instructions.
c) F3H – REP or REPE/REPZ – causes an instruction to be repeatedly executed as long as the zero flag is set
and the counter is not zero. It applies only to chain instructions.

2. Group 2 – Segment override prefixes are used to override the default segment register:
a) 2EH—CS segment override prefix – makes instruction use code segment instead of default segment.
b) 36H—SS segment override prefix – makes instruction use stack segment instead of default segment.
c) 3EH—DS segment override prefix – makes instruction use data segment instead of default segment.
d) 26H—ES segment override prefix – makes instruction use extra data segment instead of default segment.

Review Questions
1. What is an opcode? What is an operand? What is the role of each of them?
2. What are mnemonics? How do they make programming easier than when using machine code?
3. What is an addressing mode? Outline the various addressing modes? Which ones are used in the 8086?
4. What do you understand by the term assembly instruction? Describe the basic structure of an assembly instruction.
5. Describe the roles of the various fields in an 8086 instruction.
6. What are instruction prefixes? Outline effects brought about by the various 8086 instruction prefixes.

Chapter 3 Tutorial Questions

1. Name the addressing mode used for each operand in the following instructions.
a) MOV CS,BP
b) XCHG DX,[SI]
c) DEC [9600h]
d) OUT [DX],AL
e) ADD [DI+56h],AX
f) SUB DI, [BX+23h]
g) NEG [BP+DI+72H]
h) IMUL [BX+SI]
i) SAL BL
j) ROR [DI+44h]
k) TEST CL,DH
l) XOR AH,78h
m) STD
n) LDS DX,[500h]
o) CALL 5148H

2. It is given that AX contains 8000h, BX contains 7050h, CX contains 500h, DX contains 1200h, SI contains
900h, DI contains 450h, BP contains 6000h and SP contains 5800h before execution of each instruction.
For each instruction in question 1 that involves a memory location, what is the address of the location?

3. Describe the following instructions fully. Meanings of instructions are given as word equations.
a) MOV SP,DS SP ← DS

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 b) XCHG [DI+25h],AX [DI+25h] ↔ AX
c) IN AL,[08h] AL ← port[08h]
d) ADC DL,[SI+650h] DL ← DL + [SI+650h] + CF
e) INC [BX+25h] [BX+25h] ← [BX+25h] + 1
f) SUB [2300h],SI [2300h] ← [2300h] - SI
g) NOT [BP+SI] [BP+SI] ← not [BP+SI]
h) DIV [BP+DI+44h] AX ← DX:AX / [BP+DI+44h]; DX ← DX:AX % [BP+DI+44h]
i) SHR CX Shift bits right
j) ROL [5000h] Rotate bits left
k) CMP DH,50h DH – 50h
l) AND [6580h],SP [6580h] ← [6580h] • SP
m) CMC CF ← not CF
n) JMP [BX+67h] IP ← [BX + 67h]
o) JNZ 45h if ZF=0 then IP ← IP + 45h – 2

4. What are the contents of the indicated memory locations and registers after execution of the instructions
given Table Q4? Initial contents of some of the locations are given. The instructions execute
independently.
Table Q4
Instruction Initial contents of some locations (before Locations and
execution) registers whose
contents are required
a) MOV AH,CL AH=22H; CL=47H AH,CL
b) XCHG [7008],DL DL=9BH; [7008H]=61H DL, [7008]
c) IN AL,[DX] Port [DX]=5EH; AL=D6H AX, port [DX]
d) OUT [10h],AX AX=F56BH, port [10h]=2085h AX, port [10h]
e) ADC CX,48h CX=69H, CF = 1 CX, CF
f) SUB [DI + 5h],SI DI=5400H, SI=E3H, [5405H]=AAAAh, CF=1, DI, SI, [5405h], ZF, CF
ZF=0
g) INC [BP + DI + 14h] BP=A172H, DI=08B2H, [AA38]=57h BP, DI, [AA38]
h) NEG DX DX=C200 DX
i) OR [BX],SP BX=4144H, SP = 2159h, [4144] = 0844h BX, SP, [4144]
j) CMP BH,[SI] BH=55H; SI = 90h; [90h]=46, CF=0, ZF=1 BH, SI, [90h], CF, ZF
k) MUL SP SP=478h; AX = 1598h, DX = 745h SP, AX, DX
l) CBW AL=C7h AL, AH, AX
m) DAA
n) SHR DL,1 DL=97H, CF=0 DL, CF
o) ROL [BP + SI] BP=B2H; SI=2400h, [24B2h]=E5h BP, SI, [24B2h], CF
p) RCR [BX + 14h] BX=2405h, [2419h]=E5h BX, [2419h] , CF
q) SAR [BX + SI + 7h] BX=E6H; SI=2400h, [24EDh]=E5h BX, SI, [24EDh] , CF
r) JMP 3348H IP = 9008H IP
s) JNP 88H IP=4006H; PF=0 IP
t) JZ 90H IP=9009H; ZF=0 IP
u) JCXZ CX=47H CX, IP
v) CMC
w) XLAT
x) LES BP,[SI + 75h] BP=560Ah; SI=6420h; [6495]=640h; ES=5Fh BP; SI; [6495]; ES
y) LEA CX,[BP + 67h] CX=520Ah; BP=6420h; [6487]=645h CX; BP; [6487]

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 5. Do a step by step filling of contents of registers, memory locations and flags indicated in the following
tables. The instructions are executed as a sequence one after the other.

Table 5a
Instruction AL CL BX DI (1890h) (1891h) (1892h) Cy
Initial contents 67 075D 1892 6478 53 40 7D 1
MOV BX,1891h
MOV AL,[1890h]
ADC AL,CL
CMP AL,[BX]
AND AL,55h
NOT AL
MOV [DI],AL

Table 5b
Port 01h has pins starting from MS pin at 0V, 0V, 0V, 0V, 0V, 0V, 0V, 0V, 5V, 5V, 0V, 0V, 5V, 5V, 5V, 0V respectively.
CL contains 2 at the start of the program.
Instruction AX DX BX DI (05D0h) (8000h) (85D0h) Cy
Initial contents 43h 22h 05D0h 1567h 8Ah C9h 40 1
MOV DI,8000h
ADC AX,DX
IN AX,01h
MOV [DI],AX
STC
ROL AX,CL
MOV [BX],AX
XOR [BX+DI],AX
XCHG BX,AX
MUL 55h
NEG [8000h]
CMC

6. Write a single 8086 assembly language instruction to do each of the following:

a) Load value in memory location 0901H into register AX
b) Subtract contents of BL from contents of CH.
c) Add contents of DI to contents of memory location pointed to by BX including the input carry (and
store result in memory).
d) Exclusive OR the contents of the register DX with the immediate value 243 (decimal).
e) Rotate left through the carry flag the contents of memory at an offset of 78 to the address pointed
to by SI.
f) Test if number in memory location at an offset of 98 to the address pointed to by BP is greater or
smaller than the number in register SP
g) Load the hexadecimal numbers 5F and 87 into registers DH and DL respectively
h) Multiply the value in AX by the value pointed to by SI.
i) Clear the direction flag
j) Load the effective address for based index with displacement addressing into register BX. Use an
index and a base register of your choice.
k) Load the far pointer at memory location 5900h into registers DS and BP.
l) Jump program execution to memory location 5D12H
m) Jump program execution to an offset of 7DH from current position if the last operation produced
a negative result.

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7. Write an 8086 assembly instruction or a sequence of 8086 assembly instructions to carry out the following:
a) Read a number from port pointed to by DX, add the number 15H to the read value and write the
result to port pointed to by 09H.
b) Move contents of memory location 0400h to memory location 0600h.
c) Read the value on input port at address 0Ch into register CX.
d) Add numbers in memory locations 9070H and 9071H and put the results in memory location
9072H.
e) Divide the number in memory location pointed to by SI by the number stored in register DI; store
result in accumulator and DX.
f) Mask the lower nibble of the value in register AH, i.e., set higher bits to zeros.
g) Convert a lower case character (assume the character is known to be a lower case letter) in
memory location 0800h to an upper case and store it back in the same location.
h) Register AH contains a right justified BCD code. Write a program to left justify the BCD code in AH
with zeros in the lower nibble position.
i) Use a memory pointer DI to store the value 0ADh in memory location A000h.
j) Write the ASCII code corresponding to a BCD code stored in register BL to port 08h.
k) Pack two unpacked BCD codes stored in AL and AH into a byte stored in AL. The lower nibble of
AL must contain the lower BCD code. (Hint, first left justify the more significant nibble).

8. Work out the hexadecimal representations of the following instructions:

a) MOV AH,CL
b) XCHG [BX],DL
c) ADC [8056h],48h
d) SUB [DI + 5h],SI
e) INC [BP + DI + 14h]
f) NEG DX
g) TEST BH,[SI]
h) MUL SP
i) SHR DL,1
j) OUT 10h,AX
k) IN AL,DX
l) CMC
m) JMP 8596h

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