EASTERN VISAYAS STATE UNIVERSITY
SCHOOL OF ENGINEERING ELECTRONICS
ENGINEERING DEPARTMENT
NAME: Silvano, Jomil L. COURSE & YEAR: BSEE 3C
Gallano, Jan Nino
Tala, Francis Anthony
Hollanda, Allan Jr.
Llosa, Franz Joseph
Padual, Aldwin
INSTRUCTOR: Engr. Anni Lou Bordios 1ST Semester SY 2025-2026
EE 333 LABORATORY ACTIVITY
ACTIVITY 3: UNIVERSAL LOGIC GATES
Overview
This laboratory activity aims to demonstrate the concept of universal logic gates and their applications in digital
circuit design. Universal gates, namely NAND and NOR, are fundamental because any Boolean function can be
implemented using only one of these gate types. Through a series of verification and design tasks, students will
construct basic logic operations using NAND and NOR gates, and extend their understanding by designing a
simple alarm circuit. The activity reinforces logical reasoning, circuit analysis, and practical implementation of
combinational logic systems.
Objectives:
After completing this experiment, students should be able to:
1. Verify the logical operations and truth tables of the universal logic gates, specifically the NAND and NOR
gates.
2. Demonstrate that NAND and NOR gates can be used to implement all basic logic functions, establishing
their property as universal gates.
3. Design and construct an alarm circuit that activates when at least two switches are ON, using NAND gates
as the sole logic elements.
Pre-lab Preparation
Students must read the following before performing the lab:
TTL logic family basics and pinouts for 74xx series.
Symbols and truth tables for NAND and NOR gates.
Safety rules for using breadboards, power supplies, and measurement instruments.
Safety and Good Laboratory Practice
Use a regulated 5 V DC supply only. Do not exceed 5.5 V.
Always switch power OFF when wiring or re-wiring circuits.
Connect ground (0 V) first when connecting instruments.
Use current-limiting resistors (330–1kΩ) with LEDs.
Avoid short circuits across power rails.
Report any damaged ICs or wiring incidents to the instructor immediately.
Materials and Equipment
1 Regulated DC power supply (5V) 1 7402/74LS02 NOR gate
1 Breadboard 3 LEDs
Connecting wires 3 Resistors (330 – 470
1 7400/74LS00 NAND gate ohms)
Principles
The NAND and NOR gates are considered universal gates because they can be used to obtain the function of the
other logic gates by using the principle of negation.
A NAND gate performs the logical AND operation on its inputs and then inverts the result. Its standard symbol
resembles that of an AND gate with a small bubble at the output, indicating inversion. The logical operation is
expressed as:
𝑌=𝐴∙𝐵
Since the NAND configuration naturally aligns with the characteristics of transistor circuits, particularly those
using common-emitter stages, NAND gates are often simpler to design and more widely used in integrated
circuits than non-inverting gates such as the AND gate.
The standard symbol for a NAND gate is shown in Figure 1.
Figure 1. NAND Gate
Similarly, a NOR gate performs the logical OR operation followed by inversion. Its symbol is identical to that of
an OR gate with an inversion bubble at the output, representing the logical operation:
𝑌=𝐴+𝐵
Part 1 The Universal Logic Gates Part
1a. Testing NAND Gate Procedures:
1. With power OFF, place the 7400 NAND gate on the breadboard and wire power pins.
2. Connect the given circuit.
Label in the figure the pins
used for inputs and outputs.
3. Connect the outputs X and Y to LEDs.
4. Test for the logic outputs (X and Y).
5. Record the status of the LED indicators X and Y on Truth Table 1.
Table 1. NAND Gate
A B C X Y
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 1
1 1 1 0 1
Part 1b. Testing NOR Gate Procedures:
1. With power OFF, place the 7402 NOR gate on the breadboard and wire power pins.
2. Connect the given circuit.
Label in the figure the pins
used for inputs and outputs.
3. Connect the outputs X and Y to LEDs.
4. Test for the logic output (X and Y).
5. Record the status of the LED indicators X and Y on Truth Table 2.
Table 2. NOR Gate
A B C X Y
0 0 0 1 0
0 0 1 1 0
0 1 0 0 1
0 1 1 0 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 0 0
Questions:
1. What is the logic operation performed by a NAND gate?
A logical AND operation and an inversion (NOT) are carried out by a NAND gate. Only when every input
is high (logic 1) does it generate a low output (logic 0); otherwise, the output is high (logic 1).
2. Based on your truth table, when does the output of a NAND gate become logic 0?
In particular, when both inputs (A and B) are logic 1, the NAND gate's output becomes logic 0.
3. What is the logic operation performed by a NOR gate?
A logical OR operation and an inversion are carried out by a NOR gate. It functions as an "active
low" gate, meaning that only when all inputs are low is the output high.
4. When does the output of a NOR gate become logic 1?
Only when both inputs (A and B) are logic 0 does a NOR gate's output become logic 1.
5. Compare the behavior of the NAND and NOR gates in terms of inversion. How are they similar?
Based on the negation principle, both gates are universal gates. They are comparable in that they both flip
the outcome of a common logic operation (OR for NOR, AND for NAND). By connecting their inputs,
both can also be set up as a typical NOT gate (inverter).
6. From your experimental results, did the actual behavior of the NAND and NOR gates match their
theoretical truth tables? Explain briefly.
Indeed, the behavior is consistent with the theoretical truth tables. With the exception of when both inputs
were high, the NAND gate's output was always high (1). With the exception of when both inputs were low, the
NOR gate output was always low (0).
Part 2. Application: Alarm Circuit Using NAND Gates
Problem Statement
An alarm circuit is composed of three switches, namely Switch A, Switch B, and Switch C. The alarm circuit has
an output indicator that turns ON a LED when at least two of the switches are ON. If an ON state represents logic
1, determine how many 2-input NAND gates are needed to implement the circuit.
Truth Table:
Switch A Switch B Switch C Output Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Boolean Expression: Y=𝐴̅𝐵𝐶 + A𝐵̅ 𝐶 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶 ------- Y=AB+BC+AC
Implementation using NAND Gates: Y= ̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶
̿̿̿̿ ∙ 𝐵𝐶
Y=𝐴𝐵 ̿̿̿̿ ∙ 𝐴𝐶
̿̿̿̿
Logic Diagram:
Verification (attach photos for every possible output show in truth table):
Questions:
1. What is the required logical condition for the LED alarm to turn ON in the given circuit?
The required condition is that at least two switches must be in the ON state (Logic 1) simultaneously.
2. Why is it possible to implement the alarm circuit using only NAND gates?
It is possible because the NAND gate is a universal gate. Any Boolean function (including AND, OR, and NOT)
can be implemented using only NAND gates.
3. How many 3-input NAND gates are required to realize the circuit, and how are they used?
Strictly speaking, one 3-input NAND gate is required for the final stage of the simplified design. It is used to
combine the outputs of the three previous 2-input NAND gates.
4. How did you obtain a 3-input NAND gate given that you only have a 2-input NAND gate?
Since the materials list only includes 7400/74LS00 (Quad 2-Input NAND), a 3-input NAND function must be
constructed using 2-input NAND gates. To strictly synthesize a 3-input NAND using 2-input gates.
5. What advantage does the use of NAND gates o er in implementing combinational logic circuits such as
the alarm system?
Using NAND gates offers several advantages,
simplicity, cost, and IC design.
Conclusion
We successfully investigated the idea and use of universal logic gates in this lab exercise. By confirming the
functionality of NAND and NOR gates and showcasing their adaptability in digital circuit design, the experiment
accomplished its main goals.
The truth tables for the 7400 NAND and 7402 NOR gates were first confirmed. The experimental findings
verified that the NOR gate only produces a logic 1 when all inputs are low, and the NAND gate only produces a
logic 0 when all inputs are high. Their behavior as inverted AND and OR functions, respectively, was confirmed
by these results, which were in perfect agreement with the theoretical logic operations.
Second, the exercise illustrated these gates' ubiquitous feature. We demonstrated that complicated combinational
logic, notably a majority vote function, can be implemented without the need for separate AND or OR chips by
building a functional alarm circuit using only NAND gates. This reaffirmed the idea that a single kind of
universal gate can be used to create any Boolean function, simplifying circuit design and lowering the number of
components needed.
All things considered, this experiment demonstrated the effectiveness and significance of NAND and NOR gates
in digital electronics. They are essential components of contemporary integrated circuits and logic architecture
because they can mimic the operation of any other logic gate.
EASTERN VISAYAS STATE
UNIVERSITY SCHOOL OF
ENGINEERING
ELECTRONICS ENGINEERING
DEPARTMENT
NAME: Jan Nino S. Gallano COURSE C YEAR: BSEE 3-C
Jomil L. Silvano
Francis Anthony Tala
Allan M. Holanda Jr.
Aldwin Padual
Franz Joseph A. Llosa
INSTRUCTOR: Engr. Anni Lou Bordios 1ST Semester SY 2025-2026
EE 333 LABORATORY ACTIVITY
ACTIVITY 4: ADDERS
Overview
Binary addition is one of the most fundamental operations in digital systems, forming the basis of arithmetic logic units
(ALUs), counters, and a wide range of computational architectures. This experiment introduces the design and
implementation of full adders—combinational circuits capable of adding three input bits—and explores how these
building blocks can be cascaded to construct multi-bit binary adders. Students will verify full adder functionality using
discrete logic gates, analyze truth table outputs, derive Boolean expressions, and extend their understanding to create
and test a four-bit ripple-carry adder.
Objectives:
After completing this experiment, students should be able to:
1. Implement and verify the logic-gate–level design of a full adder by constructing the circuit and testing its
SUM and CARRY outputs.
2. Derive and simplify the Boolean expressions for the SUM and CARRY outputs based on the completed truth
table.
3. Design, construct, and test a four-bit ripple-carry adder using cascaded full adders and validate its
performance through sample binary addition cases.
Pre-lab Preparation
Students must read the following before performing the lab:
TTL logic family basics and pinouts for 7408, 7432, C 7486 series.
Symbols and truth tables for AND, OR and XOR gates.
Safety rules for using breadboards, power supplies, and measurement instruments.
Safety and Good Laboratory Practice
Use a regulated 5 V DC supply only. Do not exceed 5.5 V.
Always switch power OFF when wiring or re‑wiring circuits.
Connect ground (0 V) first when connecting instruments. Use
current‑limiting resistors (330–1kΩ) with LEDs.
Avoid short circuits across power rails.
Report any damaged ICs or wiring incidents to the instructor immediately.
Materials and Equipment
1 Regulated DC power supply 3 7408 AND Gates
(5V) 1 Breadboard 2 7432 OR Gates
Connecting wires 4 LEDs
2 7486 XOR 4 Resistors (330 – 470 ohms)
Gates
Procedures:
A. Construction and Verification of the Full Adder
1. Assemble the full adder circuit as shown in the provided logic diagram. Ensure proper orientation and pin
connections of the 7486 XOR, 7408 AND, and 7432 OR ICs.
2. Connect the circuit to the regulated power supply and verify that all logic ICs receive correct Vcc and
ground connections.
3. Apply all eight input combinations of 𝐴, 𝐵, and 𝐶𝑖𝑛 (0–7 in binary).
4. For each input set, use the logic probe (or LED state) to observe the SUM and CARRY outputs.
5. Record the results systematically in the truth table provided, ensuring accuracy and completeness.
Figure 1. Logic Diagram
Table 1. Full Adder
A B C Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
B. Derivation of Boolean Expressions
6. Based on the completed truth table, derive the Boolean expressions for SUM and CARRY.
Sum =l
Carry =
7. Simplify the expressions using Boolean algebra or Karnaugh maps, and write the final expressions in the
spaces provided.
C. Design of a Four-Bit Ripple-Carry Adder
8. Using the conceptual understanding of cascading full adders, draw the circuit diagram of a four-bit ripple-
carry adder.
9. Ensure that the CARRY OUT of each full adder stage connects to the CARRY IN of the next higher-
order stage.
D. Construction and Testing of the Four-Bit Adder
10. Construct the four-bit adder circuit on a breadboard following your design.
11. Apply the binary input pairs specified in the activity below.
12. For each case, observe the SUM outputs and final carry-out using the logic probe.
13. Write the computed results clearly and verify whether they match the expected binary sums.
E. Block Diagram Representation
Generally, half adders and full adders are represented by block diagrams as shown.
14. Using the standard block symbols for half adders and full adders, redraw the four-bit adder using block-
level abstraction.
15. Ensure that carries are properly cascaded between blocks to reflect the logical structure of a ripple-carry
adder.
Questions:
1. Explain the functional difference between a half adder and a full adder. Why is the full adder necessary
when designing multi-bit adders
Half Adder (HA): Adds two single-bit binary numbers (A and B) and provides two outputs: Sum (S) and
Carry ©. It has no input for a carry from a previous stage.
Full Adder (FA): Adds three single-bit binary numbers: two main inputs (A and B) and a Carry-in
(C_{in}) from a previous lower-order bit.
2. Explain why XOR gates are fundamental in generating the SUM output of full adders.
Boolean Expressions Match: Yes—derived expressions from truth tables align with standard forms: S =A
+ B + 𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑁 + 𝐵𝐶𝑁
3. If the circuit produced an incorrect SUM or CARRY output, identify possible sources of error.
XOR (Exclusive OR) gates are fundamental for the Sum output because they act as “difference detectors”
or “odd parity generators.”In binary, the sum bit is 1 only if an odd number of inputs are 1.
If you have two 1s, the sum should be 0 (since 1+1=10). The XOR gate naturally outputs 0 for (1,1) and (0,0),
and 1 for (0,1) or (1,0), which perfectly mimics the behavior of binary addition without a carry.
4. If the circuit produced an incorrect SUM or CARRY output, identify possible sources of error.
Possible Errors:
Faulty components, incorrect wiring, design mistakes (e.g., wrong Boolean logic), timing delays (ripple
carry glitches), or incorrect initial carry-in..
Conclusion
Half adders enable basic 2-bit addition, while full adders address the critical need for carry propagation in multi-
bit systems—forming the core of ripple-carry adders. Their Boolean expressions are well-defined and rely on
XOR gates for sum logic. Implementation errors can stem from hardware, design, or timing issues, highlighting
the importance of precise circuit planning and testing in digital arithmetic desig
EASTERN VISAYAS STATE UNIVERSITY
SCHOOL OF ENGINEERING
ELECTRONICS ENGINEERING
DEPARTMENT
NAME: Silvano, Jomil L. COURSE & YEAR: BSEE 3C
Gallano, Jan Nino
Tala, Francis Anthony
Hollanda, Allan Jr.
Llosa, Franz Joseph
Padual, Aldwin
INSTRUCTOR: Engr. Anni Lou Bordios 1ST Semester SY 2025-2026
EE 333 LABORATORY ACTIVITY
ACTIVITY 5: SEVEN SEGMENT DECODER
Overview
Seven-segment displays serve as fundamental output devices in digital electronics, providing a simple and
effective means of representing numerical information. A seven-segment decoder interprets a binary input—
typically a 4-bit code—and activates specific LED segments to display digits from 0 to 9. This experiment
guides students through the process of analyzing the behavior of each display segment, deriving the
necessary Boolean expressions, and implementing the decoder using basic logic gates. By constructing and
testing the circuit, students gain practical experience in combinational logic design and develop a deeper
understanding of how digital systems generate visual numeric outputs.
Objectives:
After completing this experiment, students should be able to:
1. Construct and analyze the complete truth table for a seven-segment decoder corresponding to
decimal inputs 0–9.
2. Derive, simplify, and implement the Boolean expressions for each display segment using logic
gates.
3. Build and test a functional seven-segment decoder circuit that correctly displays digits 0–9 using
discrete LED segments.
Pre-lab Preparation
Students must read the following before performing the lab:
TTL logic family basics and pinouts for 74xx series.
Symbols and truth tables for NOT, AND, OR gates.
Safety rules for using breadboards, power supplies, and measurement instruments.
Safety and Good Laboratory Practice
Use a regulated 5 V DC supply only. Do not exceed 5.5 V.
Always switch power OFF when wiring or re wiring circuits.
Connect ground (0 V) first when connecting -instruments.
Avoid short -circuits across power rails. Use
current limiting resistors (330–1kΩ) with LEDs.
Report any damaged ICs or wiring incidents to the instructor immediately.
Materials and Equipment 5 7408 AND gate
1 Regulated DC power supply 5 7432 OR gate
(5V) 1 Breadboard 7 LEDs
Connecting wires 7 Resistors (330 – 470 ohms)
1 7404 NOT gate
Principles
A seven segment decoder is used as a display decoder. Each segment in the display is actually a LED
component. These LEDs are activated in a pattern so as to represent the digits 0 to 9 and the characters A to F.
The seven segment decoder determines which LED in the seven segment display needs to be activated based on a
given input combination.
Procedures:
Develop the Seven-Segment Truth Table
a. Identify the four input bits (M, N, O, P) that represent decimal digits 0–9 in binary form. b. For each
input combination, determine which segments (a–g) must illuminate to display the correct digit.
c. Complete the truth table by marking each segment as ON or OFF for all required input values.
M N O P a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 0 1
Derive and Simplify Boolean expressions
a. For each segment output (a through g), list the minterms corresponding to ON states from the truth
table.
b. Simplify the expressions using Boolean algebra or Karnaugh maps to obtain minimal logical forms.
c. Write the final simplified expressions clearly in the space provided.
Segment a: A= M+O+NP+𝑁 ̅ 𝑃̅
Segment b: B= 𝑁̅ + 𝑂̅𝑃̅ + 𝑂𝑃
Segment c: C= N+𝑂̅+P
Segment d: D= M+ ̅̅̅̅
𝑁𝑃 +𝑁̅ O + O𝑃̅ + N𝑂̅P
̅̅̅̅+ O𝑃̅
Segment e: E= 𝑁𝑃
Segment f: F= M+ ̅̅̅̅
𝑂𝑃+N𝑂̅+N𝑃̅
Segment g: G= M+N𝑂̅+𝑁 ̅ 𝑂+ O𝑃̅
3. Prepare the Logic Diagram
a. Using the simplified expressions, draw the corresponding gate-level implementation using AND, OR,
and NOT gates.
b. Ensure that each logic block is clearly labeled and connected to its respective segment output.
4. Construct the Seven-Segment Decoder Circuit
a. Place the required ICs (7408, 7432, 7404) on the breadboard and connect them to the regulated power
supply with proper grounding.
b. b. Wire the input variables M, N, O, and P to switches or jumper settings that allow selection of binary
inputs 0–9.
c. c. Connect each logic output to its respective LED segment, observing proper LED polarity and using
current-limiting resistors if necessary.
5. Test and Verify the Display Output
a. Apply input combinations for decimal digits 0–9 sequentially.
b. Observe the LED illumination pattern for each input and verify that the correct numeral appears.
c. Document any inconsistencies and troubleshoot wiring, logic connections, or expression
simplifications as needed.
@ (M, N, O, P) – 0000
@ (M, N, O, P) – 0001
@ (M, N, O, P) – 0010
@ (M, N, O, P) – 0011
@ (M, N, O, P) – 0100
@ (M, N, O, P) – 0101
@(M, N, O, P) – 0110
@(M, N, O, P) – 0111
@(M, N, O, P) – 1000
@(M, N, O, P) – 1001
Questions:
1. What is the primary function of a seven-segment decoder in a digital system?
A seven-segment decoder's main job is to transform binary coded data more precisely, a 4-bit binary
code that represents a decimal number into a particular pattern of active signals. The seven distinct
display segments are driven by these signals to visually represent human-readable numerical digits
(0–9).
2. Why is it necessary to derive individual Boolean expressions for each segment (a–g)?
Each segment, labeled a through g, works independently to create different shapes. Segment 'a', for
instance, lights up for the digits 0, 2, and 3, among others, but stays dark for 1 and 4. Since the
activation pattern for each segment is unique relative to the input binary code, a separate Boolean
equation must be derived for each segment to define exactly when it should be ON or OFF
3. In your truth table, which input combinations activate the most segments, and why?
The greatest number of segments are activated by the input combination for the decimal digit 8
(1000). All seven segments (a, b, c, d, e, f, and g) must be illuminated in order for the number '8' to
be displayed. As a result, each segment output has a logic HIGH due to the logic state for input
'1000'.
4. How does Boolean simplification (e.g., using Karnaugh maps) improve the design of a seven
segment decoder?
The complexity of the logic expressions is decreased by Boolean simplification. We reduce the
number of literals and terms by grouping minterms (1s) and applying "Don't Care" conditions (for
inputs 10–15). Because fewer physical logic gates (AND, OR, and NOT) and chips are needed to
construct the circuit, it is more effective, less expensive, and simpler to wire on a breadboard.
5. Explain how the seven-segment decoder can be integrated into larger digital systems. 6.
Based on your implementation, how do inverter gates (7404) contribute to segment control? Binary
processing is used in larger systems like digital clocks, calculators, and counters. The interface
between this internal binary processing and the human user is a seven-segment decoder. It converts the
binary output from a microcontroller or counter into an understandable visual readout.
Discussion of Results
The BCD-to-7-segment decoder circuit’s development went through several key design stages that were based
on basic electronic principles. The very first design chose the right physical “8” shape that a seven-segment
display would show with separate LEDs. This design outlined the segments a to g that are required for digit
indication. The 74LS47D got chosen as the major logic part. This IC is a BCD-to-7-segment decoder that
transforms the pretty complicated Boolean logic needed to convert a 4-bit binary input into the specific segment
patterns for numbers 0–9. The circuit was described as a Common Anode arrangement. This means the positive
terminals (Anodes) of the LEDs are connected to the +5.0V power supply while the decoder “sinks” the current
through its output pins to Ground in order to turn on the selected segments. During the design process, a “High-
to-High” conflict (short circuit) was discovered where the IC outputs were connected to 5V. Fixing this permits
the IC to operate correctly as a switch for the LEDs.
Conclusion
This laboratory/ experiment shows the design and logical mapping of a 7-segment decoder circuit. The circuit
converts the 4-bit binary signals into decimal digits that are easy to read with the use of a 74LS47D IC in a
Common Anode structure. Resistors are necessary to ensure that the LEDs last longer and the IC does not get
damaged. In a Common Anode setup, the decoder has to be the only way for the LEDs to reach ground;
otherwise, connecting IC outputs to +5V will cause the circuit to not work. With the wiring currently in your last
file, the hardware is already set in a way to do BCD conversion provided that the short at the IC outputs for the
power rail is removed.
DOCUMENTATION: