High Full Well Capacity and Low Noise Characteristics in 0.
6 µm Pixels via Buried
Sublocal Connections in a 2-Layer Transistor Pixel Stacked CMOS Image Sensor
Masataka Sugimoto, Tatsuya Okawa, Kanta Suzuki, Tomoharu Ogita, Keiji Nishida,
Katsunori Hiramatsu, Tomoyuki Hirano, Yoshiaki Kikuchi, †Yuji Nishimura, †Kohei Takeuchi,
†Daisuke Yoneyama, †Toru Nagaki, †Noriteru Yamada, †Hiroyuki Kawashima, and Yoshiaki Kitano
Sony Semiconductor Solutions; †Sony Semiconductor Manufacturing
4-14-1 Asahi-cho, Atsugi, Kanagawa, Japan
E-mail: [Link]@[Link]; Tel: +81-50-3140-6958
Abstract layer transistor pixel stacked CMOS image
Herein, we demonstrate the development of a sensor (“2-Layer Pixel”) has been proposed
2-Layer Transistor Pixel stacked CMOS as a promising technology for capturing
image sensor (CIS) that possesses a high full- images with low noise and high D-range and
well capacity (FWC) and low random noise achieving Pixel shrinkage in CMOS image
(RN). A high FWC was achieved by sensors. [1-2] Schematic diagrams of the 2-
increasing the photodiode (PD) volume by Layer Pixel are shown in Figs. 1 and 2.
fabricating PDs and pixel transistors on The 2-Layer Pixel comprises an Si layer on
different silicon (Si) layers in a 3D sequential which the PDs and transfer gates are
integration process and introducing a single arranged. the second layer contains t pixel
vertical gate (SVG). Buried sublocal transistors, such as amplifier transistors,
connections (BSCs) that connect multiple select gates, reset gates, and deep contacts, to
floating diffusions (FD) and Pixel FinFETs connect the PDs and pixel transistors.
were introduced to improve the conversion Additionally, full trench isolations (FTIs) are
gain and random noise (RN). We have formed to separate the pixels. In a previous
demonstrated a 2-Layer Pixel with a 0.6 µm study, we developed a three-dimensional
pixel with an RN of 0.99, an FWC of 8000e-, (3D) sequential integration process to realize
and a dynamic-range of 78.1 dB. the 2-Layer Pixel. [2]
This paper presents a 2-Layer Pixel with a
0.6 µm Pixel by introducing a single vertical
Ⅰ. Introduction
transfer gate (SVG), buried sublocal
Ensuring high dynamic range (D-range) for connections (BSCs), and Pixel FinFETs.
pixel shrinkage is important for image
capture. Pixel shrinkage makes it difficult to
ensure a high FWC owing to the inability to
secure PD area and low noise because of the
size reduction of the pixel transistors. A two-
which the contact area changes from the Si
Ⅱ. Improvement of FWC
surface to the Si sidewall, as shown in Fig.
The major performance requirements for 4(b). Compared with SCs, BSCs can be
PDs and transfer gate (TRG) are high FWC separated from TGs and the capacitance of
with no-lag and no-blooming. In this device, TGs can be lowered. By optimizing the
the PDs were completely separated by layout and depth of the BSCs, the FD
introducing full trench isolation (FTI) in the capacitance was reduced by 46%, as shown
1st Si Layer that formed the PDs, resulting in in Fig. 5(a). The BSCs exhibited Ohmic
a structure with no-blooming. TRG conductivity, and the resistance is plotted in
optimization is performed only for no-lag and Fig. 5(b). To shrink the FD-sharing unit from
FWC, and the degree of freedom of the TRG 2x4 to 2x2, we adopted Pixel-FinFETs.
design are improved compared with the case Introducing BSCs and changing the FD
where FTI is not applied. The 2-Layer Pixel sharing unit increased the conversion gain by
structure enlarges the TRG layout area as shown 2.26 times and decreased the RN by 67%, as
in Fig. 3(a-b). The introduction of SVG shown in Fig. 6(a)and(b).
expands the area available for TRG placement
because it causes a change in the PD V. Conclusions
configuration which eliminates the need for a We fabricated a 2-Layer Pixel with 0.6 μm
shallow PD to achieve a high FWC and no-lag, Pixel, as shown in Fig. 7. Figure 8 shows the
as shown in Fig. 3(b-c). An FWC of 8000e- relationship between the pixel size and D-
was achieved with the SVG by optimizing its range, wherein the FWC and RN of PD CISs
geometry and placement. reported in previous studies [3-7] are
compared with those obtained in this study.
The performance parameters and comparison
Ⅲ. Improvement of RN
with prior studies are summarized in Table Ⅰ.
Reducing the FD capacitance is important for
improving RN and conversion gain. BSCs Reference
were introduced to reduce the diffusion layer [1] K. Nakazawa et al, IEDM, 2021
capacitance, and Pixel FinFETs was [2] K. Zaitsu et al, VLSI, 2022
introduced to shrink the FD sharing unit. [3] Y. Oh et al, IEDM, 2020
In the conventional 2-Layer-Pixels, SCs are [4] H. Kim et al, ISSCC, 2020
used to connect multiple floating diffusions. [5] J. Park et al, ISSCC, 2021
SCs are structures formed between 1st-Layer [6] J. Yun et al, VLSI, 2022
and 2nd-Layer, which contacts to the Si [7] S. Park et al, ISSCC, 2022
surface of the 1st layer and have ohmic
conductivity. The BSCs are structures in
Fig. 1 Schematics of the 2-Layer Pixel based on a three-
dimensional sequential integration process [1]
Fig. 4 Design optimization based on sublocal
connections to connect multiple floating diffusions
(FDs). (a, b) Schematics of device structures (a) with
the sublocal connections [2] and (b) with the buried
sublocal connections.
Fig. 2 Cross-sectional structure of the photodiode (PD)
and pixel transistor.
Fig. 3(a―c) Schematics of enlargement TG layout area
by 2-Layer Pixel structure and the introduction of SVG
Fig. 5 (a) Comparison of FD Capacitance between the 2-
Layer Pixels with the buried sublocal connections and
the sublocal connections. (b) Resistance of the buried
sublocal connections.
Fig. 7 Relationships between the pixel size and D-range
in this work compared with those in previous studies. [3-
7] D-range=20*log10(FWC/RN)
Table. 1 Performance comparison table
Fig. 5 (a) Comparison of conversion gain and random
noise between FD sharing units and contacts. (b)
Comparison of RN histogram between FD Sharing units
and contacts.
Fig. 6 Cross-sectional image of the 2-Layer Pixel with
0.6 μm PDs