BVM ENGINEERING COLLEGE [AN AUTONOMOUS INSTITUTION]
204CP: COMPUTER ORGANIZATION AND ARCHITECTURE
CREDITS - 5 (Lc , Tc , Pc : 4, 0, 1 )
2nd Year, B. Tech. (Computer Engineering)
Course Objective: To impart knowledge of the basic structure of digital computer, its operation,
design of basic processors, memory organization and processor interface with various memory &
input/output devices.
Teaching and Assessment Scheme:
Teaching Scheme
Credits Assessment Scheme Total
(Hours per Week)
Marks
Theory Practical
L T P C
ESE CE ESE CE
150
4 0 2 5 60 40 20 30
Course Contents:
Unit Topics Teaching
No. Hours
1 Basic Structure of Computers: 05
Block Diagram of General Purpose Computers; Detailed Understanding of
Each Functional Unit; Data Transfer Across Bus between registers and
memory; Simple Bus Structures; Details of Address; Control and Data Bus
with Interfacing
2 Instruction Set: 15
Instruction format; Addressing Modes. Instruction Set of a Simple Real
World Microprocessor, Covering Data Transfer instructions; Arithmetic &
Logical instructions; Branching instructions; Stack & Subroutine;
Interfacing of memory & I/O
3 Central Processor Unit Design: 08
Single Bus Architecture; Detailed Design of Execution Unit Using
Hardwired Control as Well As Microprogrammed Control; Horizontal and
Vertical Microinstructions; Concept of Nano-programming; Introduction to
RISC and CISC Architectures
4 Arithmetic Processor Design: 05
Addition; Subtraction; Multiplication and Division Algorithms in Signed
Binary Arithmetic for Fixed and Floating Point Representations and
Related Design Standards and Issues
5 Memory and Input-Output Organization: 13
Types of Memory; Memory Hierarchies; Organization of Static and
Dynamic Semiconductor Memories; Types of ROM; Cache Organization:
Direct, Associative and set associative; Device Interfacing and Selection;
Memory and I/O Mapped I/Os; Modes of Data Transfer-Programmed;
Interrupt and DMA Driven I/O-Interrupt Types and Priority Schemes;
Synchronous and Asynchronous Data Transfer
Unit Topics Teaching
No. Hours
6 Pipeline & Superscalar architecture: 10
Pipelining, basic concepts; Hazards, types of hazards, ways to overcome
the hazards; Superscalar architecture, instruction issue policies, anti and
output dependencies, Architecture of Very Long Instruction Word (VLIW)
processors, Multithreading, Interleaved, Blocked, Simultaneous and Chip
Multithreading; Multicore architecture
Total 56
Some of the above or related topics may also be covered through – Self Learning or Co-
Curricular activities (like Workshops / Peer Learning / Professor of Practice / Expert talks)
List of References:
1. Hamacher, Vranesic, Zaky, “Computer Organization”, McGraw Hill
2. M. Morris Mano, “Computer System Architecture”, Pearson Education
3. N D Jotwani, “Computer system organization”, McGraw Hill
4. V Rajaraman, C Siva Murthy, “Parallel Computers Architecture and Programming, PHI
5. William Stallings, “ Computer Organization and Architecture : Designing for Performance,
Pearson Education India
6. [Link], “Microprocessor Architecture, Programming and Applications with 8085”,
Penram International
7. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The
hardware/software interface, Morgan Kaufmann.
Course Outcomes (COs):
After successful completion of the course, the student will be able to:
1. Explain the organization and functionality of the control unit, arithmetic and logic unit
(ALU), memory unit, and I/O unit in a computer system.
2. Apply knowledge of the processor’s internal registers and operations for assembly
programming to provide solutions of given problems
3. Compare execution time of instructions in terms of machine cycles and T states
4. Design and analyze a basic Central Processing Unit (CPU) architecture, incorporating
essential components and functionalities.
5. Design the interfacing of memory and I/O modules with the CPU, incorporating interrupt-
driven mechanisms and Direct Memory Access (DMA) for efficient data transfer
6. Analyze and compare the performance improvements in modern computer architectures,
including pipelining, superscalar execution, multithreading, and multicore processing, to
assess their impact on computational efficiency and scalability